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armv8/ls1088a: configure PMU's PCTBENR to enable WDT

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The SP805-WDT module on LS1088A requires configuration of PMU's
PCTBENR register to enable watchdog counter decrement and reset
signal generation. The watchdog clock needs to be enabled first.

Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>
This commit is contained in:
Zhang Ying-22455 2018-01-09 16:25:46 +08:00 committed by York Sun
parent a2bbfc5480
commit 958b2ed526
1 changed files with 2 additions and 2 deletions
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4
arch/arm/cpu/armv8/fsl-layerscape/cpu.c
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@ -578,7 +578,7 @@ int timer_init(void)
#ifdef CONFIG_FSL_LSCH3
u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
#endif
#ifdef CONFIG_ARCH_LS2080A
#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
u32 __iomem *pctbenr = (u32 *)FSL_PMU_PCTBENR_OFFSET;
u32 svr_dev_id;
#endif
@ -597,7 +597,7 @@ int timer_init(void)
out_le32(cltbenr, 0xf);
#endif
#ifdef CONFIG_ARCH_LS2080A
#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A)
/*
* In certain Layerscape SoCs, the clock for each core's
* has an enable bit in the PMU Physical Core Time Base Enable