ARM: MediaTek: Add support for MediaTek MT8512 SoC
Add support for MediaTek MT8512 SoC. This include the file that will initialize the SoC after boot and its device tree. Signed-off-by: mingming lee <mingming.lee@mediatek.com>
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mingming lee
Tom Rini
parent
0c0859cf2d
commit
953bb4c3ce
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@ -0,0 +1,115 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright (C) 2019 MediaTek Inc.
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* Author: Mingming Lee <mingming.lee@mediatek.com>
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*
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*/
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#include <dt-bindings/clock/mt8512-clk.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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compatible = "mediatek,mt8512";
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interrupt-parent = <&sysirq>;
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#address-cells = <1>;
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#size-cells = <1>;
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gic: interrupt-controller@c000000 {
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compatible = "arm,gic-v3";
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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interrupt-controller;
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reg = <0xc000000 0x40000>, /* GICD */
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<0xc080000 0x200000>; /* GICR */
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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topckgen: clock-controller@10000000 {
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compatible = "mediatek,mt8512-topckgen";
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reg = <0x10000000 0x1000>;
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#clock-cells = <1>;
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};
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topckgen_cg: clock-controller-cg@10000000 {
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compatible = "mediatek,mt8512-topckgen-cg";
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reg = <0x10000000 0x1000>;
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#clock-cells = <1>;
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};
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infracfg: clock-controller@10001000 {
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compatible = "mediatek,mt8512-infracfg";
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reg = <0x10001000 0x1000>;
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#clock-cells = <1>;
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};
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pinctrl: pinctrl@10005000 {
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compatible = "mediatek,mt8512-pinctrl";
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reg = <0x10005000 0x1000>;
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gpio: gpio-controller {
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gpio-controller;
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#gpio-cells = <2>;
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};
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};
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watchdog0: watchdog@10007000 {
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compatible = "mediatek,wdt";
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reg = <0x10007000 0x1000>;
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interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_FALLING>;
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#reset-cells = <1>;
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status = "disabled";
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timeout-sec = <60>;
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reset-on-timeout;
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};
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timer0: apxgpt@10008000 {
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compatible = "mediatek,timer";
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reg = <0x10008000 0x1000>;
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interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_SYS_26M_D2>,
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<&topckgen CLK_TOP_CLK32K>,
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<&infracfg CLK_INFRA_APXGPT>;
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clock-names = "clk13m",
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"clk32k",
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"bus";
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};
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apmixedsys: clock-controller@1000c000 {
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compatible = "mediatek,mt8512-apmixedsys";
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reg = <0x1000c000 0x1000>;
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#clock-cells = <1>;
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};
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sysirq: interrupt-controller@10200a80 {
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compatible = "mediatek,sysirq";
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interrupt-controller;
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#interrupt-cells = <3>;
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interrupt-parent = <&gic>;
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reg = <0x10200a80 0x50>;
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};
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uart0: serial@11002000 {
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compatible = "mediatek,hsuart";
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reg = <0x11002000 0x1000>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_CLK26M>,
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<&infracfg CLK_INFRA_UART0>;
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clock-names = "baud", "bus";
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status = "disabled";
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};
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mmc0: mmc@11230000 {
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compatible = "mediatek,mt8512-mmc";
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reg = <0x11230000 0x1000>,
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<0x11cd0000 0x1000>;
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interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
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<&infracfg CLK_INFRA_MSDC0>,
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<&infracfg CLK_INFRA_MSDC0_SRC>;
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clock-names = "source", "hclk", "source_cg";
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status = "disabled";
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};
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};
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@ -6,6 +6,10 @@ config SYS_SOC
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config SYS_VENDOR
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default "mediatek"
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config MT8512
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bool "MediaTek MT8512 SoC"
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default n
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choice
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prompt "MediaTek board select"
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@ -29,6 +33,16 @@ config TARGET_MT7629
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including DDR3, crypto engine, 3x3 11n/ac Wi-Fi, Gigabit Ethernet,
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switch, USB3.0, PCIe, UART, SPI, I2C and PWM.
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config TARGET_MT8512
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bool "MediaTek MT8512 M1 Board"
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select ARM64
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select MT8512
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help
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The MediaTek MT8512 is a ARM64-based SoC with a quad-core Cortex-A53.
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including UART, SPI, USB2.0 and OTG, SD and MMC cards, NAND, PWM,
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Ethernet, IR TX/RX, I2C, I2S, S/PDIF, and built-in Wi-Fi / Bluetooth combo
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chip and several DDR3 and DDR4 options.
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config TARGET_MT8516
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bool "MediaTek MT8516 SoC"
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select ARM64
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@ -51,6 +65,7 @@ endchoice
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source "board/mediatek/mt7623/Kconfig"
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source "board/mediatek/mt7629/Kconfig"
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source "board/mediatek/mt8512/Kconfig"
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source "board/mediatek/mt8518/Kconfig"
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source "board/mediatek/pumpkin/Kconfig"
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@ -3,6 +3,7 @@
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obj-y += cpu.o
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obj-$(CONFIG_SPL_BUILD) += spl.o
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obj-$(CONFIG_MT8512) += mt8512/
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obj-$(CONFIG_TARGET_MT7623) += mt7623/
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obj-$(CONFIG_TARGET_MT7629) += mt7629/
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obj-$(CONFIG_TARGET_MT8516) += mt8516/
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@ -0,0 +1,4 @@
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# SPDX-License-Identifier: GPL-2.0
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obj-y += init.o
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obj-y += lowlevel_init.o
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@ -0,0 +1,78 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Configuration for MediaTek MT8512 SoC
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*
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* Copyright (C) 2019 MediaTek Inc.
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* Author: Mingming Lee <mingming.lee@mediatek.com>
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*/
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#include <clk.h>
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#include <common.h>
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#include <dm.h>
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#include <fdtdec.h>
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#include <ram.h>
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#include <wdt.h>
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#include <asm/arch/misc.h>
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#include <asm/armv8/mmu.h>
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#include <asm/sections.h>
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#include <dm/uclass.h>
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#include <dt-bindings/clock/mt8512-clk.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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return fdtdec_setup_mem_size_base();
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}
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phys_size_t get_effective_memsize(void)
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{
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/* limit stack below tee reserve memory */
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return gd->ram_size - 6 * SZ_1M;
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}
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int dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = gd->ram_base;
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gd->bd->bi_dram[0].size = get_effective_memsize();
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return 0;
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}
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void reset_cpu(ulong addr)
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{
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struct udevice *watchdog_dev = NULL;
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if (uclass_get_device_by_seq(UCLASS_WDT, 0, &watchdog_dev))
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if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev))
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psci_system_reset();
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wdt_expire_now(watchdog_dev, 0);
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}
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int print_cpuinfo(void)
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{
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debug("CPU: MediaTek MT8512\n");
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return 0;
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}
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static struct mm_region mt8512_mem_map[] = {
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{
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/* DDR */
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.virt = 0x40000000UL,
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.phys = 0x40000000UL,
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.size = 0x40000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
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}, {
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.virt = 0x00000000UL,
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.phys = 0x00000000UL,
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.size = 0x40000000UL,
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.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
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PTE_BLOCK_NON_SHARE |
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PTE_BLOCK_PXN | PTE_BLOCK_UXN
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}, {
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0,
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}
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};
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struct mm_region *mem_map = mt8512_mem_map;
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@ -0,0 +1,32 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (C) 2019 MediaTek Inc.
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* Author: Mingming Lee <mingming.lee@mediatek.com>
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*/
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/*
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* Switch from AArch64 EL2 to AArch32 EL2
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* @param inputs:
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* x0: argument, zero
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* x1: machine nr
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* x2: fdt address
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* x3: input argument
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* x4: kernel entry point
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* @param outputs for secure firmware:
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* x0: function id
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* x1: kernel entry point
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* x2: machine nr
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* x3: fdt address
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*/
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.global armv8_el2_to_aarch32
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armv8_el2_to_aarch32:
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mov x3, x2
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mov x2, x1
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mov x1, x4
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mov x4, #0
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/* Define in src\bsp\trustzone\atf\v1.2\ */
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/* mt8xxx\plat\mediatek\common\sip_svc.h */
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/* MTK_SIP_KERNEL_BOOT_AARCH64 for U-BOOT-64 to KERNEL*/
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ldr x0, =0xC2000200
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SMC #0
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ret
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