mirror of
https://github.com/brain-hackers/u-boot-brain
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dm: spi: xilinx_spi: Convert to driver model
This converts the xilinx spi driver to use the driver model. Signed-off-by: Jagan Teki <jteki@openedev.com> Acked-by: Simon Glass <sjg@chromium.org> Cc: Michal Simek <michal.simek@xilinx.com>
This commit is contained in:
parent
89cab97e98
commit
9505c36ed0
@ -4,6 +4,7 @@
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* Supports 8 bit SPI transfers only, with or w/o FIFO
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* Supports 8 bit SPI transfers only, with or w/o FIFO
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*
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*
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* Based on bfin_spi.c, by way of altera_spi.c
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* Based on bfin_spi.c, by way of altera_spi.c
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* Copyright (c) 2015 Jagan Teki <jteki@openedev.com>
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* Copyright (c) 2012 Stephan Linz <linz@li-pro.net>
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* Copyright (c) 2012 Stephan Linz <linz@li-pro.net>
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* Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca>
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* Copyright (c) 2010 Graeme Smecher <graeme.smecher@mail.mcgill.ca>
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* Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw>
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* Copyright (c) 2010 Thomas Chou <thomas@wytron.com.tw>
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@ -14,6 +15,8 @@
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#include <config.h>
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#include <config.h>
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#include <common.h>
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <malloc.h>
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#include <malloc.h>
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#include <spi.h>
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#include <spi.h>
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@ -79,7 +82,7 @@
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#endif
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#endif
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/* xilinx spi register set */
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/* xilinx spi register set */
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struct xilinx_spi_reg {
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struct xilinx_spi_regs {
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u32 __space0__[7];
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u32 __space0__[7];
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u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */
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u32 dgier; /* Device Global Interrupt Enable Register (DGIER) */
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u32 ipisr; /* IP Interrupt Status Register (IPISR) */
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u32 ipisr; /* IP Interrupt Status Register (IPISR) */
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@ -97,113 +100,75 @@ struct xilinx_spi_reg {
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u32 spirfor; /* SPI Receive FIFO Occupancy Register (SPIRFOR) */
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u32 spirfor; /* SPI Receive FIFO Occupancy Register (SPIRFOR) */
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};
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};
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/* xilinx spi slave */
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/* xilinx spi priv */
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struct xilinx_spi_slave {
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struct xilinx_spi_priv {
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struct spi_slave slave;
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struct xilinx_spi_regs *regs;
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struct xilinx_spi_reg *regs;
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unsigned int freq;
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unsigned int freq;
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unsigned int mode;
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unsigned int mode;
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};
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};
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static inline struct xilinx_spi_slave *to_xilinx_spi_slave(
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struct spi_slave *slave)
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{
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return container_of(slave, struct xilinx_spi_slave, slave);
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}
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static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST;
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static unsigned long xilinx_spi_base_list[] = CONFIG_SYS_XILINX_SPI_LIST;
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int spi_cs_is_valid(unsigned int bus, unsigned int cs)
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static int xilinx_spi_probe(struct udevice *bus)
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{
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{
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return bus < ARRAY_SIZE(xilinx_spi_base_list) && cs < 32;
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struct xilinx_spi_priv *priv = dev_get_priv(bus);
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}
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struct xilinx_spi_regs *regs = priv->regs;
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void spi_cs_activate(struct spi_slave *slave)
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priv->regs = (struct xilinx_spi_regs *)xilinx_spi_base_list[bus->seq];
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{
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struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
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writel(SPISSR_ACT(slave->cs), &xilspi->regs->spissr);
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writel(SPISSR_RESET_VALUE, ®s->srr);
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}
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void spi_cs_deactivate(struct spi_slave *slave)
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{
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struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
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writel(SPISSR_OFF, &xilspi->regs->spissr);
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}
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void spi_init(void)
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{
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/* do nothing */
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}
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struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
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unsigned int max_hz, unsigned int mode)
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{
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struct xilinx_spi_slave *xilspi;
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if (!spi_cs_is_valid(bus, cs)) {
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printf("XILSPI error: unsupported bus %d / cs %d\n", bus, cs);
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return NULL;
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}
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xilspi = spi_alloc_slave(struct xilinx_spi_slave, bus, cs);
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if (!xilspi) {
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printf("XILSPI error: malloc of SPI structure failed\n");
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return NULL;
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}
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xilspi->regs = (struct xilinx_spi_reg *)xilinx_spi_base_list[bus];
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xilspi->freq = max_hz;
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xilspi->mode = mode;
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debug("spi_setup_slave: bus:%i cs:%i base:%p mode:%x max_hz:%d\n",
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bus, cs, xilspi->regs, xilspi->mode, xilspi->freq);
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writel(SPISSR_RESET_VALUE, &xilspi->regs->srr);
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return &xilspi->slave;
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}
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void spi_free_slave(struct spi_slave *slave)
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{
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struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
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free(xilspi);
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}
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int spi_claim_bus(struct spi_slave *slave)
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{
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struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
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u32 spicr;
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debug("spi_claim_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
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writel(SPISSR_OFF, &xilspi->regs->spissr);
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spicr = XILSPI_SPICR_DFLT_ON;
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if (xilspi->mode & SPI_LSB_FIRST)
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spicr |= SPICR_LSB_FIRST;
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if (xilspi->mode & SPI_CPHA)
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spicr |= SPICR_CPHA;
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if (xilspi->mode & SPI_CPOL)
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spicr |= SPICR_CPOL;
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if (xilspi->mode & SPI_LOOP)
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spicr |= SPICR_LOOP;
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writel(spicr, &xilspi->regs->spicr);
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return 0;
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return 0;
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}
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}
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void spi_release_bus(struct spi_slave *slave)
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static void spi_cs_activate(struct udevice *dev, uint cs)
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{
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{
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struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
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struct udevice *bus = dev_get_parent(dev);
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struct xilinx_spi_priv *priv = dev_get_priv(bus);
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struct xilinx_spi_regs *regs = priv->regs;
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debug("spi_release_bus: bus:%i cs:%i\n", slave->bus, slave->cs);
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writel(SPISSR_ACT(cs), ®s->spissr);
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writel(SPISSR_OFF, &xilspi->regs->spissr);
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writel(XILSPI_SPICR_DFLT_OFF, &xilspi->regs->spicr);
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}
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}
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int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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static void spi_cs_deactivate(struct udevice *dev)
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void *din, unsigned long flags)
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{
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{
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struct xilinx_spi_slave *xilspi = to_xilinx_spi_slave(slave);
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struct udevice *bus = dev_get_parent(dev);
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struct xilinx_spi_priv *priv = dev_get_priv(bus);
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struct xilinx_spi_regs *regs = priv->regs;
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writel(SPISSR_OFF, ®s->spissr);
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}
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static int xilinx_spi_claim_bus(struct udevice *dev)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct xilinx_spi_priv *priv = dev_get_priv(bus);
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struct xilinx_spi_regs *regs = priv->regs;
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writel(SPISSR_OFF, ®s->spissr);
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writel(XILSPI_SPICR_DFLT_ON, ®s->spicr);
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return 0;
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}
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static int xilinx_spi_release_bus(struct udevice *dev)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct xilinx_spi_priv *priv = dev_get_priv(bus);
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struct xilinx_spi_regs *regs = priv->regs;
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writel(SPISSR_OFF, ®s->spissr);
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writel(XILSPI_SPICR_DFLT_OFF, ®s->spicr);
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return 0;
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}
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static int xilinx_spi_xfer(struct udevice *dev, unsigned int bitlen,
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const void *dout, void *din, unsigned long flags)
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{
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struct udevice *bus = dev_get_parent(dev);
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struct xilinx_spi_priv *priv = dev_get_priv(bus);
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struct xilinx_spi_regs *regs = priv->regs;
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struct dm_spi_slave_platdata *slave_plat = dev_get_parent_platdata(dev);
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/* assume spi core configured to do 8 bit transfers */
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/* assume spi core configured to do 8 bit transfers */
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unsigned int bytes = bitlen / XILSPI_MAX_XFER_BITS;
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unsigned int bytes = bitlen / XILSPI_MAX_XFER_BITS;
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const unsigned char *txp = dout;
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const unsigned char *txp = dout;
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@ -212,7 +177,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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unsigned global_timeout;
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unsigned global_timeout;
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debug("spi_xfer: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n",
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debug("spi_xfer: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n",
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slave->bus, slave->cs, bitlen, bytes, flags);
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bus->seq, slave_plat->cs, bitlen, bytes, flags);
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if (bitlen == 0)
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if (bitlen == 0)
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goto done;
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goto done;
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@ -225,8 +190,8 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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}
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}
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/* empty read buffer */
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/* empty read buffer */
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while (rxecount && !(readl(&xilspi->regs->spisr) & SPISR_RX_EMPTY)) {
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while (rxecount && !(readl(®s->spisr) & SPISR_RX_EMPTY)) {
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readl(&xilspi->regs->spidrr);
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readl(®s->spidrr);
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rxecount--;
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rxecount--;
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}
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}
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@ -236,11 +201,11 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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}
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}
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if (flags & SPI_XFER_BEGIN)
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if (flags & SPI_XFER_BEGIN)
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spi_cs_activate(slave);
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spi_cs_activate(dev, slave_plat->cs);
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/* at least 1usec or greater, leftover 1 */
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/* at least 1usec or greater, leftover 1 */
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global_timeout = xilspi->freq > XILSPI_MAX_XFER_BITS * 1000000 ? 2 :
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global_timeout = priv->freq > XILSPI_MAX_XFER_BITS * 1000000 ? 2 :
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(XILSPI_MAX_XFER_BITS * 1000000 / xilspi->freq) + 1;
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(XILSPI_MAX_XFER_BITS * 1000000 / priv->freq) + 1;
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while (bytes--) {
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while (bytes--) {
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unsigned timeout = global_timeout;
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unsigned timeout = global_timeout;
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@ -249,8 +214,8 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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debug("spi_xfer: tx:%x ", d);
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debug("spi_xfer: tx:%x ", d);
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/* write out and wait for processing (receive data) */
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/* write out and wait for processing (receive data) */
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writel(d & SPIDTR_8BIT_MASK, &xilspi->regs->spidtr);
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writel(d & SPIDTR_8BIT_MASK, ®s->spidtr);
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while (timeout && readl(&xilspi->regs->spisr)
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while (timeout && readl(®s->spisr)
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& SPISR_RX_EMPTY) {
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& SPISR_RX_EMPTY) {
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timeout--;
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timeout--;
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udelay(1);
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udelay(1);
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@ -262,7 +227,7 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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}
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}
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/* read Rx element and push into data in buffer */
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/* read Rx element and push into data in buffer */
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d = readl(&xilspi->regs->spidrr) & SPIDRR_8BIT_MASK;
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d = readl(®s->spidrr) & SPIDRR_8BIT_MASK;
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if (rxp)
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if (rxp)
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*rxp++ = d;
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*rxp++ = d;
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debug("spi_xfer: rx:%x\n", d);
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debug("spi_xfer: rx:%x\n", d);
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@ -270,7 +235,66 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
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done:
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done:
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if (flags & SPI_XFER_END)
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if (flags & SPI_XFER_END)
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spi_cs_deactivate(slave);
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spi_cs_deactivate(dev);
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return 0;
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return 0;
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}
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}
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static int xilinx_spi_set_speed(struct udevice *bus, uint speed)
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{
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struct xilinx_spi_priv *priv = dev_get_priv(bus);
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priv->freq = speed;
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debug("xilinx_spi_set_speed: regs=%p, mode=%d\n", priv->regs,
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priv->freq);
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return 0;
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}
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static int xilinx_spi_set_mode(struct udevice *bus, uint mode)
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{
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struct xilinx_spi_priv *priv = dev_get_priv(bus);
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struct xilinx_spi_regs *regs = priv->regs;
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uint32_t spicr;
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spicr = readl(®s->spicr);
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if (priv->mode & SPI_LSB_FIRST)
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spicr |= SPICR_LSB_FIRST;
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if (priv->mode & SPI_CPHA)
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spicr |= SPICR_CPHA;
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if (priv->mode & SPI_CPOL)
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spicr |= SPICR_CPOL;
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if (priv->mode & SPI_LOOP)
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spicr |= SPICR_LOOP;
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writel(spicr, ®s->spicr);
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priv->mode = mode;
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debug("xilinx_spi_set_mode: regs=%p, mode=%d\n", priv->regs,
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priv->mode);
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return 0;
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}
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static const struct dm_spi_ops xilinx_spi_ops = {
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.claim_bus = xilinx_spi_claim_bus,
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.release_bus = xilinx_spi_release_bus,
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.xfer = xilinx_spi_xfer,
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.set_speed = xilinx_spi_set_speed,
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.set_mode = xilinx_spi_set_mode,
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};
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static const struct udevice_id xilinx_spi_ids[] = {
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{ .compatible = "xlnx,xilinx-spi" },
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{ }
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};
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U_BOOT_DRIVER(xilinx_spi) = {
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.name = "xilinx_spi",
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.id = UCLASS_SPI,
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.of_match = xilinx_spi_ids,
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.ops = &xilinx_spi_ops,
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.priv_auto_alloc_size = sizeof(struct xilinx_spi_priv),
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.probe = xilinx_spi_probe,
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};
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