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sh: ms7750se: Remove the board

Browse Source 
Last change to this board was done in 2016, has no prospects of
ever being converted to DM, drop it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Chris Brandt <chris.brandt@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Vladimir Zapolskiy <vz@mleia.com>
Cc: Yoshihiro Shimoda <shimoda.yoshihiro.uh@renesas.com>
This commit is contained in:
Marek Vasut 2019-05-20 03:19:44 +02:00 committed by Marek Vasut
parent 6b371a7a4b
commit 94bb4492e1
8 changed files with 0 additions and 290 deletions
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5
arch/sh/Kconfig
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@ -21,10 +21,6 @@ choice
prompt "Target select"
optional
config TARGET_MS7750SE
bool "SolutionEngine 7750"
select CPU_SH4
config TARGET_AP_SH4A_4A
bool "ALPHAPROJECT AP-SH4A-4A"
select CPU_SH4A
@ -76,7 +72,6 @@ config SYS_CPU
source "arch/sh/lib/Kconfig"
source "board/alphaproject/ap_sh4a_4a/Kconfig"
source "board/ms7750se/Kconfig"
source "board/renesas/MigoR/Kconfig"
source "board/renesas/ap325rxa/Kconfig"
source "board/renesas/r0p7734/Kconfig"

9
board/ms7750se/Kconfig
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@ -1,9 +0,0 @@
if TARGET_MS7750SE
config SYS_BOARD
default "ms7750se"
config SYS_CONFIG_NAME
default "ms7750se"
endif

7
board/ms7750se/MAINTAINERS
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@ -1,7 +0,0 @@
MS7750SE BOARD
M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
S: Maintained
F: board/ms7750se/
F: include/configs/ms7750se.h
F: configs/ms7750se_defconfig

7
board/ms7750se/Makefile
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@ -1,7 +0,0 @@
# SPDX-License-Identifier: GPL-2.0+
#
# Copyright (C) 2007
# Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
obj-y := ms7750se.o
extra-y += lowlevel_init.o

141
board/ms7750se/lowlevel_init.S
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@ -1,141 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
modified from SH-IPL+g
Renesaso SuperH / Solution Enginge MS775xSE01 BSC setting.
Support CPU : SH7750/SH7750S/SH7750R/SH7751/SH7751R
Coyright (c) 2007 Nobuhiro Iwamatsu <iwmatsu@nigauri.org>
*/
#include <config.h>
#include <asm/processor.h>
#include <asm/macro.h>
#ifdef CONFIG_CPU_SH7751
#define BCR2_D_VALUE 0x2FFC /* Area 1-6 width: 32/32/32/32/32/16 */
#define WCR1_D_VALUE 0x02770771 /* DMA:0 A6:2 A3:0 A0:1 Others:15 */
#ifdef CONFIG_MARUBUN_PCCARD
#define WCR2_D_VALUE 0xFFFE4FE7 /* A6:15 A6B:7 A5:15 A5B:7 A4:15
A3:2 A2:15 A1:15 A0:6 A0B:7 */
#else /* CONFIG_MARUBUN_PCCARD */
#define WCR2_D_VALUE 0x7FFE4FE7 /* A6:3 A6B:7 A5:15 A5B:7 A4:15
A3:2 A2:15 A1:15 A0:6 A0B:7 */
#endif /* CONFIG_MARUBUN_PCCARD */
#define WCR3_D_VALUE 0x01777771 /* A6: 0-1 A5: 1-3 A4: 1-3 A3: 1-3
A2: 1-3 A1: 1-3 A0: 0-1 */
#define RTCOR_D_VALUE 0xA50D /* Write code A5, data 0D (~15us?) */
#define SDMR3_ADDRESS 0xFF940088 /* SDMR3 address on 32-bit bus */
#define MCR_D1_VALUE 0x100901B4 /* SDRAM 32-bit, CAS/RAS Refresh, .. */
#define MCR_D2_VALUE 0x500901B4 /* Same w/MRSET now 1 (mode reg cmd) */
#else /* CONFIG_CPU_SH7751 */
#define BCR2_D_VALUE 0x2E3C /* Area 1-6 width: 32/32/64/16/32/16 */
#define WCR1_D_VALUE 0x02720777 /* DMA:0 A6:2 A4:2 A3:0 Others:15 */
#define WCR2_D_VALUE 0xFFFE4FFF /* A6:15 A6B:7 A5:15 A5B:7 A4:15
A3:2 A2:15 A1:15 A0:15 A0B:7 */
#define WCR3_D_VALUE 0x01717771 /* A6: 0-1 A5: 1-3 A4: 0-1 A3: 1-3
A2: 1-3 A1: 1-3 A0: 0-1 */
#define RTCOR_D_VALUE 0xA510 /* Write code A5, data 10 (~15us?) */
#define SDMR3_ADDRESS 0xFF940110 /* SDMR3 address on 64-bit bus */
#define MCR_D1_VALUE 0x8801001C /* SDRAM 64-bit, CAS/RAS Refresh, .. */
#define MCR_D2_VALUE 0xC801001C /* Same w/MRSET now 1 (mode reg cmd) */
#endif /* CONFIG_CPU_SH7751 */
.global lowlevel_init
.text
.align 2
lowlevel_init:
write32 CCR_A, CCR_D_DISABLE
init_bsc:
write16 FRQCR_A, FRQCR_D
write32 BCR1_A, BCR1_D
write16 BCR2_A, BCR2_D
write32 WCR1_A, WCR1_D
write32 WCR2_A, WCR2_D
write32 WCR3_A, WCR3_D
write32 MCR_A, MCR_D1
/* Set SDRAM mode */
write8 SDMR3_A, SDMR3_D
! Do you need PCMCIA setting?
! If so, please add the lines here...
write16 RTCNT_A, RTCNT_D
write16 RTCOR_A, RTCOR_D
write16 RTCSR_A, RTCSR_D
write16 RFCR_A, RFCR_D
/* Wait DRAM refresh 30 times */
mov #30, r3
1:
mov.w @r1, r0
extu.w r0, r2
cmp/hi r3, r2
bf 1b
write32 MCR_A, MCR_D2
/* Set SDRAM mode */
write8 SDMR3_A, SDMR3_D
rts
nop
.align 2
CCR_A: .long CCR
CCR_D_DISABLE: .long 0x0808
FRQCR_A: .long FRQCR
FRQCR_D:
#ifdef CONFIG_CPU_TYPE_R
.word 0x0e1a /* 12:3:3 */
#else /* CONFIG_CPU_TYPE_R */
#ifdef CONFIG_GOOD_SESH4
.word 0x00e13 /* 6:2:1 */
#else
.word 0x00e23 /* 6:1:1 */
#endif
.align 2
#endif /* CONFIG_CPU_TYPE_R */
BCR1_A: .long BCR1
BCR1_D: .long 0x00000008 /* Area 3 SDRAM */
BCR2_A: .long BCR2
BCR2_D: .long BCR2_D_VALUE /* Bus width settings */
WCR1_A: .long WCR1
WCR1_D: .long WCR1_D_VALUE /* Inter-area or turnaround wait states */
WCR2_A: .long WCR2
WCR2_D: .long WCR2_D_VALUE /* Per-area access and burst wait states */
WCR3_A: .long WCR3
WCR3_D: .long WCR3_D_VALUE /* Address setup and data hold cycles */
RTCSR_A: .long RTCSR
RTCSR_D: .word 0xA518 /* RTCSR Write Code A5h Data 18h */
.align 2
RTCNT_A: .long RTCNT
RTCNT_D: .word 0xA500 /* RTCNT Write Code A5h Data 00h */
.align 2
RTCOR_A: .long RTCOR
RTCOR_D: .word RTCOR_D_VALUE /* Set refresh time (about 15us) */
.align 2
SDMR3_A: .long SDMR3_ADDRESS
SDMR3_D: .long 0x00
MCR_A: .long MCR
MCR_D1: .long MCR_D1_VALUE
MCR_D2: .long MCR_D2_VALUE
RFCR_A: .long RFCR
RFCR_D: .word 0xA400 /* RFCR Write Code A4h Data 00h */
.align 2

24
board/ms7750se/ms7750se.c
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@ -1,24 +0,0 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2007
* Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*/
#include <common.h>
#include <asm/processor.h>
int checkboard(void)
{
puts("BOARD: SH7750/SH7750S/SH7750R Solution Engine\n");
return 0;
}
int board_init(void)
{
return 0;
}
int board_late_init(void)
{
return 0;
}

32
configs/ms7750se_defconfig
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@ -1,32 +0,0 @@
CONFIG_SH=y
CONFIG_SYS_TEXT_BASE=0x8FFC0000
CONFIG_TARGET_MS7750SE=y
CONFIG_BOOTDELAY=-1
CONFIG_USE_BOOTARGS=y
CONFIG_BOOTARGS="console=ttySC0,38400"
# CONFIG_CMDLINE_EDITING is not set
# CONFIG_AUTO_COMPLETE is not set
# CONFIG_CMD_BDI is not set
# CONFIG_CMD_CONSOLE is not set
# CONFIG_CMD_BOOTD is not set
# CONFIG_CMD_RUN is not set
# CONFIG_CMD_IMI is not set
# CONFIG_CMD_XIMG is not set
# CONFIG_CMD_EDITENV is not set
# CONFIG_CMD_ENV_EXISTS is not set
# CONFIG_CMD_MEMORY is not set
# CONFIG_CMD_LOADB is not set
# CONFIG_CMD_LOADS is not set
# CONFIG_CMD_ECHO is not set
# CONFIG_CMD_ITEST is not set
# CONFIG_CMD_SOURCE is not set
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_MISC is not set
CONFIG_ENV_IS_IN_FLASH=y
# CONFIG_NET is not set
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_CFI=y
CONFIG_BAUDRATE=38400
CONFIG_SCIF_CONSOLE=y
CONFIG_USE_PRIVATE_LIBGCC=y

65
include/configs/ms7750se.h
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@ -1,65 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Configuation settings for the Hitachi Solution Engine 7750
*
* Copyright (C) 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
*/
#ifndef __MS7750SE_H
#define __MS7750SE_H
#define CONFIG_CPU_SH7750 1
/* #define CONFIG_CPU_SH7751 1 */
/* #define CONFIG_CPU_TYPE_R 1 */
#define __LITTLE_ENDIAN__ 1
#define CONFIG_DISPLAY_BOARDINFO
/*
* Command line configuration.
*/
#define CONFIG_CONS_SCIF1 1
#define CONFIG_ENV_OVERWRITE 1
/* SDRAM */
#define CONFIG_SYS_SDRAM_BASE (0x8C000000)
#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024)
#define CONFIG_SYS_PBSIZE 256
#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000)
/* NOR Flash */
/* #define CONFIG_SYS_FLASH_BASE (0xA1000000)*/
#define CONFIG_SYS_FLASH_BASE (0xA0000000)
#define CONFIG_SYS_MAX_FLASH_BANKS (1) /* Max number of
* Flash memory banks
*/
#define CONFIG_SYS_MAX_FLASH_SECT 142
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 4 * 1024 * 1024)
#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) /* Address of u-boot image in Flash */
#define CONFIG_SYS_MONITOR_LEN (128 * 1024)
#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Size of DRAM reserved for malloc() use */
#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
#define CONFIG_SYS_RX_ETH_BUFFER (8)
#undef CONFIG_SYS_FLASH_CFI_BROKEN_TABLE
#undef CONFIG_SYS_FLASH_QUIET_TEST
#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CONFIG_ENV_SECT_SIZE 0x20000
#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
#define CONFIG_SYS_FLASH_WRITE_TOUT 500
/* Board Clock */
#define CONFIG_SYS_CLK_FREQ 33333333
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#endif /* __MS7750SE_H */