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x86: ivybridge: Convert pch.c to use DM PCI API
Convert this file to use the driver model PCI API. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
This commit is contained in:
Simon Glass
Bin Meng
parent
fad12961b0
commit
9434c7a35d
@ -354,10 +354,10 @@ static void enable_clock_gating(struct udevice *pch)
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reg16 |= (1 << 2) | (1 << 11);
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dm_pci_write_config16(pch, GEN_PMCON_1, reg16);
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pch_iobp_update(0xEB007F07, ~0UL, (1 << 31));
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pch_iobp_update(0xEB004000, ~0UL, (1 << 7));
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pch_iobp_update(0xEC007F07, ~0UL, (1 << 31));
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pch_iobp_update(0xEC004000, ~0UL, (1 << 7));
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pch_iobp_update(pch, 0xEB007F07, ~0UL, (1 << 31));
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pch_iobp_update(pch, 0xEB004000, ~0UL, (1 << 7));
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pch_iobp_update(pch, 0xEC007F07, ~0UL, (1 << 31));
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pch_iobp_update(pch, 0xEC004000, ~0UL, (1 << 7));
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reg32 = readl(RCB_REG(CG));
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reg32 |= (1 << 31);
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@ -573,7 +573,7 @@ static int lpc_init_extra(struct udevice *dev)
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pch_power_options(pch);
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/* Initialize power management */
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switch (pch_silicon_type()) {
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switch (pch_silicon_type(pch)) {
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case PCH_TYPE_CPT: /* CougarPoint */
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cpt_pm_init(pch);
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break;
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@ -14,32 +14,34 @@
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static int pch_revision_id = -1;
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static int pch_type = -1;
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int pch_silicon_revision(void)
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int pch_silicon_revision(struct udevice *dev)
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{
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pci_dev_t dev;
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u8 val;
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dev = PCH_LPC_DEV;
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if (pch_revision_id < 0) {
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dm_pci_read_config8(dev, PCI_REVISION_ID, &val);
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pch_revision_id = val;
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}
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if (pch_revision_id < 0)
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pch_revision_id = x86_pci_read_config8(dev, PCI_REVISION_ID);
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return pch_revision_id;
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}
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int pch_silicon_type(void)
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int pch_silicon_type(struct udevice *dev)
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{
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pci_dev_t dev;
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u8 val;
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dev = PCH_LPC_DEV;
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if (pch_type < 0) {
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dm_pci_read_config8(dev, PCI_DEVICE_ID + 1, &val);
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pch_type = val;
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}
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if (pch_type < 0)
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pch_type = x86_pci_read_config8(dev, PCI_DEVICE_ID + 1);
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return pch_type;
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}
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int pch_silicon_supported(int type, int rev)
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int pch_silicon_supported(struct udevice *dev, int type, int rev)
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{
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int cur_type = pch_silicon_type();
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int cur_rev = pch_silicon_revision();
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int cur_type = pch_silicon_type(dev);
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int cur_rev = pch_silicon_revision(dev);
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switch (type) {
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case PCH_TYPE_CPT:
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@ -78,7 +80,8 @@ static inline int iobp_poll(void)
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return 0;
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}
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void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
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void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue,
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u32 orvalue)
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{
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u32 data;
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@ -86,7 +89,7 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
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writel(address, RCB_REG(IOBPIRI));
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/* READ OPCODE */
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if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
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if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0))
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writel(IOBPS_RW_BX, RCB_REG(IOBPS));
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else
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writel(IOBPS_READ_AX, RCB_REG(IOBPS));
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@ -109,7 +112,7 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue)
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data |= orvalue;
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/* WRITE OPCODE */
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if (pch_silicon_supported(PCH_TYPE_CPT, PCH_STEP_B0))
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if (pch_silicon_supported(dev, PCH_TYPE_CPT, PCH_STEP_B0))
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writel(IOBPS_RW_BX, RCB_REG(IOBPS));
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else
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writel(IOBPS_WRITE_AX, RCB_REG(IOBPS));
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@ -51,7 +51,7 @@ static void common_sata_init(struct udevice *dev, unsigned int port_map)
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dm_pci_write_config32(dev, 0x94, ((port_map ^ 0x3f) << 24) | 0x183);
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}
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static void bd82x6x_sata_init(struct udevice *dev)
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static void bd82x6x_sata_init(struct udevice *dev, struct udevice *pch)
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{
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unsigned int port_map, speed_support, port_tx;
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const void *blob = gd->fdt_blob;
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@ -170,11 +170,11 @@ static void bd82x6x_sata_init(struct udevice *dev)
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/* Set Gen3 Transmitter settings if needed */
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port_tx = fdtdec_get_int(blob, node, "intel,sata-port0-gen3-tx", 0);
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if (port_tx)
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pch_iobp_update(SATA_IOBP_SP0G3IR, 0, port_tx);
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pch_iobp_update(pch, SATA_IOBP_SP0G3IR, 0, port_tx);
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port_tx = fdtdec_get_int(blob, node, "intel,sata-port1-gen3-tx", 0);
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if (port_tx)
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pch_iobp_update(SATA_IOBP_SP1G3IR, 0, port_tx);
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pch_iobp_update(pch, SATA_IOBP_SP1G3IR, 0, port_tx);
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/* Additional Programming Requirements */
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sir_write(dev, 0x04, 0x00001600);
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@ -199,8 +199,8 @@ static void bd82x6x_sata_init(struct udevice *dev)
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sir_write(dev, 0xc8, 0x0c0c0c0c);
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sir_write(dev, 0xd4, 0x10000000);
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pch_iobp_update(0xea004001, 0x3fffffff, 0xc0000000);
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pch_iobp_update(0xea00408a, 0xfffffcff, 0x00000100);
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pch_iobp_update(pch, 0xea004001, 0x3fffffff, 0xc0000000);
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pch_iobp_update(pch, 0xea00408a, 0xfffffcff, 0x00000100);
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}
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static void bd82x6x_sata_enable(struct udevice *dev)
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@ -226,10 +226,19 @@ static void bd82x6x_sata_enable(struct udevice *dev)
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static int bd82x6x_sata_probe(struct udevice *dev)
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{
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struct udevice *pch;
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int ret;
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ret = uclass_first_device(UCLASS_PCH, &pch);
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if (ret)
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return ret;
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if (!pch)
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return -ENODEV;
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if (!(gd->flags & GD_FLG_RELOC))
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bd82x6x_sata_enable(dev);
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else
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bd82x6x_sata_init(dev);
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bd82x6x_sata_init(dev, pch);
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return 0;
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}
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@ -30,11 +30,6 @@
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#define SMBUS_IO_BASE 0x0400
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int pch_silicon_revision(void);
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int pch_silicon_type(void);
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int pch_silicon_supported(int type, int rev);
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void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
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#define MAINBOARD_POWER_OFF 0
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#define MAINBOARD_POWER_ON 1
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#define MAINBOARD_POWER_KEEP 2
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@ -470,4 +465,41 @@ void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue);
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#define DMISCI_STS (1 << 9)
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#define TCO2_STS 0x66
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/**
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* pch_silicon_revision() - Read silicon revision ID from the PCH
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*
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* @dev: PCH device
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* @return silicon revision ID
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*/
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int pch_silicon_revision(struct udevice *dev);
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/**
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* pch_silicon_revision() - Read silicon device ID from the PCH
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*
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* @dev: PCH device
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* @return silicon device ID
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*/
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int pch_silicon_type(struct udevice *dev);
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/**
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* pch_silicon_supported() - Check if a certain revision is supported
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*
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* @dev: PCH device
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* @type: PCH type
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* @rev: Minimum required resion
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* @return 0 if not supported, 1 if supported
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*/
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int pch_silicon_supported(struct udevice *dev, int type, int rev);
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/**
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* pch_pch_iobp_update() - Update a pch register
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*
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* @dev: PCH device
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* @address: Address to update
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* @andvalue: Value to AND with existing value
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* @orvalue: Value to OR with existing value
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*/
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void pch_iobp_update(struct udevice *dev, u32 address, u32 andvalue,
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u32 orvalue);
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#endif
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