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mpc83xx: Introduce ARCH_MPC831*

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Replace CONFIG_MPC833* with proper CONFIG_ARCH_MPC833* Kconfig options.

Signed-off-by: Mario Six <mario.six@gdsys.cc>
This commit is contained in:
Mario Six 2019-01-21 09:17:25 +01:00
parent 4bc97a3b81
commit 9403fc41c7
17 changed files with 64 additions and 61 deletions
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15
arch/powerpc/cpu/mpc83xx/Kconfig
View File

@ -17,6 +17,7 @@ config TARGET_SBC8349
config TARGET_VE8313
bool "Support ve8313"
select ARCH_MPC8313
config TARGET_VME8349
bool "Support vme8349"
@ -28,11 +29,13 @@ config TARGET_MPC8308RDB
config TARGET_MPC8313ERDB
bool "Support MPC8313ERDB"
select ARCH_MPC8313
select BOARD_EARLY_INIT_F
select SUPPORT_SPL
config TARGET_MPC8315ERDB
bool "Support MPC8315ERDB"
select ARCH_MPC8315
select BOARD_EARLY_INIT_F
config TARGET_MPC8323ERDB
@ -65,6 +68,7 @@ config TARGET_MPC837XERDB
config TARGET_IDS8313
bool "Support ids8313"
select ARCH_MPC8313
select DM
imply CMD_DM
@ -113,6 +117,17 @@ config ARCH_MPC8309
bool
select ARCH_MPC830X
config ARCH_MPC831X
bool
config ARCH_MPC8313
bool
select ARCH_MPC831X
config ARCH_MPC8315
bool
select ARCH_MPC831X
source "board/esd/vme8349/Kconfig"
source "board/freescale/mpc8308rdb/Kconfig"
source "board/freescale/mpc8313erdb/Kconfig"

2
arch/powerpc/cpu/mpc83xx/cpu.c
View File

@ -18,7 +18,7 @@
#include <tsec.h>
#include <netdev.h>
#include <fsl_esdhc.h>
#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_MPC831x)
#if defined(CONFIG_BOOTCOUNT_LIMIT) && !defined(CONFIG_ARCH_MPC831X)
#include <linux/immap_qe.h>
#include <asm/io.h>
#endif

4
arch/powerpc/cpu/mpc83xx/cpu_init.c
View File

@ -240,7 +240,7 @@ void cpu_init_f (volatile immap_t * im)
/* System General Purpose Register */
#ifdef CONFIG_SYS_SICRH
#if defined(CONFIG_MPC834x) || defined(CONFIG_MPC8313)
#if defined(CONFIG_MPC834x) || defined(CONFIG_ARCH_MPC8313)
/* regarding to MPC34x manual rev.1 bits 28..29 must be preserved */
__raw_writel((im->sysconf.sicrh & 0x0000000C) | CONFIG_SYS_SICRH,
&im->sysconf.sicrh);
@ -312,7 +312,7 @@ void cpu_init_f (volatile immap_t * im)
im->gpio[1].dat = CONFIG_SYS_GPIO2_DAT;
im->gpio[1].dir = CONFIG_SYS_GPIO2_DIR;
#endif
#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_MPC831x)
#if defined(CONFIG_USB_EHCI_FSL) && defined(CONFIG_ARCH_MPC831X)
uint32_t temp;
struct usb_ehci *ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;

6
arch/powerpc/cpu/mpc83xx/fdt.c
View File

@ -16,7 +16,7 @@ extern void ft_qe_setup(void *blob);
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_BOOTCOUNT_LIMIT) && \
(defined(CONFIG_QE) && !defined(CONFIG_MPC831x))
(defined(CONFIG_QE) && !defined(CONFIG_ARCH_MPC831X))
#include <linux/immap_qe.h>
void fdt_fixup_muram (void *blob)
@ -52,7 +52,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) ||\
defined(CONFIG_HAS_ETH4) || defined(CONFIG_HAS_ETH5)
#ifdef CONFIG_MPC8313
#ifdef CONFIG_ARCH_MPC8313
/*
* mpc8313e erratum IPIC1 swapped TSEC interrupt ID numbers on rev. 1
* h/w (see AN3545). The base device tree in use has rev. 1 ID numbers,
@ -123,7 +123,7 @@ void ft_cpu_setup(void *blob, bd_t *bd)
fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
#if defined(CONFIG_BOOTCOUNT_LIMIT) && \
(defined(CONFIG_QE) && !defined(CONFIG_MPC831x))
(defined(CONFIG_QE) && !defined(CONFIG_ARCH_MPC831X))
fdt_fixup_muram (blob);
#endif
}

2
arch/powerpc/cpu/mpc83xx/spd_sdram.c
View File

@ -31,7 +31,7 @@ void board_add_ram_info(int use_default)
printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
>> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x)
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16)
puts(", 16-bit");
else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32)

40
arch/powerpc/cpu/mpc83xx/speed.c
View File

@ -85,7 +85,7 @@ int get_clocks(void)
u32 lcrr;
u32 csb_clk;
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
u32 tsec1_clk;
u32 tsec2_clk;
@ -101,7 +101,7 @@ int get_clocks(void)
#if !defined(CONFIG_MPC832x)
u32 i2c2_clk;
#endif
#if defined(CONFIG_MPC8315)
#if defined(CONFIG_ARCH_MPC8315)
u32 tdm_clk;
#endif
#if defined(CONFIG_FSL_ESDHC)
@ -122,12 +122,12 @@ int get_clocks(void)
u32 qe_clk;
u32 brg_clk;
#endif
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
defined(CONFIG_MPC837x)
u32 pciexp1_clk;
u32 pciexp2_clk;
#endif
#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315)
u32 sata_clk;
#endif
@ -155,7 +155,7 @@ int get_clocks(void)
sccr = im->clk.sccr;
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
switch ((sccr & SCCR_TSEC1CM) >> SCCR_TSEC1CM_SHIFT) {
case 0:
@ -176,7 +176,7 @@ int get_clocks(void)
}
#endif
#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_MPC831x) || \
#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X) || \
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
switch ((sccr & SCCR_USBDRCM) >> SCCR_USBDRCM_SHIFT) {
case 0:
@ -197,7 +197,7 @@ int get_clocks(void)
}
#endif
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC8315) || \
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315) || \
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
switch ((sccr & SCCR_TSEC2CM) >> SCCR_TSEC2CM_SHIFT) {
case 0:
@ -216,7 +216,7 @@ int get_clocks(void)
/* unknown SCCR_TSEC2CM value */
return -4;
}
#elif defined(CONFIG_MPC8313)
#elif defined(CONFIG_ARCH_MPC8313)
tsec2_clk = tsec1_clk;
if (!(sccr & SCCR_TSEC1ON))
@ -291,7 +291,7 @@ int get_clocks(void)
return -8;
}
#endif
#if defined(CONFIG_MPC8315)
#if defined(CONFIG_ARCH_MPC8315)
switch ((sccr & SCCR_TDMCM) >> SCCR_TDMCM_SHIFT) {
case 0:
tdm_clk = 0;
@ -317,7 +317,7 @@ int get_clocks(void)
i2c1_clk = csb_clk;
#elif defined(CONFIG_MPC832x)
i2c1_clk = enc_clk;
#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x)
#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
i2c1_clk = enc_clk;
#elif defined(CONFIG_FSL_ESDHC)
i2c1_clk = sdhc_clk;
@ -330,7 +330,7 @@ int get_clocks(void)
i2c2_clk = csb_clk; /* i2c-2 clk is equal to csb clk */
#endif
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
defined(CONFIG_MPC837x)
switch ((sccr & SCCR_PCIEXP1CM) >> SCCR_PCIEXP1CM_SHIFT) {
case 0:
@ -369,7 +369,7 @@ int get_clocks(void)
}
#endif
#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315)
switch ((sccr & SCCR_SATA1CM) >> SCCR_SATA1CM_SHIFT) {
case 0:
sata_clk = 0;
@ -448,7 +448,7 @@ int get_clocks(void)
#endif
gd->arch.csb_clk = csb_clk;
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
gd->arch.tsec1_clk = tsec1_clk;
gd->arch.tsec2_clk = tsec2_clk;
@ -459,7 +459,7 @@ int get_clocks(void)
#if defined(CONFIG_MPC834x)
gd->arch.usbmph_clk = usbmph_clk;
#endif
#if defined(CONFIG_MPC8315)
#if defined(CONFIG_ARCH_MPC8315)
gd->arch.tdm_clk = tdm_clk;
#endif
#if defined(CONFIG_FSL_ESDHC)
@ -483,12 +483,12 @@ int get_clocks(void)
gd->arch.qe_clk = qe_clk;
gd->arch.brg_clk = brg_clk;
#endif
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
defined(CONFIG_MPC837x)
gd->arch.pciexp1_clk = pciexp1_clk;
gd->arch.pciexp2_clk = pciexp2_clk;
#endif
#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315)
gd->arch.sata_clk = sata_clk;
#endif
gd->pci_clk = pci_sync_in;
@ -550,7 +550,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
printf(" I2C2: %-4s MHz\n",
strmhz(buf, gd->arch.i2c2_clk));
#endif
#if defined(CONFIG_MPC8315)
#if defined(CONFIG_ARCH_MPC8315)
printf(" TDM: %-4s MHz\n",
strmhz(buf, gd->arch.tdm_clk));
#endif
@ -558,7 +558,7 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
printf(" SDHC: %-4s MHz\n",
strmhz(buf, gd->arch.sdhc_clk));
#endif
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
printf(" TSEC1: %-4s MHz\n",
strmhz(buf, gd->arch.tsec1_clk));
@ -574,14 +574,14 @@ static int do_clocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
printf(" USB MPH: %-4s MHz\n",
strmhz(buf, gd->arch.usbmph_clk));
#endif
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
defined(CONFIG_MPC837x)
printf(" PCIEXP1: %-4s MHz\n",
strmhz(buf, gd->arch.pciexp1_clk));
printf(" PCIEXP2: %-4s MHz\n",
strmhz(buf, gd->arch.pciexp2_clk));
#endif
#if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
#if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315)
printf(" SATA: %-4s MHz\n",
strmhz(buf, gd->arch.sata_clk));
#endif

4
arch/powerpc/include/asm/arch-mpc83xx/gpio.h
View File

@ -6,8 +6,8 @@
/*
* The MCP83xx's 1-2 GPIO controllers each with 32 bits.
*/
#if defined(CONFIG_MPC8313) || defined(CONFIG_ARCH_MPC8308) || \
defined(CONFIG_MPC8315)
#if defined(CONFIG_ARCH_MPC8313) || defined(CONFIG_ARCH_MPC8308) || \
defined(CONFIG_ARCH_MPC8315)
#define MPC83XX_GPIO_CTRLRS 1
#elif defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
#define MPC83XX_GPIO_CTRLRS 2

8
arch/powerpc/include/asm/global_data.h
View File

@ -35,7 +35,7 @@ struct arch_global_data {
#else
/* There are other clocks in the MPC83XX */
u32 csb_clk;
# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \
# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
defined(CONFIG_MPC834x) || defined(CONFIG_MPC837x)
u32 tsec1_clk;
u32 tsec2_clk;
@ -46,19 +46,19 @@ struct arch_global_data {
# if defined(CONFIG_MPC834x)
u32 usbmph_clk;
# endif /* CONFIG_MPC834x */
# if defined(CONFIG_MPC8315)
# if defined(CONFIG_ARCH_MPC8315)
u32 tdm_clk;
# endif
u32 core_clk;
u32 enc_clk;
u32 lbiu_clk;
u32 lclk_clk;
# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \
# if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
defined(CONFIG_MPC837x)
u32 pciexp1_clk;
u32 pciexp2_clk;
# endif
# if defined(CONFIG_MPC837x) || defined(CONFIG_MPC8315)
# if defined(CONFIG_MPC837x) || defined(CONFIG_ARCH_MPC8315)
u32 sata_clk;
# endif
# if defined(CONFIG_MPC8360)

4
arch/powerpc/include/asm/immap_83xx.h
View File

@ -679,7 +679,7 @@ typedef struct immap {
#define CONFIG_SYS_MPC83xx_USB2_OFFSET 0x23000
#endif
#elif defined(CONFIG_MPC8313)
#elif defined(CONFIG_ARCH_MPC8313)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */
@ -714,7 +714,7 @@ typedef struct immap {
u8 res7[0xC0000];
} immap_t;
#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC8315)
#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315)
typedef struct immap {
sysconf83xx_t sysconf; /* System configuration */
wdt83xx_t wdt; /* Watch Dog Timer (WDT) Registers */

4
arch/powerpc/include/asm/mpc8xxx_spi.h
View File

@ -11,8 +11,8 @@
#include <asm/types.h>
#if defined(CONFIG_ARCH_MPC8308) || \
defined(CONFIG_MPC8313) || \
defined(CONFIG_MPC8315) || \
defined(CONFIG_ARCH_MPC8313) || \
defined(CONFIG_ARCH_MPC8315) || \
defined(CONFIG_MPC834x) || \
defined(CONFIG_MPC837x)

4
drivers/ram/mpc83xx_sdram.c
View File

@ -180,7 +180,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
case ODT_RD_ONLY_CURRENT:
case ODT_RD_ONLY_OTHER_CS:
if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
!IS_ENABLED(CONFIG_MPC831x) &&
!IS_ENABLED(CONFIG_ARCH_MPC831X) &&
!IS_ENABLED(CONFIG_MPC8360) &&
!IS_ENABLED(CONFIG_MPC837x)) {
debug("%s: odt_rd_cfg value %d invalid.\n",
@ -211,7 +211,7 @@ static int mpc83xx_sdram_static_init(ofnode node, u32 cs, u32 mapaddr, u32 size)
case ODT_WR_ONLY_CURRENT:
case ODT_WR_ONLY_OTHER_CS:
if (!IS_ENABLED(CONFIG_ARCH_MPC830X) &&
!IS_ENABLED(CONFIG_MPC831x) &&
!IS_ENABLED(CONFIG_ARCH_MPC831X) &&
!IS_ENABLED(CONFIG_MPC8360) &&
!IS_ENABLED(CONFIG_MPC837x)) {
debug("%s: odt_wr_cfg value %d invalid.\n",

2
include/configs/MPC8313ERDB.h
View File

@ -13,8 +13,6 @@
* High Level Configuration Options
*/
#define CONFIG_E300 1
#define CONFIG_MPC831x 1
#define CONFIG_MPC8313 1
#define CONFIG_MPC8313ERDB 1
#ifdef CONFIG_NAND

2
include/configs/MPC8315ERDB.h
View File

@ -22,8 +22,6 @@
* High Level Configuration Options
*/
#define CONFIG_E300 1 /* E300 family */
#define CONFIG_MPC831x 1 /* MPC831x CPU family */
#define CONFIG_MPC8315 1 /* MPC8315 CPU specific */
#define CONFIG_MPC8315ERDB 1 /* MPC8315ERDB board specific */
/*

3
include/configs/ids8313.h
View File

@ -14,9 +14,6 @@
/*
* High Level Configuration Options
*/
#define CONFIG_MPC831x
#define CONFIG_MPC8313
#define CONFIG_FSL_ELBC
#define CONFIG_BOOT_RETRY_TIME 900

2
include/configs/ve8313.h
View File

@ -16,8 +16,6 @@
* High Level Configuration Options
*/
#define CONFIG_E300 1
#define CONFIG_MPC831x 1
#define CONFIG_MPC8313 1
#define CONFIG_PCI_INDIRECT_BRIDGE 1
#define CONFIG_FSL_ELBC 1

20
include/mpc83xx.h
View File

@ -129,7 +129,7 @@
#define SPCR_TSEC2EP 0x00000003
#define SPCR_TSEC2EP_SHIFT (31-31)
#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \
#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
defined(CONFIG_MPC837x)
/* SPCR bits - MPC8308, MPC831x and MPC837x specific */
/* TSEC data priority */
@ -216,7 +216,7 @@
#define SICRL_URT_CTPR 0x06000000
#define SICRL_IRQ_CTPR 0x00C00000
#elif defined(CONFIG_MPC8313)
#elif defined(CONFIG_ARCH_MPC8313)
/* SICRL bits - MPC8313 specific */
#define SICRL_LBC 0x30000000
#define SICRL_UART 0x0C000000
@ -248,7 +248,7 @@
#define SICRH_TSOBI1 0x00000002
#define SICRH_TSOBI2 0x00000001
#elif defined(CONFIG_MPC8315)
#elif defined(CONFIG_ARCH_MPC8315)
/* SICRL bits - MPC8315 specific */
#define SICRL_DMA_CH0 0xc0000000
#define SICRL_DMA_SPI 0x30000000
@ -639,7 +639,7 @@
#define HRCWL_CE_TO_PLL_1X30 0x0000001E
#define HRCWL_CE_TO_PLL_1X31 0x0000001F
#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC8315)
#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315)
#define HRCWL_SVCOD 0x30000000
#define HRCWL_SVCOD_SHIFT 28
#define HRCWL_SVCOD_DIV_2 0x00000000
@ -765,7 +765,7 @@
#define HRCWH_ROM_LOC_LOCAL_16BIT 0x00600000
#define HRCWH_ROM_LOC_LOCAL_32BIT 0x00700000
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
defined(CONFIG_MPC837x)
#define HRCWH_ROM_LOC_NAND_SP_8BIT 0x00100000
#define HRCWH_ROM_LOC_NAND_SP_16BIT 0x00200000
@ -818,7 +818,7 @@
/*
* RSR - Reset Status Register
*/
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x) || \
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X) || \
defined(CONFIG_MPC837x)
#define RSR_RSTSRC 0xF0000000 /* Reset source */
#define RSR_RSTSRC_SHIFT 28
@ -965,7 +965,7 @@
#define SCCR_USBCM_2 0x00A00000
#define SCCR_USBCM_3 0x00F00000
#elif defined(CONFIG_MPC8313)
#elif defined(CONFIG_ARCH_MPC8313)
/* TSEC1 bits are for TSEC2 as well */
#define SCCR_TSEC1CM 0xc0000000
#define SCCR_TSEC1CM_SHIFT 30
@ -986,7 +986,7 @@
#define SCCR_USBDRCM_2 0x00200000
#define SCCR_USBDRCM_3 0x00300000
#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC8315)
#elif defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC8315)
/* SCCR bits - MPC8315/MPC8308 specific */
#define SCCR_TSEC1CM 0xc0000000
#define SCCR_TSEC1CM_SHIFT 30
@ -1117,7 +1117,7 @@
*/
#define CSCONFIG_EN 0x80000000
#define CSCONFIG_AP 0x00800000
#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_MPC831x)
#if defined(CONFIG_ARCH_MPC830X) || defined(CONFIG_ARCH_MPC831X)
#define CSCONFIG_ODT_RD_NEVER 0x00000000
#define CSCONFIG_ODT_RD_ONLY_CURRENT 0x00100000
#define CSCONFIG_ODT_RD_ONLY_OTHER_CS 0x00200000
@ -1239,7 +1239,7 @@
#define SDRAM_CFG_SDRAM_TYPE_MASK 0x07000000
#define SDRAM_CFG_SDRAM_TYPE_SHIFT 24
#define SDRAM_CFG_DYN_PWR 0x00200000
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_MPC831x)
#if defined(CONFIG_ARCH_MPC8308) || defined(CONFIG_ARCH_MPC831X)
#define SDRAM_CFG_DBW_MASK 0x00180000
#define SDRAM_CFG_DBW_16 0x00100000
#define SDRAM_CFG_DBW_32 0x00080000

3
scripts/config_whitelist.txt
View File

@ -1220,11 +1220,8 @@ CONFIG_MMC_SPI_SPEED
CONFIG_MMC_SUNXI_SLOT
CONFIG_MMU
CONFIG_MONITOR_IS_IN_RAM
CONFIG_MPC8313
CONFIG_MPC8313ERDB
CONFIG_MPC8315
CONFIG_MPC8315ERDB
CONFIG_MPC831x
CONFIG_MPC832XEMDS
CONFIG_MPC832x
CONFIG_MPC8349