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sunxi: clk: Fix USB PHY clock macros for A83T
The A83T has 3 PHYs, the last one being HSIC, which has 2 clocks. Also there is only 1 OHCI. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
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@ -224,14 +224,14 @@ struct sunxi_ccm_reg {
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#define CCM_USB_CTRL_PHY0_RST (0x1 << 0)
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#define CCM_USB_CTRL_PHY1_RST (0x1 << 1)
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#define CCM_USB_CTRL_PHY2_RST (0x1 << 2)
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#define CCM_USB_CTRL_HSIC_RST (0x1 << 2)
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/* There is no global phy clk gate on sun6i, define as 0 */
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#define CCM_USB_CTRL_PHYGATE 0
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#define CCM_USB_CTRL_PHY0_CLK (0x1 << 8)
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#define CCM_USB_CTRL_PHY1_CLK (0x1 << 9)
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#define CCM_USB_CTRL_PHY2_CLK (0x1 << 10)
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#define CCM_USB_CTRL_HSIC_CLK (0x1 << 10)
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#define CCM_USB_CTRL_12M_CLK (0x1 << 11)
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#define CCM_USB_CTRL_OHCI0_CLK (0x1 << 16)
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#define CCM_USB_CTRL_OHCI1_CLK (0x1 << 17)
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#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0
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#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1
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