brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-10-01 00:50:43 +09:00
Code Issues Projects Releases Wiki Activity

SPC1920: add support for the FM18L08 Ramtron FRAM

Browse Source
This commit is contained in:
Markus Klotzbuecher 2007-01-09 14:57:13 +01:00 committed by Markus Klotzbuecher
parent 38ccd2fdf3
commit 9295acb774
2 changed files with 19 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
board/spc1920/spc1920.c
View File

@ -175,6 +175,11 @@ long int initdram (int board_type)
/* initalize the DSP Host Port Interface */
hpi_init();
/* PLD Setup */
memctl->memc_or4 = CFG_OR4_PRELIM;
memctl->memc_br4 = CFG_BR4_PRELIM;
udelay(1000);
/* PLD Setup */
memctl->memc_or5 = CFG_OR5_PRELIM;
memctl->memc_br5 = CFG_BR5_PRELIM;

15
include/configs/spc1920.h
View File

@ -391,11 +391,24 @@
#define HPI_HPID_NOINC_2 HPI_REG(0x300000c + 2)
#endif /* CONFIG_SPC1920_HPI_TEST */
/*
* Ramtron FM18L08 FRAM 32KB on CS4
*/
#define CFG_SPC1920_FRAM_BASE 0x80100000
#define CFG_PRELIM_OR4_AM 0xffff8000
#define CFG_OR4_PRELIM (CFG_PRELIM_OR4_AM | \
OR_ACS_DIV2 | \
OR_BI | \
OR_SCY_4_CLK | \
OR_TRLX)
#define CFG_BR4_PRELIM ((CFG_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V);
/*
* PLD CS5
*/
#define CFG_SPC1920_PLD_BASE 0x80000000
#define CFG_PRELIM_OR5_AM 0xfff00000
#define CFG_PRELIM_OR5_AM 0xffff8000
#define CFG_OR5_PRELIM (CFG_PRELIM_OR5_AM | \
OR_CSNT_SAM | \