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riscv: Add some comments to start.S

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This adds comments regarding the ordering and purpose of certain
instructions as I understand them.

Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Liang <ycliang@andestech.com>
This commit is contained in:
Sean Anderson 2020-09-21 07:51:41 -04:00 committed by Andes
parent 85768134b4
commit 924de3216e
1 changed files with 17 additions and 2 deletions
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19
arch/riscv/cpu/start.S
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@ -43,7 +43,10 @@ _start:
csrr a0, CSR_MHARTID
#endif
/* save hart id and dtb pointer */
/*
* Save hart id and dtb pointer. The thread pointer register is not
* modified by C code. It is used by secondary_hart_loop.
*/
mv tp, a0
mv s1, a1
@ -54,10 +57,18 @@ _start:
*/
mv gp, zero
/*
* Set the trap handler. This must happen after initializing gp because
* the handler may use it.
*/
la t0, trap_entry
csrw MODE_PREFIX(tvec), t0
/* mask all interrupts */
/*
* Mask all interrupts. Interrupts are disabled globally (in m/sstatus)
* for U-Boot, but we will need to read m/sip to determine if we get an
* IPI
*/
csrw MODE_PREFIX(ie), zero
#if CONFIG_IS_ENABLED(SMP)
@ -412,6 +423,10 @@ secondary_hart_relocate:
mv gp, a2
#endif
/*
* Interrupts are disabled globally, but they can still be read from m/sip. The
* wfi function will wake us up if we get an IPI, even if we do not trap.
*/
secondary_hart_loop:
wfi