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https://github.com/brain-hackers/u-boot-brain
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ARM: dts: socfpga: Factor out U-Boot specifics from A10 handoff files
Pull out the u-boot,dm-pre-reloc from socfpga_arria10_socdk_sdmmc_handoff.dtsi into separate dtsi header file to make it easier to patch in custom handoff dtsi files, without having to manually add the U-Boot bits. Shuffle the include clauses in the A10 DT files to make it obvious what gets included where without having to follow confusing long chain of includes, i.e. board DT file includes everything it needs. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
This commit is contained in:
Marek Vasut
parent
990ed4452c
commit
917bd8a876
67
arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
Normal file
67
arch/arm/dts/socfpga_arria10_handoff_u-boot.dtsi
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@ -0,0 +1,67 @@
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// SPDX-License-Identifier: GPL-2.0+ OR X11
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/ {
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chosen {
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u-boot,dm-pre-reloc;
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};
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clocks {
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u-boot,dm-pre-reloc;
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altera_arria10_hps_eosc1 {
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u-boot,dm-pre-reloc;
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};
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altera_arria10_hps_cb_intosc_ls {
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u-boot,dm-pre-reloc;
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};
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altera_arria10_hps_f2h_free {
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u-boot,dm-pre-reloc;
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};
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};
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clock_manager@0xffd04000 {
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u-boot,dm-pre-reloc;
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mainpll {
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u-boot,dm-pre-reloc;
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};
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perpll {
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u-boot,dm-pre-reloc;
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};
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alteragrp {
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u-boot,dm-pre-reloc;
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};
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};
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pinmux@0xffd07000 {
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u-boot,dm-pre-reloc;
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shared {
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u-boot,dm-pre-reloc;
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};
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dedicated {
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u-boot,dm-pre-reloc;
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};
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dedicated_cfg {
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u-boot,dm-pre-reloc;
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};
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fpga {
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u-boot,dm-pre-reloc;
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};
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};
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noc@0xffd10000 {
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u-boot,dm-pre-reloc;
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firewall {
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u-boot,dm-pre-reloc;
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};
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};
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};
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@ -14,7 +14,8 @@
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
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#include "socfpga_arria10.dtsi"
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/ {
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model = "Altera SOCFPGA Arria 10";
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@ -17,6 +17,8 @@
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/dts-v1/;
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#include "socfpga_arria10_socdk.dtsi"
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#include "socfpga_arria10_socdk_sdmmc_handoff.dtsi"
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#include "socfpga_arria10_handoff_u-boot.dtsi"
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/ {
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chosen {
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@ -11,8 +11,6 @@
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*</auto-generated>
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*/
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#include "socfpga_arria10.dtsi"
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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@ -24,13 +22,11 @@
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/* Clock sources */
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clocks {
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u-boot,dm-pre-reloc;
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#address-cells = <1>;
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#size-cells = <1>;
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/* Clock source: altera_arria10_hps_eosc1 */
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altera_arria10_hps_eosc1: altera_arria10_hps_eosc1 {
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u-boot,dm-pre-reloc;
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <25000000>;
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@ -39,7 +35,6 @@
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/* Clock source: altera_arria10_hps_cb_intosc_ls */
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altera_arria10_hps_cb_intosc_ls: altera_arria10_hps_cb_intosc_ls {
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u-boot,dm-pre-reloc;
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <60000000>;
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@ -48,7 +43,6 @@
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/* Clock source: altera_arria10_hps_f2h_free */
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altera_arria10_hps_f2h_free: altera_arria10_hps_f2h_free {
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u-boot,dm-pre-reloc;
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <200000000>;
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@ -62,14 +56,12 @@
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* Binding: device
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*/
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i_clk_mgr: clock_manager@0xffd04000 {
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u-boot,dm-pre-reloc;
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compatible = "altr,socfpga-a10-clk-init";
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reg = <0xffd04000 0x00000200>;
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reg-names = "soc_clock_manager_OCP_SLV";
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/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_mainpllgrp */
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mainpll {
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u-boot,dm-pre-reloc;
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vco0-psrc = <0>; /* Field: vco0.psrc */
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vco1-denom = <1>; /* Field: vco1.denom */
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vco1-numer = <191>; /* Field: vco1.numer */
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@ -98,7 +90,6 @@
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/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_perpllgrp */
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perpll {
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u-boot,dm-pre-reloc;
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vco0-psrc = <0>; /* Field: vco0.psrc */
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vco1-denom = <1>; /* Field: vco1.denom */
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vco1-numer = <159>; /* Field: vco1.numer */
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@ -124,7 +115,6 @@
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/* Address Block: soc_clock_manager_OCP_SLV.i_clk_mgr_alteragrp */
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alteragrp {
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u-boot,dm-pre-reloc;
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nocclk = <0x0384000b>; /* Register: nocclk */
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mpuclk = <0x03840001>; /* Register: mpuclk */
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};
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@ -136,7 +126,6 @@
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* Binding: pinmux
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*/
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i_io48_pin_mux: pinmux@0xffd07000 {
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u-boot,dm-pre-reloc;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "pinctrl-single";
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@ -145,7 +134,6 @@
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/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_shared_3v_io_grp */
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shared {
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u-boot,dm-pre-reloc;
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reg = <0xffd07000 0x00000200>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x0000000f>;
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@ -202,7 +190,6 @@
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/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
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dedicated {
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u-boot,dm-pre-reloc;
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reg = <0xffd07200 0x00000200>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x0000000f>;
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@ -225,7 +212,6 @@
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/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_dedicated_io_grp */
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dedicated_cfg {
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u-boot,dm-pre-reloc;
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reg = <0xffd07200 0x00000200>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x003f3f3f>;
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@ -252,7 +238,6 @@
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/* Address Block: soc_3v_io48_pin_mux_OCP_SLV.i_io48_pin_mux_fpga_interface_grp */
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fpga {
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u-boot,dm-pre-reloc;
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reg = <0xffd07400 0x00000100>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <0x00000001>;
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@ -283,13 +268,11 @@
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* Binding: device
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*/
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i_noc: noc@0xffd10000 {
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u-boot,dm-pre-reloc;
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compatible = "altr,socfpga-a10-noc";
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reg = <0xffd10000 0x00008000>;
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reg-names = "mpu_m0";
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firewall {
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u-boot,dm-pre-reloc;
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/*
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* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.base
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* Driver setting: altera_arria10_soc_noc_arria10_uboot_driver.I_NOC.mpu_m0.noc_fw_ddr_mpu_fpga2sdram_ddr_scr.mpuregion0addr.limit
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