drivers: pci_ep: Introduce UCLASS_PCI_EP uclass
Introduce new UCLASS_PCI_EP class for handling PCI endpoint devices, allowing to set various attributes of the PCI endpoint device, such as: * configuration space header * BAR definitions * outband memory mapping * start/stop PCI link Signed-off-by: Ramon Fried <ramon.fried@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Ramon Fried
Tom Rini
parent
ef8b7e045e
commit
914026d258
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@ -633,6 +633,12 @@ M: Simon Glass <sjg@chromium.org>
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S: Maintained
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F: tools/patman/
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PCI Endpoint
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M: Ramon Fried <rfried.dev@gmail.com>
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S: Maintained
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F: drivers/pci_endpoint/
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F: include/pci_ep.h
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POWER
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M: Jaehoon Chung <jh80.chung@samsung.com>
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S: Maintained
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@ -66,6 +66,8 @@ source "drivers/nvme/Kconfig"
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source "drivers/pci/Kconfig"
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source "drivers/pci_endpoint/Kconfig"
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source "drivers/pch/Kconfig"
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source "drivers/pcmcia/Kconfig"
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@ -86,6 +86,7 @@ obj-$(CONFIG_FPGA) += fpga/
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obj-y += misc/
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obj-$(CONFIG_MMC) += mmc/
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obj-$(CONFIG_NVME) += nvme/
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obj-$(CONFIG_PCI_ENDPOINT) += pci_endpoint/
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obj-y += pcmcia/
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obj-y += dfu/
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obj-$(CONFIG_PCH) += pch/
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@ -0,0 +1,17 @@
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# SPDX-License-Identifier: GPL-2.0
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#
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# PCI Endpoint Support
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#
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menu "PCI Endpoint"
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config PCI_ENDPOINT
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bool "PCI Endpoint Support"
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depends on DM
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help
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Enable this configuration option to support configurable PCI
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endpoints. This should be enabled if the platform has a PCI
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controllers that can operate in endpoint mode (as a device
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connected to PCI host or bridge).
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endmenu
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@ -0,0 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# (C) Copyright 2019
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# Ramon Fried <ramon.fried@gmail.com>
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obj-y += pci_ep-uclass.o
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@ -0,0 +1,211 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* PCI Endpoint uclass
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*
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* Based on Linux PCI-EP driver written by
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* Kishon Vijay Abraham I <kishon@ti.com>
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*
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* Copyright (c) 2019
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* Written by Ramon Fried <ramon.fried@gmail.com>
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*/
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#include <common.h>
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#include <dm.h>
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#include <errno.h>
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#include <linux/log2.h>
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#include <pci_ep.h>
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DECLARE_GLOBAL_DATA_PTR;
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int pci_ep_write_header(struct udevice *dev, uint fn, struct pci_ep_header *hdr)
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{
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struct pci_ep_ops *ops = pci_ep_get_ops(dev);
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if (!ops->write_header)
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return -ENOSYS;
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return ops->write_header(dev, fn, hdr);
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}
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int pci_ep_read_header(struct udevice *dev, uint fn, struct pci_ep_header *hdr)
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{
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struct pci_ep_ops *ops = pci_ep_get_ops(dev);
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if (!ops->read_header)
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return -ENOSYS;
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return ops->read_header(dev, fn, hdr);
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}
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int pci_ep_set_bar(struct udevice *dev, uint func_no, struct pci_bar *ep_bar)
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{
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struct pci_ep_ops *ops = pci_ep_get_ops(dev);
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int flags = ep_bar->flags;
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/* Some basic bar validity checks */
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if (ep_bar->barno > BAR_5 || ep_bar < BAR_0)
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return -EINVAL;
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if ((ep_bar->barno == BAR_5 &&
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(flags & PCI_BASE_ADDRESS_MEM_TYPE_64)) ||
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((flags & PCI_BASE_ADDRESS_SPACE_IO) &&
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(flags & PCI_BASE_ADDRESS_IO_MASK)) ||
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(upper_32_bits(ep_bar->size) &&
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!(flags & PCI_BASE_ADDRESS_MEM_TYPE_64)))
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return -EINVAL;
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if (!ops->set_bar)
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return -ENOSYS;
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return ops->set_bar(dev, func_no, ep_bar);
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}
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int pci_ep_read_bar(struct udevice *dev, uint func_no, struct pci_bar *ep_bar,
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enum pci_barno barno)
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{
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struct pci_ep_ops *ops = pci_ep_get_ops(dev);
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/* Some basic bar validity checks */
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if (barno > BAR_5 || barno < BAR_0)
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return -EINVAL;
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if (!ops->read_bar)
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return -ENOSYS;
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return ops->read_bar(dev, func_no, ep_bar, barno);
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}
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int pci_ep_clear_bar(struct udevice *dev, uint func_num, enum pci_barno bar)
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{
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struct pci_ep_ops *ops = pci_ep_get_ops(dev);
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if (!ops->clear_bar)
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return -ENOSYS;
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return ops->clear_bar(dev, func_num, bar);
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}
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int pci_ep_map_addr(struct udevice *dev, uint func_no, phys_addr_t addr,
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u64 pci_addr, size_t size)
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{
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struct pci_ep_ops *ops = pci_ep_get_ops(dev);
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if (!ops->map_addr)
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return -ENOSYS;
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return ops->map_addr(dev, func_no, addr, pci_addr, size);
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}
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int pci_ep_unmap_addr(struct udevice *dev, uint func_no, phys_addr_t addr)
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{
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struct pci_ep_ops *ops = pci_ep_get_ops(dev);
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if (!ops->unmap_addr)
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return -ENOSYS;
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return ops->unmap_addr(dev, func_no, addr);
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}
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int pci_ep_set_msi(struct udevice *dev, uint func_no, uint interrupts)
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{
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struct pci_ep_ops *ops = pci_ep_get_ops(dev);
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uint encode_int;
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if (interrupts > 32)
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return -EINVAL;
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if (!ops->set_msi)
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return -ENOSYS;
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/* MSI spec permits allocation of
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* only 1, 2, 4, 8, 16, 32 interrupts
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*/
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encode_int = order_base_2(interrupts);
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return ops->set_msi(dev, func_no, encode_int);
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}
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int pci_ep_get_msi(struct udevice *dev, uint func_no)
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{
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struct pci_ep_ops *ops = pci_ep_get_ops(dev);
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int interrupt;
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if (!ops->get_msi)
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return -ENOSYS;
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interrupt = ops->get_msi(dev, func_no);
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if (interrupt < 0)
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return 0;
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/* Translate back from order base 2*/
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interrupt = 1 << interrupt;
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return interrupt;
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}
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int pci_ep_set_msix(struct udevice *dev, uint func_no, uint interrupts)
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{
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struct pci_ep_ops *ops = pci_ep_get_ops(dev);
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if (interrupts < 1 || interrupts > 2048)
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return -EINVAL;
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if (!ops->set_msix)
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return -ENOSYS;
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return ops->set_msix(dev, func_no, interrupts - 1);
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}
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int pci_ep_get_msix(struct udevice *dev, uint func_no)
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{
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struct pci_ep_ops *ops = pci_ep_get_ops(dev);
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int interrupt;
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if (!ops->get_msix)
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return -ENOSYS;
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interrupt = ops->get_msix(dev, func_no);
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if (interrupt < 0)
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return 0;
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return interrupt + 1;
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}
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int pci_ep_raise_irq(struct udevice *dev, uint func_no,
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enum pci_ep_irq_type type, uint interrupt_num)
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{
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struct pci_ep_ops *ops = pci_ep_get_ops(dev);
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if (!ops->raise_irq)
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return -ENOSYS;
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return ops->raise_irq(dev, func_no, type, interrupt_num);
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}
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int pci_ep_start(struct udevice *dev)
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{
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struct pci_ep_ops *ops = pci_ep_get_ops(dev);
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if (!ops->start)
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return -ENOSYS;
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return ops->start(dev);
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}
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int pci_ep_stop(struct udevice *dev)
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{
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struct pci_ep_ops *ops = pci_ep_get_ops(dev);
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if (!ops->stop)
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return -ENOSYS;
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return ops->stop(dev);
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}
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UCLASS_DRIVER(pci_ep) = {
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.id = UCLASS_PCI_EP,
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.name = "pci_ep",
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.flags = DM_UC_FLAG_SEQ_ALIAS,
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};
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@ -69,6 +69,7 @@ enum uclass_id {
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UCLASS_PANEL_BACKLIGHT, /* Backlight controller for panel */
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UCLASS_PCH, /* x86 platform controller hub */
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UCLASS_PCI, /* PCI bus */
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UCLASS_PCI_EP, /* PCI endpoint device */
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UCLASS_PCI_GENERIC, /* Generic PCI bus device */
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UCLASS_PHY, /* Physical Layer (PHY) device */
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UCLASS_PINCONFIG, /* Pin configuration node device */
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@ -0,0 +1,414 @@
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/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Adapted from Linux kernel driver
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* Copyright (C) 2017 Texas Instruments
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* Author: Kishon Vijay Abraham I <kishon@ti.com>
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*
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* (C) Copyright 2019
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* Ramon Fried <ramon.fried@gmail.com>
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*/
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#ifndef _PCI_EP_H
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#define _PCI_EP_H
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#include <pci.h>
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/**
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* enum pci_interrupt_pin - PCI INTx interrupt values
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* @PCI_INTERRUPT_UNKNOWN: Unknown or unassigned interrupt
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* @PCI_INTERRUPT_INTA: PCI INTA pin
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* @PCI_INTERRUPT_INTB: PCI INTB pin
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* @PCI_INTERRUPT_INTC: PCI INTC pin
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* @PCI_INTERRUPT_INTD: PCI INTD pin
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*
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* Corresponds to values for legacy PCI INTx interrupts, as can be found in the
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* PCI_INTERRUPT_PIN register.
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*/
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enum pci_interrupt_pin {
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PCI_INTERRUPT_UNKNOWN,
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PCI_INTERRUPT_INTA,
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PCI_INTERRUPT_INTB,
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PCI_INTERRUPT_INTC,
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PCI_INTERRUPT_INTD,
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};
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enum pci_barno {
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BAR_0,
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BAR_1,
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BAR_2,
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BAR_3,
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BAR_4,
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BAR_5,
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};
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enum pci_ep_irq_type {
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PCI_EP_IRQ_UNKNOWN,
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PCI_EP_IRQ_LEGACY,
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PCI_EP_IRQ_MSI,
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PCI_EP_IRQ_MSIX,
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};
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/**
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* struct pci_bar - represents the BAR (Base Address Register) of EP device
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* @phys_addr: physical address that should be mapped to the BAR
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* @size: the size of the address space present in BAR
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* pci_barno: number of pci BAR to set (0..5)
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* @flags: BAR access flags
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*/
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struct pci_bar {
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dma_addr_t phys_addr;
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size_t size;
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enum pci_barno barno;
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int flags;
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};
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/**
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* struct pci_ep_header - represents standard configuration header
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* @vendorid: identifies device manufacturer
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* @deviceid: identifies a particular device
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* @revid: specifies a device-specific revision identifier
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* @progif_code: identifies a specific register-level programming interface
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* @subclass_code: identifies more specifically the function of the device
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* @baseclass_code: broadly classifies the type of function the device performs
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* @cache_line_size: specifies the system cacheline size in units of DWORDs
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* @subsys_vendor_id: vendor of the add-in card or subsystem
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* @subsys_id: id specific to vendor
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* @interrupt_pin: interrupt pin the device (or device function) uses
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*/
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struct pci_ep_header {
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u16 vendorid;
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u16 deviceid;
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u8 revid;
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u8 progif_code;
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u8 subclass_code;
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u8 baseclass_code;
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u8 cache_line_size;
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u16 subsys_vendor_id;
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u16 subsys_id;
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enum pci_interrupt_pin interrupt_pin;
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};
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/* PCI endpoint operations */
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struct pci_ep_ops {
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/**
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* write_header() - Write a PCI configuration space header
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*
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* @dev: device to write to
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* @func_num: EP function to fill
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* @hdr: header to write
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* @return 0 if OK, -ve on error
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*/
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int (*write_header)(struct udevice *dev, uint func_num,
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struct pci_ep_header *hdr);
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/**
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* read_header() - Read a PCI configuration space header
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*
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* @dev: device to write to
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* @func_num: EP function to fill
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* @hdr: header to read to
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* @return 0 if OK, -ve on error
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*/
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int (*read_header)(struct udevice *dev, uint func_num,
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struct pci_ep_header *hdr);
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/**
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* set_bar() - Set BAR (Base Address Register) properties
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*
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* @dev: device to set
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* @func_num: EP function to set
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* @bar: bar data
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* @return 0 if OK, -ve on error
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*/
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int (*set_bar)(struct udevice *dev, uint func_num,
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struct pci_bar *bar);
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/**
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* read_bar() - Read BAR (Base Address Register) properties
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*
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* @dev: device to read
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* @func_num: EP function to read
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* @bar: struct to copy data to
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* @barno: bar number to read
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* @return 0 if OK, -ve on error
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*/
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int (*read_bar)(struct udevice *dev, uint func_num,
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struct pci_bar *bar, enum pci_barno barno);
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/**
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* clear_bar() - clear BAR (Base Address Register)
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*
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* @dev: device to clear
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* @func_num: EP function to clear
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* @bar: bar number
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* @return 0 if OK, -ve on error
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*/
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int (*clear_bar)(struct udevice *dev, uint func_num,
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enum pci_barno bar);
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/**
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* map_addr() - map CPU address to PCI address
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*
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* outband region is used in order to generate PCI read/write
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* transaction from local memory/write.
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*
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* @dev: device to set
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* @func_num: EP function to set
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* @addr: local physical address base
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* @pci_addr: pci address to translate to
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* @size: region size
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* @return 0 if OK, -ve on error
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*/
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int (*map_addr)(struct udevice *dev, uint func_num,
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phys_addr_t addr, u64 pci_addr, size_t size);
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/**
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* unmap_addr() - unmap CPU address to PCI address
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*
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* unmap previously mapped region.
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*
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* @dev: device to set
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* @func_num: EP function to set
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* @addr: local physical address base
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* @return 0 if OK, -ve on error
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*/
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int (*unmap_addr)(struct udevice *dev, uint func_num,
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phys_addr_t addr);
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/**
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* set_msi() - set msi capability property
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*
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* set the number of required MSI vectors the device
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* needs for operation.
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*
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* @dev: device to set
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* @func_num: EP function to set
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* @interrupts: required interrupts count
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* @return 0 if OK, -ve on error
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*/
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int (*set_msi)(struct udevice *dev, uint func_num, uint interrupts);
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/**
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* get_msi() - get the number of MSI interrupts allocated by the host.
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*
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* Read the Multiple Message Enable bitfield from
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* Message control register.
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*
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* @dev: device to use
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* @func_num: EP function to use
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* @return msi count if OK, -EINVAL if msi were not enabled at host.
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*/
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int (*get_msi)(struct udevice *dev, uint func_num);
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/**
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* set_msix() - set msix capability property
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*
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* set the number of required MSIx vectors the device
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* needs for operation.
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*
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* @dev: device to set
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* @func_num: EP function to set
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* @interrupts: required interrupts count
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* @return 0 if OK, -ve on error
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*/
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int (*set_msix)(struct udevice *dev, uint func_num,
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uint interrupts);
|
||||
|
||||
/**
|
||||
* get_msix() - get the number of MSIx interrupts allocated by the host.
|
||||
*
|
||||
* Read the Multiple Message Enable bitfield from
|
||||
* Message control register.
|
||||
*
|
||||
* @dev: device to use
|
||||
* @func_num: EP function to use
|
||||
* @return msi count if OK, -EINVAL if msi were not enabled at host.
|
||||
*/
|
||||
int (*get_msix)(struct udevice *dev, uint func_num);
|
||||
|
||||
/**
|
||||
* raise_irq() - raise a legacy, MSI or MSI-X interrupt
|
||||
*
|
||||
* @dev: device to set
|
||||
* @func_num: EP function to set
|
||||
* @type: type of irq to send
|
||||
* @interrupt_num: interrupt vector to use
|
||||
* @return 0 if OK, -ve on error
|
||||
*/
|
||||
int (*raise_irq)(struct udevice *dev, uint func_num,
|
||||
enum pci_ep_irq_type type, uint interrupt_num);
|
||||
/**
|
||||
* start() - start the PCI link
|
||||
*
|
||||
* @dev: device to set
|
||||
* @return 0 if OK, -ve on error
|
||||
*/
|
||||
int (*start)(struct udevice *dev);
|
||||
|
||||
/**
|
||||
* stop() - stop the PCI link
|
||||
*
|
||||
* @dev: device to set
|
||||
* @return 0 if OK, -ve on error
|
||||
*/
|
||||
int (*stop)(struct udevice *dev);
|
||||
};
|
||||
|
||||
#define pci_ep_get_ops(dev) ((struct pci_ep_ops *)(dev)->driver->ops)
|
||||
|
||||
/**
|
||||
* pci_ep_write_header() - Write a PCI configuration space header
|
||||
*
|
||||
* @dev: device to write to
|
||||
* @func_num: EP function to fill
|
||||
* @hdr: header to write
|
||||
* @return 0 if OK, -ve on error
|
||||
*/
|
||||
int pci_ep_write_header(struct udevice *dev, uint func_num,
|
||||
struct pci_ep_header *hdr);
|
||||
|
||||
/**
|
||||
* dm_pci_ep_read_header() - Read a PCI configuration space header
|
||||
*
|
||||
* @dev: device to write to
|
||||
* @func_num: EP function to fill
|
||||
* @hdr: header to read to
|
||||
* @return 0 if OK, -ve on error
|
||||
*/
|
||||
int pci_ep_read_header(struct udevice *dev, uint func_num,
|
||||
struct pci_ep_header *hdr);
|
||||
/**
|
||||
* pci_ep_set_bar() - Set BAR (Base Address Register) properties
|
||||
*
|
||||
* @dev: device to set
|
||||
* @func_num: EP function to set
|
||||
* @bar: bar data
|
||||
* @return 0 if OK, -ve on error
|
||||
*/
|
||||
int pci_ep_set_bar(struct udevice *dev, uint func_num, struct pci_bar *bar);
|
||||
|
||||
/**
|
||||
* pci_ep_read_bar() - Read BAR (Base Address Register) properties
|
||||
*
|
||||
* @dev: device to read
|
||||
* @func_num: EP function to read
|
||||
* @bar: struct to copy data to
|
||||
* @barno: bar number to read
|
||||
* @return 0 if OK, -ve on error
|
||||
*/
|
||||
int pci_ep_read_bar(struct udevice *dev, uint func_no, struct pci_bar *ep_bar,
|
||||
enum pci_barno barno);
|
||||
|
||||
/**
|
||||
* pci_ep_clear_bar() - Clear BAR (Base Address Register)
|
||||
* mark the BAR as empty so host won't map it.
|
||||
* @dev: device to clear
|
||||
* @func_num: EP function to clear
|
||||
* @bar: bar number
|
||||
* @return 0 if OK, -ve on error
|
||||
*/
|
||||
int pci_ep_clear_bar(struct udevice *dev, uint func_num, enum pci_barno bar);
|
||||
/**
|
||||
* pci_ep_map_addr() - map CPU address to PCI address
|
||||
*
|
||||
* outband region is used in order to generate PCI read/write
|
||||
* transaction from local memory/write.
|
||||
*
|
||||
* @dev: device to set
|
||||
* @func_num: EP function to set
|
||||
* @addr: local physical address base
|
||||
* @pci_addr: pci address to translate to
|
||||
* @size: region size
|
||||
* @return 0 if OK, -ve on error
|
||||
*/
|
||||
int pci_ep_map_addr(struct udevice *dev, uint func_num, phys_addr_t addr,
|
||||
u64 pci_addr, size_t size);
|
||||
/**
|
||||
* pci_ep_unmap_addr() - unmap CPU address to PCI address
|
||||
*
|
||||
* unmap previously mapped region.
|
||||
*
|
||||
* @dev: device to set
|
||||
* @func_num: EP function to set
|
||||
* @addr: local physical address base
|
||||
* @return 0 if OK, -ve on error
|
||||
*/
|
||||
int pci_ep_unmap_addr(struct udevice *dev, uint func_num, phys_addr_t addr);
|
||||
|
||||
/**
|
||||
* pci_ep_set_msi() - set msi capability property
|
||||
*
|
||||
* set the number of required MSI vectors the device
|
||||
* needs for operation.
|
||||
*
|
||||
* @dev: device to set
|
||||
* @func_num: EP function to set
|
||||
* @interrupts: required interrupts count
|
||||
* @return 0 if OK, -ve on error
|
||||
*/
|
||||
int pci_ep_set_msi(struct udevice *dev, uint func_num, uint interrupts);
|
||||
|
||||
/**
|
||||
* pci_ep_get_msi() - get the number of MSI interrupts allocated by the host.
|
||||
*
|
||||
* Read the Multiple Message Enable bitfield from
|
||||
* Message control register.
|
||||
*
|
||||
* @dev: device to use
|
||||
* @func_num: EP function to use
|
||||
* @return msi count if OK, -EINVAL if msi were not enabled at host.
|
||||
*/
|
||||
int pci_ep_get_msi(struct udevice *dev, uint func_num);
|
||||
|
||||
/**
|
||||
* pci_ep_set_msix() - set msi capability property
|
||||
*
|
||||
* set the number of required MSIx vectors the device
|
||||
* needs for operation.
|
||||
*
|
||||
* @dev: device to set
|
||||
* @func_num: EP function to set
|
||||
* @interrupts: required interrupts count
|
||||
* @return 0 if OK, -ve on error
|
||||
*/
|
||||
int pci_ep_set_msix(struct udevice *dev, uint func_num, uint interrupts);
|
||||
|
||||
/**
|
||||
* pci_ep_get_msix() - get the number of MSIx interrupts allocated by the host.
|
||||
*
|
||||
* Read the Multiple Message Enable bitfield from
|
||||
* Message control register.
|
||||
*
|
||||
* @dev: device to use
|
||||
* @func_num: EP function to use
|
||||
* @return msi count if OK, -EINVAL if msi were not enabled at host.
|
||||
*/
|
||||
int pci_ep_get_msix(struct udevice *dev, uint func_num);
|
||||
|
||||
/**
|
||||
* pci_ep_raise_irq() - raise a legacy, MSI or MSI-X interrupt
|
||||
*
|
||||
* @dev: device to set
|
||||
* @func_num: EP function to set
|
||||
* @type: type of irq to send
|
||||
* @interrupt_num: interrupt vector to use
|
||||
* @return 0 if OK, -ve on error
|
||||
*/
|
||||
int pci_ep_raise_irq(struct udevice *dev, uint func_num,
|
||||
enum pci_ep_irq_type type, uint interrupt_num);
|
||||
/**
|
||||
* pci_ep_start() - start the PCI link
|
||||
*
|
||||
* Enable PCI endpoint device and start link
|
||||
* process.
|
||||
*
|
||||
* @dev: device to set
|
||||
* @return 0 if OK, -ve on error
|
||||
*/
|
||||
int pci_ep_start(struct udevice *dev);
|
||||
|
||||
/**
|
||||
* pci_ep_stop() - stop the PCI link
|
||||
*
|
||||
* Disable PCI endpoint device and stop
|
||||
* link.
|
||||
*
|
||||
* @dev: device to set
|
||||
* @return 0 if OK, -ve on error
|
||||
*/
|
||||
int pci_ep_stop(struct udevice *dev);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue