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mx6: clock: Modify GPMI clock to support mx6sx
On mx6sx, the CCM register bits for GPMI are different as other mx6 platforms. Modify the GPMI clock function to support mx6sx. Signed-off-by: Ye.Li <B37916@freescale.com>
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@ -47,6 +47,17 @@ void setup_gpmi_io_clk(u32 cfg)
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
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MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
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MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK);
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#if defined(CONFIG_MX6SX)
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clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
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clrsetbits_le32(&imx_ccm->cs2cdr,
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MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK |
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MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK |
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MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK,
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cfg);
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setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);
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#else
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clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
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clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
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clrsetbits_le32(&imx_ccm->cs2cdr,
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clrsetbits_le32(&imx_ccm->cs2cdr,
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@ -56,6 +67,7 @@ void setup_gpmi_io_clk(u32 cfg)
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cfg);
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cfg);
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setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
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setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
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#endif
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setbits_le32(&imx_ccm->CCGR4,
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setbits_le32(&imx_ccm->CCGR4,
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MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
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MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
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