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https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
spi: sun4i: Driver cleanup
- drop unused macros. - use base instead of base_addr, for better code readability - move .probe and .ofdata_to_platdata functions in required places to add platdata support in future. - use sentinel sun4i_spi_ids. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
This commit is contained in:
Jagan Teki
parent
853f4511e9
commit
903e7cf37c
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@ -33,57 +33,16 @@
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#include <linux/iopoll.h>
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#define SUN4I_RXDATA_REG 0x00
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DECLARE_GLOBAL_DATA_PTR;
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#define SUN4I_TXDATA_REG 0x04
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#define SUN4I_CTL_REG 0x08
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#define SUN4I_CTL_ENABLE BIT(0)
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#define SUN4I_CTL_MASTER BIT(1)
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#define SUN4I_CTL_CPHA BIT(2)
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#define SUN4I_CTL_CPOL BIT(3)
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#define SUN4I_CTL_CS_ACTIVE_LOW BIT(4)
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#define SUN4I_CTL_LMTF BIT(6)
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#define SUN4I_CTL_TF_RST BIT(8)
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#define SUN4I_CTL_RF_RST BIT(9)
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#define SUN4I_CTL_XCH BIT(10)
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#define SUN4I_CTL_CS_MASK 0x3000
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#define SUN4I_CTL_CS(cs) (((cs) << 12) & SUN4I_CTL_CS_MASK)
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#define SUN4I_CTL_DHB BIT(15)
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#define SUN4I_CTL_CS_MANUAL BIT(16)
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#define SUN4I_CTL_CS_LEVEL BIT(17)
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#define SUN4I_CTL_TP BIT(18)
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#define SUN4I_INT_CTL_REG 0x0c
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#define SUN4I_INT_CTL_RF_F34 BIT(4)
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#define SUN4I_INT_CTL_TF_E34 BIT(12)
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#define SUN4I_INT_CTL_TC BIT(16)
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#define SUN4I_INT_STA_REG 0x10
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#define SUN4I_DMA_CTL_REG 0x14
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#define SUN4I_WAIT_REG 0x18
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#define SUN4I_CLK_CTL_REG 0x1c
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#define SUN4I_CLK_CTL_CDR2_MASK 0xff
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#define SUN4I_CLK_CTL_CDR2(div) ((div) & SUN4I_CLK_CTL_CDR2_MASK)
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#define SUN4I_CLK_CTL_CDR1_MASK 0xf
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#define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)
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#define SUN4I_CLK_CTL_DRS BIT(12)
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#define SUN4I_MAX_XFER_SIZE 0xffffff
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#define SUN4I_BURST_CNT_REG 0x20
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#define SUN4I_BURST_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
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#define SUN4I_XMIT_CNT_REG 0x24
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#define SUN4I_XMIT_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
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#define SUN4I_FIFO_STA_REG 0x28
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#define SUN4I_FIFO_STA_RF_CNT_BITS 0
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#define SUN4I_FIFO_STA_TF_CNT_MASK 0x7f
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#define SUN4I_FIFO_STA_TF_CNT_BITS 16
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/* sun4i spi registers */
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#define SUN4I_RXDATA_REG 0x00
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#define SUN4I_TXDATA_REG 0x04
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#define SUN4I_CTL_REG 0x08
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#define SUN4I_CLK_CTL_REG 0x1c
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#define SUN4I_BURST_CNT_REG 0x20
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#define SUN4I_XMIT_CNT_REG 0x24
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#define SUN4I_FIFO_STA_REG 0x28
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/* sun6i spi registers */
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#define SUN6I_GBL_CTL_REG 0x04
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@ -97,12 +56,25 @@
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#define SUN6I_TXDATA_REG 0x200
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#define SUN6I_RXDATA_REG 0x300
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#define SUN4I_SPI_MAX_RATE 24000000
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#define SUN4I_SPI_MIN_RATE 3000
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#define SUN4I_SPI_DEFAULT_RATE 1000000
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#define SUN4I_SPI_TIMEOUT_US 1000000
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/* sun spi bits */
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#define SUN4I_CTL_ENABLE BIT(0)
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#define SUN4I_CTL_MASTER BIT(1)
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#define SUN4I_CLK_CTL_CDR2_MASK 0xff
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#define SUN4I_CLK_CTL_CDR2(div) ((div) & SUN4I_CLK_CTL_CDR2_MASK)
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#define SUN4I_CLK_CTL_CDR1_MASK 0xf
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#define SUN4I_CLK_CTL_CDR1(div) (((div) & SUN4I_CLK_CTL_CDR1_MASK) << 8)
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#define SUN4I_CLK_CTL_DRS BIT(12)
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#define SUN4I_MAX_XFER_SIZE 0xffffff
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#define SUN4I_BURST_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
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#define SUN4I_XMIT_CNT(cnt) ((cnt) & SUN4I_MAX_XFER_SIZE)
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#define SUN4I_FIFO_STA_RF_CNT_BITS 0
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#define SPI_REG(priv, reg) ((priv)->base_addr + \
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#define SUN4I_SPI_MAX_RATE 24000000
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#define SUN4I_SPI_MIN_RATE 3000
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#define SUN4I_SPI_DEFAULT_RATE 1000000
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#define SUN4I_SPI_TIMEOUT_US 1000000
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#define SPI_REG(priv, reg) ((priv)->base + \
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(priv)->variant->regs[reg])
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#define SPI_BIT(priv, bit) ((priv)->variant->bits[bit])
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#define SPI_CS(priv, cs) (((cs) << SPI_BIT(priv, SPI_TCR_CS_SEL)) & \
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@ -149,7 +121,7 @@ struct sun4i_spi_variant {
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struct sun4i_spi_platdata {
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struct sun4i_spi_variant *variant;
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u32 base_addr;
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u32 base;
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u32 max_hz;
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};
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@ -157,7 +129,7 @@ struct sun4i_spi_priv {
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struct sun4i_spi_variant *variant;
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struct clk clk_ahb, clk_mod;
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struct reset_ctl reset;
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u32 base_addr;
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u32 base;
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u32 freq;
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u32 mode;
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@ -165,8 +137,6 @@ struct sun4i_spi_priv {
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u8 *rx_buf;
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};
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DECLARE_GLOBAL_DATA_PTR;
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static inline void sun4i_spi_drain_fifo(struct sun4i_spi_priv *priv, int len)
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{
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u8 byte;
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@ -328,56 +298,6 @@ err_ahb:
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return ret;
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}
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static int sun4i_spi_ofdata_to_platdata(struct udevice *bus)
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{
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struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
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int node = dev_of_offset(bus);
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plat->base_addr = devfdt_get_addr(bus);
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plat->variant = (struct sun4i_spi_variant *)dev_get_driver_data(bus);
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plat->max_hz = fdtdec_get_int(gd->fdt_blob, node,
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"spi-max-frequency",
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SUN4I_SPI_DEFAULT_RATE);
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if (plat->max_hz > SUN4I_SPI_MAX_RATE)
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plat->max_hz = SUN4I_SPI_MAX_RATE;
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return 0;
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}
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static int sun4i_spi_probe(struct udevice *bus)
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{
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struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
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struct sun4i_spi_priv *priv = dev_get_priv(bus);
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int ret;
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ret = clk_get_by_name(bus, "ahb", &priv->clk_ahb);
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if (ret) {
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dev_err(dev, "failed to get ahb clock\n");
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return ret;
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}
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ret = clk_get_by_name(bus, "mod", &priv->clk_mod);
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if (ret) {
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dev_err(dev, "failed to get mod clock\n");
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return ret;
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}
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ret = reset_get_by_index(bus, 0, &priv->reset);
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if (ret && ret != -ENOENT) {
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dev_err(dev, "failed to get reset\n");
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return ret;
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}
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sun4i_spi_parse_pins(bus);
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priv->variant = plat->variant;
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priv->base_addr = plat->base_addr;
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priv->freq = plat->max_hz;
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return 0;
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}
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static int sun4i_spi_claim_bus(struct udevice *dev)
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{
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struct sun4i_spi_priv *priv = dev_get_priv(dev->parent);
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@ -558,6 +478,56 @@ static const struct dm_spi_ops sun4i_spi_ops = {
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.set_mode = sun4i_spi_set_mode,
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};
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static int sun4i_spi_probe(struct udevice *bus)
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{
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struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
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struct sun4i_spi_priv *priv = dev_get_priv(bus);
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int ret;
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ret = clk_get_by_name(bus, "ahb", &priv->clk_ahb);
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if (ret) {
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dev_err(dev, "failed to get ahb clock\n");
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return ret;
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}
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ret = clk_get_by_name(bus, "mod", &priv->clk_mod);
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if (ret) {
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dev_err(dev, "failed to get mod clock\n");
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return ret;
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}
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ret = reset_get_by_index(bus, 0, &priv->reset);
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if (ret && ret != -ENOENT) {
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dev_err(dev, "failed to get reset\n");
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return ret;
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}
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sun4i_spi_parse_pins(bus);
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priv->variant = plat->variant;
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priv->base = plat->base;
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priv->freq = plat->max_hz;
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return 0;
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}
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static int sun4i_spi_ofdata_to_platdata(struct udevice *bus)
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{
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struct sun4i_spi_platdata *plat = dev_get_platdata(bus);
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int node = dev_of_offset(bus);
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plat->base = devfdt_get_addr(bus);
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plat->variant = (struct sun4i_spi_variant *)dev_get_driver_data(bus);
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plat->max_hz = fdtdec_get_int(gd->fdt_blob, node,
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"spi-max-frequency",
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SUN4I_SPI_DEFAULT_RATE);
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if (plat->max_hz > SUN4I_SPI_MAX_RATE)
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plat->max_hz = SUN4I_SPI_MAX_RATE;
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return 0;
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}
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static const unsigned long sun4i_spi_regs[] = {
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[SPI_GCR] = SUN4I_CTL_REG,
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[SPI_TCR] = SUN4I_CTL_REG,
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@ -649,7 +619,7 @@ static const struct udevice_id sun4i_spi_ids[] = {
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.compatible = "allwinner,sun8i-h3-spi",
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.data = (ulong)&sun8i_h3_spi_variant,
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},
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{ }
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{ /* sentinel */ }
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};
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U_BOOT_DRIVER(sun4i_spi) = {
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