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ARM: OMAP5: Add PRCM and Control information for SATA
Adds the necessary PRCM and Control register information for SATA on OMAP5. Signed-off-by: Roger Quadros <rogerq@ti.com>
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9c4b64fb61
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@ -203,8 +203,10 @@ struct prcm_regs const omap5_es1_prcm = {
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.cm_l3init_hsusbotg_clkctrl = 0x4a009360,
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.cm_l3init_hsusbotg_clkctrl = 0x4a009360,
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.cm_l3init_hsusbtll_clkctrl = 0x4a009368,
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.cm_l3init_hsusbtll_clkctrl = 0x4a009368,
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.cm_l3init_p1500_clkctrl = 0x4a009378,
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.cm_l3init_p1500_clkctrl = 0x4a009378,
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.cm_l3init_sata_clkctrl = 0x4a009388,
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.cm_l3init_fsusb_clkctrl = 0x4a0093d0,
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.cm_l3init_fsusb_clkctrl = 0x4a0093d0,
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.cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
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.cm_l3init_ocp2scp1_clkctrl = 0x4a0093e0,
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.cm_l3init_ocp2scp3_clkctrl = 0x4a0093e8,
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/* cm2.l4per */
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/* cm2.l4per */
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.cm_l4per_clkstctrl = 0x4a009400,
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.cm_l4per_clkstctrl = 0x4a009400,
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@ -296,6 +298,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
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.control_status = 0x4A002134,
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.control_status = 0x4A002134,
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.control_std_fuse_opp_vdd_mpu_2 = 0x4A0021B4,
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.control_std_fuse_opp_vdd_mpu_2 = 0x4A0021B4,
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.control_phy_power_usb = 0x4A002370,
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.control_phy_power_usb = 0x4A002370,
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.control_phy_power_sata = 0x4A002374,
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.control_padconf_core_base = 0x4A002800,
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.control_padconf_core_base = 0x4A002800,
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.control_paconf_global = 0x4A002DA0,
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.control_paconf_global = 0x4A002DA0,
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.control_paconf_mode = 0x4A002DA4,
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.control_paconf_mode = 0x4A002DA4,
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@ -698,6 +701,7 @@ struct prcm_regs const omap5_es2_prcm = {
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.cm_l3init_hsusbotg_clkctrl = 0x4a009660,
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.cm_l3init_hsusbotg_clkctrl = 0x4a009660,
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.cm_l3init_hsusbtll_clkctrl = 0x4a009668,
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.cm_l3init_hsusbtll_clkctrl = 0x4a009668,
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.cm_l3init_p1500_clkctrl = 0x4a009678,
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.cm_l3init_p1500_clkctrl = 0x4a009678,
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.cm_l3init_sata_clkctrl = 0x4a009688,
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.cm_l3init_fsusb_clkctrl = 0x4a0096d0,
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.cm_l3init_fsusb_clkctrl = 0x4a0096d0,
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.cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0,
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.cm_l3init_ocp2scp1_clkctrl = 0x4a0096e0,
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.cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8,
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.cm_l3init_ocp2scp3_clkctrl = 0x4a0096e8,
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@ -137,6 +137,9 @@
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#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
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#define HSMMC_CLKCTRL_CLKSEL_MASK (1 << 24)
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#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25)
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#define HSMMC_CLKCTRL_CLKSEL_DIV_MASK (1 << 25)
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/* CM_L3INIT_SATA_CLKCTRL */
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#define SATA_CLKCTRL_OPTFCLKEN_MASK (1 << 8)
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/* CM_WKUP_GPTIMER1_CLKCTRL */
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/* CM_WKUP_GPTIMER1_CLKCTRL */
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#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24)
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#define GPTIMER1_CLKCTRL_CLKSEL_MASK (1 << 24)
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@ -64,6 +64,9 @@
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/* QSPI */
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/* QSPI */
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#define QSPI_BASE 0x4B300000
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#define QSPI_BASE 0x4B300000
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/* SATA */
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#define DWC_AHSATA_BASE 0x4A140000
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/*
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/*
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* Hardware Register Details
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* Hardware Register Details
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*/
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*/
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@ -226,6 +226,7 @@ struct prcm_regs {
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u32 cm_l3init_hsusbotg_clkctrl;
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u32 cm_l3init_hsusbotg_clkctrl;
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u32 cm_l3init_hsusbtll_clkctrl;
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u32 cm_l3init_hsusbtll_clkctrl;
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u32 cm_l3init_p1500_clkctrl;
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u32 cm_l3init_p1500_clkctrl;
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u32 cm_l3init_sata_clkctrl;
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u32 cm_l3init_fsusb_clkctrl;
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u32 cm_l3init_fsusb_clkctrl;
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u32 cm_l3init_ocp2scp1_clkctrl;
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u32 cm_l3init_ocp2scp1_clkctrl;
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u32 cm_l3init_ocp2scp3_clkctrl;
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u32 cm_l3init_ocp2scp3_clkctrl;
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@ -366,6 +367,7 @@ struct omap_sys_ctrl_regs {
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u32 control_ldosram_mpu_voltage_ctrl;
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u32 control_ldosram_mpu_voltage_ctrl;
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u32 control_ldosram_core_voltage_ctrl;
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u32 control_ldosram_core_voltage_ctrl;
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u32 control_usbotghs_ctrl;
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u32 control_usbotghs_ctrl;
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u32 control_phy_power_sata;
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u32 control_padconf_core_base;
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u32 control_padconf_core_base;
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u32 control_paconf_global;
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u32 control_paconf_global;
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u32 control_paconf_mode;
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u32 control_paconf_mode;
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