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arm: Move tbu to arch_global_data

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Move this field into arch_global_data and tidy up.

Signed-off-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Simon Glass 2012-12-13 20:48:33 +00:00 committed by Tom Rini
parent b339051c0d
commit 8ff43b03e9
8 changed files with 29 additions and 29 deletions
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6
arch/arm/cpu/arm920t/a320/timer.c
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@ -75,7 +75,7 @@ int timer_init(void)
writel(cr, &tmr->cr); writel(cr, &tmr->cr);
gd->arch.timer_rate_hz = TIMER_CLOCK; gd->arch.timer_rate_hz = TIMER_CLOCK;
gd->tbu = gd->tbl = 0; gd->arch.tbu = gd->tbl = 0;
return 0; return 0;
} }
@ -90,9 +90,9 @@ unsigned long long get_ticks(void)
/* increment tbu if tbl has rolled over */ /* increment tbu if tbl has rolled over */
if (now < gd->tbl) if (now < gd->tbl)
gd->tbu++; gd->arch.tbu++;
gd->tbl = now; gd->tbl = now;
return (((unsigned long long)gd->tbu) << 32) | gd->tbl; return (((unsigned long long)gd->arch.tbu) << 32) | gd->tbl;
} }
void __udelay(unsigned long usec) void __udelay(unsigned long usec)

14
arch/arm/cpu/arm920t/s3c24x0/timer.c
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@ -45,17 +45,17 @@ int timer_init(void)
/* use PWM Timer 4 because it has no output */ /* use PWM Timer 4 because it has no output */
/* prescaler for Timer 4 is 16 */ /* prescaler for Timer 4 is 16 */
writel(0x0f00, &timers->tcfg0); writel(0x0f00, &timers->tcfg0);
if (gd->tbu == 0) { if (gd->arch.tbu == 0) {
/* /*
* for 10 ms clock period @ PCLK with 4 bit divider = 1/2 * for 10 ms clock period @ PCLK with 4 bit divider = 1/2
* (default) and prescaler = 16. Should be 10390 * (default) and prescaler = 16. Should be 10390
* @33.25MHz and 15625 @ 50 MHz * @33.25MHz and 15625 @ 50 MHz
*/ */
gd->tbu = get_PCLK() / (2 * 16 * 100); gd->arch.tbu = get_PCLK() / (2 * 16 * 100);
gd->arch.timer_rate_hz = get_PCLK() / (2 * 16); gd->arch.timer_rate_hz = get_PCLK() / (2 * 16);
} }
/* load value for 10 ms timeout */ /* load value for 10 ms timeout */
writel(gd->tbu, &timers->tcntb4); writel(gd->arch.tbu, &timers->tcntb4);
/* auto load, manual update of timer 4 */ /* auto load, manual update of timer 4 */
tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000; tmr = (readl(&timers->tcon) & ~0x0700000) | 0x0600000;
writel(tmr, &timers->tcon); writel(tmr, &timers->tcon);
@ -82,7 +82,7 @@ void __udelay (unsigned long usec)
ulong start = get_ticks(); ulong start = get_ticks();
tmo = usec / 1000; tmo = usec / 1000;
tmo *= (gd->tbu * 100); tmo *= (gd->arch.tbu * 100);
tmo /= 1000; tmo /= 1000;
while ((ulong) (get_ticks() - start) < tmo) while ((ulong) (get_ticks() - start) < tmo)
@ -104,10 +104,10 @@ void udelay_masked(unsigned long usec)
if (usec >= 1000) { if (usec >= 1000) {
tmo = usec / 1000; tmo = usec / 1000;
tmo *= (gd->tbu * 100); tmo *= (gd->arch.tbu * 100);
tmo /= 1000; tmo /= 1000;
} else { } else {
tmo = usec * (gd->tbu * 100); tmo = usec * (gd->arch.tbu * 100);
tmo /= (1000 * 1000); tmo /= (1000 * 1000);
} }
@ -133,7 +133,7 @@ unsigned long long get_ticks(void)
gd->tbl += gd->lastinc - now; gd->tbl += gd->lastinc - now;
} else { } else {
/* we have an overflow ... */ /* we have an overflow ... */
gd->tbl += gd->lastinc + gd->tbu - now; gd->tbl += gd->lastinc + gd->arch.tbu - now;
} }
gd->lastinc = now; gd->lastinc = now;

12
arch/arm/cpu/arm926ejs/armada100/timer.c
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@ -61,7 +61,7 @@ struct armd1tmr_registers {
#define COUNT_RD_REQ 0x1 #define COUNT_RD_REQ 0x1
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
/* Using gd->tbu from timestamp and gd->tbl for lastdec */ /* Using gd->arch.tbu from timestamp and gd->tbl for lastdec */
/* For preventing risk of instability in reading counter value, /* For preventing risk of instability in reading counter value,
* first set read request to register cvwr and then read same * first set read request to register cvwr and then read same
@ -84,14 +84,14 @@ ulong get_timer_masked(void)
if (now >= gd->tbl) { if (now >= gd->tbl) {
/* normal mode */ /* normal mode */
gd->tbu += now - gd->tbl; gd->arch.tbu += now - gd->tbl;
} else { } else {
/* we have an overflow ... */ /* we have an overflow ... */
gd->tbu += now + TIMER_LOAD_VAL - gd->tbl; gd->arch.tbu += now + TIMER_LOAD_VAL - gd->tbl;
} }
gd->tbl = now; gd->tbl = now;
return gd->tbu; return gd->arch.tbu;
} }
ulong get_timer(ulong base) ulong get_timer(ulong base)
@ -135,9 +135,9 @@ int timer_init(void)
/* Enable timer 0 */ /* Enable timer 0 */
writel(0x1, &armd1timers->cer); writel(0x1, &armd1timers->cer);
/* init the gd->tbu and gd->tbl value */ /* init the gd->arch.tbu and gd->tbl value */
gd->tbl = read_timer(); gd->tbl = read_timer();
gd->tbu = 0; gd->arch.tbu = 0;
return 0; return 0;
} }

6
arch/arm/cpu/arm926ejs/at91/timer.c
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@ -80,7 +80,7 @@ int timer_init(void)
writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr); writel(TIMER_LOAD_VAL | AT91_PIT_MR_EN , &pit->mr);
gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16; gd->arch.timer_rate_hz = gd->arch.mck_rate_hz / 16;
gd->tbu = gd->tbl = 0; gd->arch.tbu = gd->tbl = 0;
return 0; return 0;
} }
@ -96,9 +96,9 @@ unsigned long long get_ticks(void)
/* increment tbu if tbl has rolled over */ /* increment tbu if tbl has rolled over */
if (now < gd->tbl) if (now < gd->tbl)
gd->tbu++; gd->arch.tbu++;
gd->tbl = now; gd->tbl = now;
return (((unsigned long long)gd->tbu) << 32) | gd->tbl; return (((unsigned long long)gd->arch.tbu) << 32) | gd->tbl;
} }
void __udelay(unsigned long usec) void __udelay(unsigned long usec)

4
arch/arm/cpu/arm926ejs/davinci/timer.c
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@ -75,10 +75,10 @@ unsigned long long get_ticks(void)
/* increment tbu if tbl has rolled over */ /* increment tbu if tbl has rolled over */
if (now < gd->tbl) if (now < gd->tbl)
gd->tbu++; gd->arch.tbu++;
gd->tbl = now; gd->tbl = now;
return (((unsigned long long)gd->tbu) << 32) | gd->tbl; return (((unsigned long long)gd->arch.tbu) << 32) | gd->tbl;
} }
ulong get_timer(ulong base) ulong get_timer(ulong base)

12
arch/arm/cpu/arm926ejs/pantheon/timer.c
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@ -60,7 +60,7 @@ struct panthtmr_registers {
#define COUNT_RD_REQ 0x1 #define COUNT_RD_REQ 0x1
DECLARE_GLOBAL_DATA_PTR; DECLARE_GLOBAL_DATA_PTR;
/* Using gd->tbu from timestamp and gd->tbl for lastdec */ /* Using gd->arch.tbu from timestamp and gd->tbl for lastdec */
/* /*
* For preventing risk of instability in reading counter value, * For preventing risk of instability in reading counter value,
@ -92,14 +92,14 @@ ulong get_timer_masked(void)
if (now >= gd->tbl) { if (now >= gd->tbl) {
/* normal mode */ /* normal mode */
gd->tbu += now - gd->tbl; gd->arch.tbu += now - gd->tbl;
} else { } else {
/* we have an overflow ... */ /* we have an overflow ... */
gd->tbu += now + TIMER_LOAD_VAL - gd->tbl; gd->arch.tbu += now + TIMER_LOAD_VAL - gd->tbl;
} }
gd->tbl = now; gd->tbl = now;
return gd->tbu; return gd->arch.tbu;
} }
ulong get_timer(ulong base) ulong get_timer(ulong base)
@ -144,9 +144,9 @@ int timer_init(void)
/* Enable timer 0 */ /* Enable timer 0 */
writel(0x1, &panthtimers->cer); writel(0x1, &panthtimers->cer);
/* init the gd->tbu and gd->tbl value */ /* init the gd->arch.tbu and gd->tbl value */
gd->tbl = read_timer(); gd->tbl = read_timer();
gd->tbu = 0; gd->arch.tbu = 0;
return 0; return 0;
} }

2
arch/arm/cpu/armv7/u8500/timer.c
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@ -132,7 +132,7 @@ ulong get_timer(ulong base)
/* /*
* Emulation of Power architecture long long timebase. * Emulation of Power architecture long long timebase.
* *
* TODO: Support gd->tbu for real long long timebase. * TODO: Support gd->arch.tbu for real long long timebase.
*/ */
unsigned long long get_ticks(void) unsigned long long get_ticks(void)
{ {

2
arch/arm/include/asm/global_data.h
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@ -37,6 +37,7 @@ struct arch_global_data {
#endif #endif
/* "static data" needed by most of timer.c on ARM platforms */ /* "static data" needed by most of timer.c on ARM platforms */
unsigned long timer_rate_hz; unsigned long timer_rate_hz;
unsigned long tbu;
}; };
/* /*
@ -64,7 +65,6 @@ typedef struct global_data {
#ifdef CONFIG_ARM #ifdef CONFIG_ARM
/* "static data" needed by most of timer.c on ARM platforms */ /* "static data" needed by most of timer.c on ARM platforms */
unsigned long tbl; unsigned long tbl;
unsigned long tbu;
unsigned long long timer_reset_value; unsigned long long timer_reset_value;
unsigned long lastinc; unsigned long lastinc;
#endif #endif