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powerpc/t4240: fix per pci endpoint liodn offsets

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Update the code that builds the pci endpoint liodn
offset list so that it doesn't overlap with other
liodns and doesn't generate negative offsets like:

  fsl,liodn-offset-list = <0 0xffffffcd 0xffffffcf
                             0xffffffd1 0xffffffd3
                             0xffffffd5 0xffffffd7
                             0xffffffd9 0xffffffdb>;

The update consists in adding a parameter to the
function that builds the list to specify the base
liodn.
On PCI v2.4 use the old base = 256 and, on PCI 3.0
where some of the PCIE liodns are larger than 256,
use a base = 1024. The version check is based on
the PCI controller's version register.

Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com>
Cc: Scott Wood <scottwood@freescale.com>
Cc: York Sun <yorksun@freescale.com>
This commit is contained in:
Laurentiu TUDOR 2013-10-23 15:20:27 +03:00 committed by York Sun
parent b4125a235e
commit 8f9fe660fc
2 changed files with 24 additions and 5 deletions
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25
arch/powerpc/cpu/mpc85xx/liodn.c
View File

@ -239,9 +239,9 @@ static void fdt_fixup_srio_liodn(void *blob, struct srio_liodn_id_table *tbl)
#endif
#define CONFIG_SYS_MAX_PCI_EPS 8
#define CONFIG_SYS_PCI_EP_LIODN_START 256
static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat)
static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat,
int ep_liodn_start)
{
int off, pci_idx = 0, pci_cnt = 0, i, rc;
const uint32_t *base_liodn;
@ -271,7 +271,7 @@ static void fdt_fixup_pci_liodn_offsets(void *fdt, const char *compat)
continue;
}
for (i = 0; i < CONFIG_SYS_MAX_PCI_EPS; i++)
liodn_offs[i + 1] = CONFIG_SYS_PCI_EP_LIODN_START +
liodn_offs[i + 1] = ep_liodn_start +
i * pci_cnt + pci_idx - *base_liodn;
rc = fdt_setprop(fdt, off, "fsl,liodn-offset-list",
liodn_offs, sizeof(liodn_offs));
@ -338,5 +338,22 @@ void fdt_fixup_liodn(void *blob)
fdt_fixup_liodn_tbl(blob, rman_liodn_tbl, rman_liodn_tbl_sz);
#endif
fdt_fixup_pci_liodn_offsets(blob, "fsl,qoriq-pcie-v2.4");
ccsr_pcix_t *pcix = (ccsr_pcix_t *)CONFIG_SYS_PCIE1_ADDR;
int pci_ver = pcix->ipver1 & 0xffff, liodn_base = 0;
if (pci_ver >= 0x0204) {
if (pci_ver >= 0x0300)
liodn_base = 1024;
else
liodn_base = 256;
}
if (liodn_base) {
char compat[32];
sprintf(compat, "fsl,qoriq-pcie-v%d.%d",
(pci_ver & 0xff00) >> 8, pci_ver & 0xff);
fdt_fixup_pci_liodn_offsets(blob, compat, liodn_base);
fdt_fixup_pci_liodn_offsets(blob, "fsl,qoriq-pcie", liodn_base);
}
}

4
arch/powerpc/include/asm/immap_85xx.h
View File

@ -282,7 +282,9 @@ typedef struct ccsr_pcix {
u32 int_ack; /* PCIX IRQ Acknowledge */
u8 res000c[52];
u32 liodn_base; /* PCIX LIODN base register */
u8 res0044[3004];
u8 res0044[2996];
u32 ipver1; /* PCIX IP block revision register 1 */
u32 ipver2; /* PCIX IP block revision register 2 */
u32 potar0; /* PCIX Outbound Transaction Addr 0 */
u32 potear0; /* PCIX Outbound Translation Extended Addr 0 */
u32 powbar0; /* PCIX Outbound Window Base Addr 0 */