reset: Add IPQ40xx reset controller driver
On Qualcomm IPQ40xx SoC series, GCC clock IP also handles the resets. So since this will be needed by further drivers, lets add a driver for the reset controller. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
This commit is contained in:
Robert Marko
Tom Rini
parent
6ef099b29e
commit
8ef7df5df3
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@ -238,6 +238,8 @@ M: Luka Perkov <luka.perkov@sartura.hr>
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S: Maintained
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F: arch/arm/mach-ipq40xx/
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F: include/dt-bindings/clock/qcom,ipq4019-gcc.h
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F: include/dt-bindings/reset/qcom,ipq4019-reset.h
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F: drivers/reset/reset-ipq4019.c
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ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
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M: Stefan Roese <sr@denx.de>
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@ -148,6 +148,14 @@ config RESET_IMX7
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help
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Support for reset controller on i.MX7/8 SoCs.
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config RESET_IPQ419
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bool "Reset driver for Qualcomm IPQ40xx SoCs"
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depends on DM_RESET && ARCH_IPQ40XX
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default y
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help
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Support for reset controller on Qualcomm
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IPQ40xx SoCs.
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config RESET_SIFIVE
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bool "Reset Driver for SiFive SoC's"
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depends on DM_RESET && CLK_SIFIVE_FU540_PRCI && TARGET_SIFIVE_FU540
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@ -23,6 +23,7 @@ obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o
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obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
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obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
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obj-$(CONFIG_RESET_IMX7) += reset-imx7.o
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obj-$(CONFIG_RESET_IPQ419) += reset-ipq4019.o
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obj-$(CONFIG_RESET_SIFIVE) += reset-sifive.o
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obj-$(CONFIG_RESET_SYSCON) += reset-syscon.o
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obj-$(CONFIG_RESET_RASPBERRYPI) += reset-raspberrypi.o
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@ -0,0 +1,173 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2020 Sartura Ltd.
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*
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* Author: Robert Marko <robert.marko@sartura.hr>
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*
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* Based on Linux driver
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*/
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#include <asm/io.h>
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#include <common.h>
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#include <dm.h>
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#include <dt-bindings/reset/qcom,ipq4019-reset.h>
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#include <reset-uclass.h>
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#include <linux/bitops.h>
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#include <malloc.h>
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struct ipq4019_reset_priv {
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phys_addr_t base;
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};
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struct qcom_reset_map {
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unsigned int reg;
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u8 bit;
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};
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static const struct qcom_reset_map gcc_ipq4019_resets[] = {
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[WIFI0_CPU_INIT_RESET] = { 0x1f008, 5 },
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[WIFI0_RADIO_SRIF_RESET] = { 0x1f008, 4 },
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[WIFI0_RADIO_WARM_RESET] = { 0x1f008, 3 },
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[WIFI0_RADIO_COLD_RESET] = { 0x1f008, 2 },
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[WIFI0_CORE_WARM_RESET] = { 0x1f008, 1 },
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[WIFI0_CORE_COLD_RESET] = { 0x1f008, 0 },
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[WIFI1_CPU_INIT_RESET] = { 0x20008, 5 },
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[WIFI1_RADIO_SRIF_RESET] = { 0x20008, 4 },
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[WIFI1_RADIO_WARM_RESET] = { 0x20008, 3 },
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[WIFI1_RADIO_COLD_RESET] = { 0x20008, 2 },
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[WIFI1_CORE_WARM_RESET] = { 0x20008, 1 },
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[WIFI1_CORE_COLD_RESET] = { 0x20008, 0 },
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[USB3_UNIPHY_PHY_ARES] = { 0x1e038, 5 },
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[USB3_HSPHY_POR_ARES] = { 0x1e038, 4 },
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[USB3_HSPHY_S_ARES] = { 0x1e038, 2 },
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[USB2_HSPHY_POR_ARES] = { 0x1e01c, 4 },
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[USB2_HSPHY_S_ARES] = { 0x1e01c, 2 },
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[PCIE_PHY_AHB_ARES] = { 0x1d010, 11 },
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[PCIE_AHB_ARES] = { 0x1d010, 10 },
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[PCIE_PWR_ARES] = { 0x1d010, 9 },
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[PCIE_PIPE_STICKY_ARES] = { 0x1d010, 8 },
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[PCIE_AXI_M_STICKY_ARES] = { 0x1d010, 7 },
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[PCIE_PHY_ARES] = { 0x1d010, 6 },
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[PCIE_PARF_XPU_ARES] = { 0x1d010, 5 },
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[PCIE_AXI_S_XPU_ARES] = { 0x1d010, 4 },
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[PCIE_AXI_M_VMIDMT_ARES] = { 0x1d010, 3 },
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[PCIE_PIPE_ARES] = { 0x1d010, 2 },
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[PCIE_AXI_S_ARES] = { 0x1d010, 1 },
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[PCIE_AXI_M_ARES] = { 0x1d010, 0 },
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[ESS_RESET] = { 0x12008, 0},
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[GCC_BLSP1_BCR] = {0x01000, 0},
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[GCC_BLSP1_QUP1_BCR] = {0x02000, 0},
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[GCC_BLSP1_UART1_BCR] = {0x02038, 0},
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[GCC_BLSP1_QUP2_BCR] = {0x03008, 0},
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[GCC_BLSP1_UART2_BCR] = {0x03028, 0},
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[GCC_BIMC_BCR] = {0x04000, 0},
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[GCC_TLMM_BCR] = {0x05000, 0},
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[GCC_IMEM_BCR] = {0x0E000, 0},
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[GCC_ESS_BCR] = {0x12008, 0},
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[GCC_PRNG_BCR] = {0x13000, 0},
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[GCC_BOOT_ROM_BCR] = {0x13008, 0},
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[GCC_CRYPTO_BCR] = {0x16000, 0},
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[GCC_SDCC1_BCR] = {0x18000, 0},
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[GCC_SEC_CTRL_BCR] = {0x1A000, 0},
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[GCC_AUDIO_BCR] = {0x1B008, 0},
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[GCC_QPIC_BCR] = {0x1C000, 0},
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[GCC_PCIE_BCR] = {0x1D000, 0},
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[GCC_USB2_BCR] = {0x1E008, 0},
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[GCC_USB2_PHY_BCR] = {0x1E018, 0},
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[GCC_USB3_BCR] = {0x1E024, 0},
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[GCC_USB3_PHY_BCR] = {0x1E034, 0},
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[GCC_SYSTEM_NOC_BCR] = {0x21000, 0},
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[GCC_PCNOC_BCR] = {0x2102C, 0},
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[GCC_DCD_BCR] = {0x21038, 0},
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[GCC_SNOC_BUS_TIMEOUT0_BCR] = {0x21064, 0},
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[GCC_SNOC_BUS_TIMEOUT1_BCR] = {0x2106C, 0},
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[GCC_SNOC_BUS_TIMEOUT2_BCR] = {0x21074, 0},
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[GCC_SNOC_BUS_TIMEOUT3_BCR] = {0x2107C, 0},
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[GCC_PCNOC_BUS_TIMEOUT0_BCR] = {0x21084, 0},
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[GCC_PCNOC_BUS_TIMEOUT1_BCR] = {0x2108C, 0},
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[GCC_PCNOC_BUS_TIMEOUT2_BCR] = {0x21094, 0},
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[GCC_PCNOC_BUS_TIMEOUT3_BCR] = {0x2109C, 0},
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[GCC_PCNOC_BUS_TIMEOUT4_BCR] = {0x210A4, 0},
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[GCC_PCNOC_BUS_TIMEOUT5_BCR] = {0x210AC, 0},
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[GCC_PCNOC_BUS_TIMEOUT6_BCR] = {0x210B4, 0},
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[GCC_PCNOC_BUS_TIMEOUT7_BCR] = {0x210BC, 0},
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[GCC_PCNOC_BUS_TIMEOUT8_BCR] = {0x210C4, 0},
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[GCC_PCNOC_BUS_TIMEOUT9_BCR] = {0x210CC, 0},
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[GCC_TCSR_BCR] = {0x22000, 0},
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[GCC_MPM_BCR] = {0x24000, 0},
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[GCC_SPDM_BCR] = {0x25000, 0},
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};
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static int ipq4019_reset_assert(struct reset_ctl *rst)
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{
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struct ipq4019_reset_priv *priv = dev_get_priv(rst->dev);
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const struct qcom_reset_map *reset_map = gcc_ipq4019_resets;
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const struct qcom_reset_map *map;
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u32 value;
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map = &reset_map[rst->id];
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value = readl(priv->base + map->reg);
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value |= BIT(map->bit);
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writel(value, priv->base + map->reg);
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return 0;
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}
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static int ipq4019_reset_deassert(struct reset_ctl *rst)
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{
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struct ipq4019_reset_priv *priv = dev_get_priv(rst->dev);
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const struct qcom_reset_map *reset_map = gcc_ipq4019_resets;
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const struct qcom_reset_map *map;
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u32 value;
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map = &reset_map[rst->id];
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value = readl(priv->base + map->reg);
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value &= ~BIT(map->bit);
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writel(value, priv->base + map->reg);
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return 0;
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}
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static int ipq4019_reset_free(struct reset_ctl *rst)
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{
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return 0;
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}
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static int ipq4019_reset_request(struct reset_ctl *rst)
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{
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return 0;
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}
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static const struct reset_ops ipq4019_reset_ops = {
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.request = ipq4019_reset_request,
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.rfree = ipq4019_reset_free,
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.rst_assert = ipq4019_reset_assert,
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.rst_deassert = ipq4019_reset_deassert,
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};
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static const struct udevice_id ipq4019_reset_ids[] = {
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{ .compatible = "qcom,gcc-reset-ipq4019" },
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{ }
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};
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static int ipq4019_reset_probe(struct udevice *dev)
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{
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struct ipq4019_reset_priv *priv = dev_get_priv(dev);
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priv->base = dev_read_addr(dev);
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if (priv->base == FDT_ADDR_T_NONE)
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return -EINVAL;
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return 0;
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}
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U_BOOT_DRIVER(ipq4019_reset) = {
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.name = "ipq4019_reset",
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.id = UCLASS_RESET,
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.of_match = ipq4019_reset_ids,
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.ops = &ipq4019_reset_ops,
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.probe = ipq4019_reset_probe,
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.priv_auto_alloc_size = sizeof(struct ipq4019_reset_priv),
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};
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@ -0,0 +1,92 @@
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/* Copyright (c) 2015 The Linux Foundation. All rights reserved.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#ifndef __QCOM_RESET_IPQ4019_H__
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#define __QCOM_RESET_IPQ4019_H__
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#define WIFI0_CPU_INIT_RESET 0
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#define WIFI0_RADIO_SRIF_RESET 1
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#define WIFI0_RADIO_WARM_RESET 2
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#define WIFI0_RADIO_COLD_RESET 3
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#define WIFI0_CORE_WARM_RESET 4
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#define WIFI0_CORE_COLD_RESET 5
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#define WIFI1_CPU_INIT_RESET 6
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#define WIFI1_RADIO_SRIF_RESET 7
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#define WIFI1_RADIO_WARM_RESET 8
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#define WIFI1_RADIO_COLD_RESET 9
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#define WIFI1_CORE_WARM_RESET 10
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#define WIFI1_CORE_COLD_RESET 11
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#define USB3_UNIPHY_PHY_ARES 12
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#define USB3_HSPHY_POR_ARES 13
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#define USB3_HSPHY_S_ARES 14
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#define USB2_HSPHY_POR_ARES 15
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#define USB2_HSPHY_S_ARES 16
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#define PCIE_PHY_AHB_ARES 17
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#define PCIE_AHB_ARES 18
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#define PCIE_PWR_ARES 19
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#define PCIE_PIPE_STICKY_ARES 20
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#define PCIE_AXI_M_STICKY_ARES 21
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#define PCIE_PHY_ARES 22
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#define PCIE_PARF_XPU_ARES 23
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#define PCIE_AXI_S_XPU_ARES 24
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#define PCIE_AXI_M_VMIDMT_ARES 25
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#define PCIE_PIPE_ARES 26
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#define PCIE_AXI_S_ARES 27
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#define PCIE_AXI_M_ARES 28
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#define ESS_RESET 29
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#define GCC_BLSP1_BCR 30
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#define GCC_BLSP1_QUP1_BCR 31
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#define GCC_BLSP1_UART1_BCR 32
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#define GCC_BLSP1_QUP2_BCR 33
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#define GCC_BLSP1_UART2_BCR 34
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#define GCC_BIMC_BCR 35
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#define GCC_TLMM_BCR 36
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#define GCC_IMEM_BCR 37
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#define GCC_ESS_BCR 38
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#define GCC_PRNG_BCR 39
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#define GCC_BOOT_ROM_BCR 40
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#define GCC_CRYPTO_BCR 41
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#define GCC_SDCC1_BCR 42
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#define GCC_SEC_CTRL_BCR 43
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#define GCC_AUDIO_BCR 44
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#define GCC_QPIC_BCR 45
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#define GCC_PCIE_BCR 46
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#define GCC_USB2_BCR 47
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#define GCC_USB2_PHY_BCR 48
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#define GCC_USB3_BCR 49
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#define GCC_USB3_PHY_BCR 50
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#define GCC_SYSTEM_NOC_BCR 51
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#define GCC_PCNOC_BCR 52
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#define GCC_DCD_BCR 53
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#define GCC_SNOC_BUS_TIMEOUT0_BCR 54
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#define GCC_SNOC_BUS_TIMEOUT1_BCR 55
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#define GCC_SNOC_BUS_TIMEOUT2_BCR 56
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#define GCC_SNOC_BUS_TIMEOUT3_BCR 57
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#define GCC_PCNOC_BUS_TIMEOUT0_BCR 58
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#define GCC_PCNOC_BUS_TIMEOUT1_BCR 59
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#define GCC_PCNOC_BUS_TIMEOUT2_BCR 60
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#define GCC_PCNOC_BUS_TIMEOUT3_BCR 61
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#define GCC_PCNOC_BUS_TIMEOUT4_BCR 62
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#define GCC_PCNOC_BUS_TIMEOUT5_BCR 63
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#define GCC_PCNOC_BUS_TIMEOUT6_BCR 64
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#define GCC_PCNOC_BUS_TIMEOUT7_BCR 65
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#define GCC_PCNOC_BUS_TIMEOUT8_BCR 66
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#define GCC_PCNOC_BUS_TIMEOUT9_BCR 67
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#define GCC_TCSR_BCR 68
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#define GCC_QDSS_BCR 69
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#define GCC_MPM_BCR 70
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#define GCC_SPDM_BCR 71
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#endif
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