mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-23 05:00:24 +09:00
poplar: sync up device tree with kernel 4.20
It adds missing pinctrl headers, updates clock header and sync up Poplar device tree with kernel 4.20 release. Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This commit is contained in:
Shawn Guo
Tom Rini
parent
fbf4152ba6
commit
8eef803a27
@ -1,14 +1,17 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* DTS File for HiSilicon Poplar Development Board
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*
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* Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
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*
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* Released under the GPLv2 only.
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* SPDX-License-Identifier: GPL-2.0
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*/
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include "hi3798cv200.dtsi"
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#include "poplar-pinctrl.dtsi"
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/ {
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model = "HiSilicon Poplar Development Board";
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@ -59,6 +62,33 @@
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default-state = "off";
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};
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};
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reg_pcie: regulator-pcie {
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compatible = "regulator-fixed";
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regulator-name = "3V3_PCIE0";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio6 7 0>;
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enable-active-high;
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};
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};
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&ehci {
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status = "okay";
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};
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&emmc {
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pinctrl-names = "default";
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pinctrl-0 = <&emmc_pins_1 &emmc_pins_2
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&emmc_pins_3 &emmc_pins_4>;
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fifo-depth = <256>;
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clock-frequency = <200000000>;
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cap-mmc-highspeed;
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mmc-ddr-1_8v;
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mmc-hs200-1_8v;
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non-removable;
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bus-width = <8>;
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status = "okay";
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};
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&gmac1 {
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@ -76,17 +106,17 @@
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&gpio1 {
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status = "okay";
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gpio-line-names = "LS-GPIO-E", "",
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gpio-line-names = "GPIO-E", "",
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"", "",
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"", "LS-GPIO-F",
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"", "LS-GPIO-J";
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"", "GPIO-F",
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"", "GPIO-J";
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};
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&gpio2 {
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status = "okay";
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gpio-line-names = "LS-GPIO-H", "LS-GPIO-I",
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"LS-GPIO-L", "LS-GPIO-G",
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"LS-GPIO-K", "",
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gpio-line-names = "GPIO-H", "GPIO-I",
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"GPIO-L", "GPIO-G",
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"GPIO-K", "",
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"", "";
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};
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@ -94,15 +124,15 @@
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status = "okay";
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gpio-line-names = "", "",
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"", "",
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"LS-GPIO-C", "",
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"", "LS-GPIO-B";
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"GPIO-C", "",
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"", "GPIO-B";
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};
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&gpio4 {
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status = "okay";
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gpio-line-names = "", "",
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"", "",
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"", "LS-GPIO-D",
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"", "GPIO-D",
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"", "";
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};
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@ -110,7 +140,7 @@
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status = "okay";
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gpio-line-names = "", "USER-LED-1",
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"USER-LED-2", "",
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"", "LS-GPIO-A",
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"", "GPIO-A",
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"", "";
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};
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@ -144,6 +174,22 @@
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status = "okay";
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};
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&ohci {
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status = "okay";
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};
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&pcie {
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reset-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
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vpcie-supply = <®_pcie>;
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status = "okay";
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};
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&sd0 {
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bus-width = <4>;
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cap-sd-highspeed;
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status = "okay";
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};
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&spi0 {
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status = "okay";
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label = "LS-SPI0";
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@ -1,12 +1,16 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* DTS File for HiSilicon Hi3798cv200 SoC.
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*
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* Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
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*
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* Released under the GPLv2 only.
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* SPDX-License-Identifier: GPL-2.0
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*/
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#include <dt-bindings/clock/histb-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/reset/ti-syscon.h>
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/ {
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@ -104,6 +108,113 @@
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#reset-cells = <2>;
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};
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perictrl: peripheral-controller@8a20000 {
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compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
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"simple-mfd";
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reg = <0x8a20000 0x1000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x8a20000 0x1000>;
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usb2_phy1: usb2-phy@120 {
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compatible = "hisilicon,hi3798cv200-usb2-phy";
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reg = <0x120 0x4>;
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clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
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resets = <&crg 0xbc 4>;
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#address-cells = <1>;
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#size-cells = <0>;
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usb2_phy1_port0: phy@0 {
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reg = <0>;
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#phy-cells = <0>;
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resets = <&crg 0xbc 8>;
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};
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usb2_phy1_port1: phy@1 {
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reg = <1>;
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#phy-cells = <0>;
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resets = <&crg 0xbc 9>;
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};
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};
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usb2_phy2: usb2-phy@124 {
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compatible = "hisilicon,hi3798cv200-usb2-phy";
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reg = <0x124 0x4>;
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clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
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resets = <&crg 0xbc 6>;
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#address-cells = <1>;
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#size-cells = <0>;
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usb2_phy2_port0: phy@0 {
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reg = <0>;
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#phy-cells = <0>;
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resets = <&crg 0xbc 10>;
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};
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};
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combphy0: phy@850 {
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compatible = "hisilicon,hi3798cv200-combphy";
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reg = <0x850 0x8>;
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#phy-cells = <1>;
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clocks = <&crg HISTB_COMBPHY0_CLK>;
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resets = <&crg 0x188 4>;
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assigned-clocks = <&crg HISTB_COMBPHY0_CLK>;
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assigned-clock-rates = <100000000>;
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hisilicon,fixed-mode = <PHY_TYPE_USB3>;
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};
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combphy1: phy@858 {
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compatible = "hisilicon,hi3798cv200-combphy";
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reg = <0x858 0x8>;
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#phy-cells = <1>;
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clocks = <&crg HISTB_COMBPHY1_CLK>;
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resets = <&crg 0x188 12>;
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assigned-clocks = <&crg HISTB_COMBPHY1_CLK>;
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assigned-clock-rates = <100000000>;
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hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
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};
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};
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pmx0: pinconf@8a21000 {
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compatible = "pinconf-single";
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reg = <0x8a21000 0x180>;
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pinctrl-single,register-width = <32>;
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pinctrl-single,function-mask = <7>;
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pinctrl-single,gpio-range = <
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&range 0 8 2 /* GPIO 0 */
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&range 8 1 0 /* GPIO 1 */
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&range 9 4 2
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&range 13 1 0
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&range 14 1 1
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&range 15 1 0
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&range 16 5 0 /* GPIO 2 */
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&range 21 3 1
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&range 24 4 1 /* GPIO 3 */
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&range 28 2 2
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&range 86 1 1
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&range 87 1 0
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&range 30 4 2 /* GPIO 4 */
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&range 34 3 0
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&range 37 1 2
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&range 38 3 2 /* GPIO 6 */
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&range 41 5 0
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&range 46 8 1 /* GPIO 7 */
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&range 54 8 1 /* GPIO 8 */
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&range 64 7 1 /* GPIO 9 */
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&range 71 1 0
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&range 72 6 1 /* GPIO 10 */
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&range 78 1 0
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&range 79 1 1
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&range 80 6 1 /* GPIO 11 */
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&range 70 2 1
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&range 88 8 0 /* GPIO 12 */
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>;
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range: gpio-range {
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#pinctrl-single,gpio-range-cells = <3>;
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};
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};
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uart0: serial@8b00000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x8b00000 0x1000>;
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@ -190,13 +301,30 @@
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status = "disabled";
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};
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emmc: mmc@9830000 {
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sd0: mmc@9820000 {
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compatible = "snps,dw-mshc";
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reg = <0x9820000 0x10000>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg HISTB_SDIO0_CIU_CLK>,
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<&crg HISTB_SDIO0_BIU_CLK>;
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clock-names = "ciu", "biu";
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resets = <&crg 0x9c 4>;
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reset-names = "reset";
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status = "disabled";
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};
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emmc: mmc@9830000 {
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compatible = "hisilicon,hi3798cv200-dw-mshc";
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reg = <0x9830000 0x10000>;
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg HISTB_MMC_CIU_CLK>,
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<&crg HISTB_MMC_BIU_CLK>;
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clock-names = "ciu", "biu";
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<&crg HISTB_MMC_BIU_CLK>,
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<&crg HISTB_MMC_SAMPLE_CLK>,
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<&crg HISTB_MMC_DRV_CLK>;
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clock-names = "ciu", "biu", "ciu-sample", "ciu-drive";
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resets = <&crg 0xa0 4>;
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reset-names = "reset";
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status = "disabled";
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};
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gpio0: gpio@8b20000 {
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@ -207,6 +335,7 @@
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&pmx0 0 0 8>;
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clocks = <&crg HISTB_APB_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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@ -220,6 +349,13 @@
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <
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&pmx0 0 8 1
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&pmx0 1 9 4
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&pmx0 5 13 1
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&pmx0 6 14 1
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&pmx0 7 15 1
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>;
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clocks = <&crg HISTB_APB_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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@ -233,6 +369,7 @@
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&pmx0 0 16 5 &pmx0 5 21 3>;
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clocks = <&crg HISTB_APB_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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@ -246,6 +383,12 @@
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <
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&pmx0 0 24 4
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&pmx0 4 28 2
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&pmx0 6 86 1
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&pmx0 7 87 1
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>;
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clocks = <&crg HISTB_APB_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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@ -259,6 +402,7 @@
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&pmx0 0 30 4 &pmx0 4 34 3 &pmx0 7 37 1>;
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clocks = <&crg HISTB_APB_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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@ -285,6 +429,7 @@
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&pmx0 0 38 3 &pmx0 0 41 5>;
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clocks = <&crg HISTB_APB_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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@ -298,6 +443,7 @@
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&pmx0 0 46 8>;
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clocks = <&crg HISTB_APB_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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@ -311,6 +457,7 @@
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&pmx0 0 54 8>;
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clocks = <&crg HISTB_APB_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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@ -324,6 +471,7 @@
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&pmx0 0 64 7 &pmx0 71 1>;
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clocks = <&crg HISTB_APB_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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@ -337,6 +485,7 @@
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&pmx0 0 72 6 &pmx0 6 78 1 &pmx0 7 79 1>;
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clocks = <&crg HISTB_APB_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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@ -350,6 +499,7 @@
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&pmx0 0 80 6 &pmx0 6 70 2>;
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clocks = <&crg HISTB_APB_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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@ -363,6 +513,7 @@
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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gpio-ranges = <&pmx0 0 88 8>;
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clocks = <&crg HISTB_APB_CLK>;
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clock-names = "apb_pclk";
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status = "disabled";
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@ -405,5 +556,67 @@
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clocks = <&sysctrl HISTB_IR_CLK>;
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status = "disabled";
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};
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pcie: pcie@9860000 {
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compatible = "hisilicon,hi3798cv200-pcie";
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reg = <0x9860000 0x1000>,
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<0x0 0x2000>,
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<0x2000000 0x01000000>;
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reg-names = "control", "rc-dbi", "config";
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#address-cells = <3>;
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#size-cells = <2>;
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device_type = "pci";
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bus-range = <0 15>;
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num-lanes = <1>;
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ranges = <0x81000000 0x0 0x00000000 0x4f00000 0x0 0x100000
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0x82000000 0x0 0x3000000 0x3000000 0x0 0x01f00000>;
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interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic 0 131 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg HISTB_PCIE_AUX_CLK>,
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<&crg HISTB_PCIE_PIPE_CLK>,
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<&crg HISTB_PCIE_SYS_CLK>,
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<&crg HISTB_PCIE_BUS_CLK>;
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clock-names = "aux", "pipe", "sys", "bus";
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resets = <&crg 0x18c 6>, <&crg 0x18c 5>, <&crg 0x18c 4>;
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reset-names = "soft", "sys", "bus";
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phys = <&combphy1 PHY_TYPE_PCIE>;
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phy-names = "phy";
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status = "disabled";
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};
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ohci: ohci@9880000 {
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compatible = "generic-ohci";
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reg = <0x9880000 0x10000>;
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interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg HISTB_USB2_BUS_CLK>,
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<&crg HISTB_USB2_12M_CLK>,
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<&crg HISTB_USB2_48M_CLK>;
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clock-names = "bus", "clk12", "clk48";
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resets = <&crg 0xb8 12>;
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reset-names = "bus";
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phys = <&usb2_phy1_port0>;
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phy-names = "usb";
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status = "disabled";
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};
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ehci: ehci@9890000 {
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compatible = "generic-ehci";
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reg = <0x9890000 0x10000>;
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interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&crg HISTB_USB2_BUS_CLK>,
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<&crg HISTB_USB2_PHY_CLK>,
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<&crg HISTB_USB2_UTMI_CLK>;
|
||||
clock-names = "bus", "phy", "utmi";
|
||||
resets = <&crg 0xb8 12>,
|
||||
<&crg 0xb8 16>,
|
||||
<&crg 0xb8 13>;
|
||||
reset-names = "bus", "phy", "utmi";
|
||||
phys = <&usb2_phy1_port0>;
|
||||
phy-names = "usb";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
98
arch/arm/dts/poplar-pinctrl.dtsi
Normal file
98
arch/arm/dts/poplar-pinctrl.dtsi
Normal file
@ -0,0 +1,98 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Pinctrl dts file for HiSilicon Poplar board
|
||||
*
|
||||
* Copyright (c) 2016-2018 HiSilicon Technologies Co., Ltd.
|
||||
*/
|
||||
|
||||
#include <dt-bindings/pinctrl/hisi.h>
|
||||
|
||||
/* value, enable bits, disable bits, mask */
|
||||
#define PINCTRL_PULLDOWN(value, enable, disable, mask) \
|
||||
(value << 13) (enable << 13) (disable << 13) (mask << 13)
|
||||
#define PINCTRL_PULLUP(value, enable, disable, mask) \
|
||||
(value << 12) (enable << 12) (disable << 12) (mask << 12)
|
||||
#define PINCTRL_SLEW_RATE(value, mask) (value << 8) (mask << 8)
|
||||
#define PINCTRL_DRV_STRENGTH(value, mask) (value << 4) (mask << 4)
|
||||
|
||||
&pmx0 {
|
||||
emmc_pins_1: emmc-pins-1 {
|
||||
pinctrl-single,pins = <
|
||||
0x000 MUX_M2
|
||||
0x004 MUX_M2
|
||||
0x008 MUX_M2
|
||||
0x00c MUX_M2
|
||||
0x010 MUX_M2
|
||||
0x014 MUX_M2
|
||||
0x018 MUX_M2
|
||||
0x01c MUX_M2
|
||||
0x024 MUX_M2
|
||||
>;
|
||||
pinctrl-single,bias-pulldown = <
|
||||
PINCTRL_PULLDOWN(0, 1, 0, 1)
|
||||
>;
|
||||
pinctrl-single,bias-pullup = <
|
||||
PINCTRL_PULLUP(0, 1, 0, 1)
|
||||
>;
|
||||
pinctrl-single,slew-rate = <
|
||||
PINCTRL_SLEW_RATE(1, 1)
|
||||
>;
|
||||
pinctrl-single,drive-strength = <
|
||||
PINCTRL_DRV_STRENGTH(0xb, 0xf)
|
||||
>;
|
||||
};
|
||||
|
||||
emmc_pins_2: emmc-pins-2 {
|
||||
pinctrl-single,pins = <
|
||||
0x028 MUX_M2
|
||||
>;
|
||||
pinctrl-single,bias-pulldown = <
|
||||
PINCTRL_PULLDOWN(0, 1, 0, 1)
|
||||
>;
|
||||
pinctrl-single,bias-pullup = <
|
||||
PINCTRL_PULLUP(0, 1, 0, 1)
|
||||
>;
|
||||
pinctrl-single,slew-rate = <
|
||||
PINCTRL_SLEW_RATE(1, 1)
|
||||
>;
|
||||
pinctrl-single,drive-strength = <
|
||||
PINCTRL_DRV_STRENGTH(0x9, 0xf)
|
||||
>;
|
||||
};
|
||||
|
||||
emmc_pins_3: emmc-pins-3 {
|
||||
pinctrl-single,pins = <
|
||||
0x02c MUX_M2
|
||||
>;
|
||||
pinctrl-single,bias-pulldown = <
|
||||
PINCTRL_PULLDOWN(0, 1, 0, 1)
|
||||
>;
|
||||
pinctrl-single,bias-pullup = <
|
||||
PINCTRL_PULLUP(0, 1, 0, 1)
|
||||
>;
|
||||
pinctrl-single,slew-rate = <
|
||||
PINCTRL_SLEW_RATE(1, 1)
|
||||
>;
|
||||
pinctrl-single,drive-strength = <
|
||||
PINCTRL_DRV_STRENGTH(3, 3)
|
||||
>;
|
||||
};
|
||||
|
||||
emmc_pins_4: emmc-pins-4 {
|
||||
pinctrl-single,pins = <
|
||||
0x030 MUX_M2
|
||||
>;
|
||||
pinctrl-single,bias-pulldown = <
|
||||
PINCTRL_PULLDOWN(1, 1, 0, 1)
|
||||
>;
|
||||
pinctrl-single,bias-pullup = <
|
||||
PINCTRL_PULLUP(0, 1, 0, 1)
|
||||
>;
|
||||
pinctrl-single,slew-rate = <
|
||||
PINCTRL_SLEW_RATE(1, 1)
|
||||
>;
|
||||
pinctrl-single,drive-strength = <
|
||||
PINCTRL_DRV_STRENGTH(3, 3)
|
||||
>;
|
||||
};
|
||||
};
|
||||
@ -53,7 +53,23 @@
|
||||
#define HISTB_ETH1_MAC_CLK 31
|
||||
#define HISTB_ETH1_MACIF_CLK 32
|
||||
#define HISTB_COMBPHY1_CLK 33
|
||||
|
||||
#define HISTB_USB2_BUS_CLK 34
|
||||
#define HISTB_USB2_PHY_CLK 35
|
||||
#define HISTB_USB2_UTMI_CLK 36
|
||||
#define HISTB_USB2_12M_CLK 37
|
||||
#define HISTB_USB2_48M_CLK 38
|
||||
#define HISTB_USB2_OTG_UTMI_CLK 39
|
||||
#define HISTB_USB2_PHY1_REF_CLK 40
|
||||
#define HISTB_USB2_PHY2_REF_CLK 41
|
||||
#define HISTB_COMBPHY0_CLK 42
|
||||
#define HISTB_USB3_BUS_CLK 43
|
||||
#define HISTB_USB3_UTMI_CLK 44
|
||||
#define HISTB_USB3_PIPE_CLK 45
|
||||
#define HISTB_USB3_SUSPEND_CLK 46
|
||||
#define HISTB_USB3_BUS_CLK1 47
|
||||
#define HISTB_USB3_UTMI_CLK1 48
|
||||
#define HISTB_USB3_PIPE_CLK1 49
|
||||
#define HISTB_USB3_SUSPEND_CLK1 50
|
||||
|
||||
/* clocks provided by mcu CRG */
|
||||
#define HISTB_MCE_CLK 1
|
||||
|
||||
74
include/dt-bindings/pinctrl/hisi.h
Normal file
74
include/dt-bindings/pinctrl/hisi.h
Normal file
@ -0,0 +1,74 @@
|
||||
/*
|
||||
* This header provides constants for hisilicon pinctrl bindings.
|
||||
*
|
||||
* Copyright (c) 2015 Hisilicon Limited.
|
||||
* Copyright (c) 2015 Linaro Limited.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as
|
||||
* published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any
|
||||
* kind, whether express or implied; without even the implied warranty
|
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#ifndef _DT_BINDINGS_PINCTRL_HISI_H
|
||||
#define _DT_BINDINGS_PINCTRL_HISI_H
|
||||
|
||||
/* iomg bit definition */
|
||||
#define MUX_M0 0
|
||||
#define MUX_M1 1
|
||||
#define MUX_M2 2
|
||||
#define MUX_M3 3
|
||||
#define MUX_M4 4
|
||||
#define MUX_M5 5
|
||||
#define MUX_M6 6
|
||||
#define MUX_M7 7
|
||||
|
||||
/* iocg bit definition */
|
||||
#define PULL_MASK (3)
|
||||
#define PULL_DIS (0)
|
||||
#define PULL_UP (1 << 0)
|
||||
#define PULL_DOWN (1 << 1)
|
||||
|
||||
/* drive strength definition */
|
||||
#define DRIVE_MASK (7 << 4)
|
||||
#define DRIVE1_02MA (0 << 4)
|
||||
#define DRIVE1_04MA (1 << 4)
|
||||
#define DRIVE1_08MA (2 << 4)
|
||||
#define DRIVE1_10MA (3 << 4)
|
||||
#define DRIVE2_02MA (0 << 4)
|
||||
#define DRIVE2_04MA (1 << 4)
|
||||
#define DRIVE2_08MA (2 << 4)
|
||||
#define DRIVE2_10MA (3 << 4)
|
||||
#define DRIVE3_04MA (0 << 4)
|
||||
#define DRIVE3_08MA (1 << 4)
|
||||
#define DRIVE3_12MA (2 << 4)
|
||||
#define DRIVE3_16MA (3 << 4)
|
||||
#define DRIVE3_20MA (4 << 4)
|
||||
#define DRIVE3_24MA (5 << 4)
|
||||
#define DRIVE3_32MA (6 << 4)
|
||||
#define DRIVE3_40MA (7 << 4)
|
||||
#define DRIVE4_02MA (0 << 4)
|
||||
#define DRIVE4_04MA (2 << 4)
|
||||
#define DRIVE4_08MA (4 << 4)
|
||||
#define DRIVE4_10MA (6 << 4)
|
||||
|
||||
/* drive strength definition for hi3660 */
|
||||
#define DRIVE6_MASK (15 << 4)
|
||||
#define DRIVE6_04MA (0 << 4)
|
||||
#define DRIVE6_12MA (4 << 4)
|
||||
#define DRIVE6_19MA (8 << 4)
|
||||
#define DRIVE6_27MA (10 << 4)
|
||||
#define DRIVE6_32MA (15 << 4)
|
||||
#define DRIVE7_02MA (0 << 4)
|
||||
#define DRIVE7_04MA (1 << 4)
|
||||
#define DRIVE7_06MA (2 << 4)
|
||||
#define DRIVE7_08MA (3 << 4)
|
||||
#define DRIVE7_10MA (4 << 4)
|
||||
#define DRIVE7_12MA (5 << 4)
|
||||
#define DRIVE7_14MA (6 << 4)
|
||||
#define DRIVE7_16MA (7 << 4)
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user