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board: sam9x60ek: Add NAND flash support

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- EBI Chip Select Register is now in SFR,
- the pins are set to default values,
- timings are matching MT29F4G08BABWP's nand flash requirements.

Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
This commit is contained in:
Tudor Ambarus 2019-09-27 13:09:07 +00:00 committed by Eugen Hristev
parent cd0fcf1965
commit 8ed15e4a3a
2 changed files with 89 additions and 0 deletions
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61
board/atmel/sam9x60ek/sam9x60ek.c
View File

@ -7,8 +7,10 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/at91sam9_smc.h>
#include <asm/arch/at91_common.h>
#include <asm/arch/at91_rstc.h>
#include <asm/arch/at91_sfr.h>
#include <asm/arch/clk.h>
#include <asm/arch/gpio.h>
#include <debug_uart.h>
@ -18,6 +20,62 @@ DECLARE_GLOBAL_DATA_PTR;
void at91_prepare_cpu_var(void);
#ifdef CONFIG_CMD_NAND
static void sam9x60ek_nand_hw_init(void)
{
struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
struct atmel_sfr *sfr = (struct atmel_sfr *)ATMEL_BASE_SFR;
unsigned int csa;
at91_pio3_set_a_periph(AT91_PIO_PORTD, 0, 1); /* NAND OE */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 1, 1); /* NAND WE */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 2, 0); /* NAND ALE */
at91_pio3_set_a_periph(AT91_PIO_PORTD, 3, 0); /* NAND CLE */
/* Enable NandFlash */
at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
/* Configure RDY/BSY */
at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 6, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 7, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 8, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 9, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 10, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 11, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 12, 1);
at91_pio3_set_a_periph(AT91_PIO_PORTD, 13, 1);
at91_periph_clk_enable(ATMEL_ID_PIOD);
/* Enable CS3 */
csa = readl(&sfr->ebicsa);
csa |= AT91_SFR_CCFG_EBI_CSA(3, 1) | AT91_SFR_CCFG_NFD0_ON_D16;
/* Configure IO drive */
csa &= ~AT91_SFR_CCFG_EBI_DRIVE_SAM9X60;
writel(csa, &sfr->ebicsa);
/* Configure SMC CS3 for NAND/SmartMedia */
writel(AT91_SMC_SETUP_NWE(4), &smc->cs[3].setup);
writel(AT91_SMC_PULSE_NWE(10) | AT91_SMC_PULSE_NCS_WR(20) |
AT91_SMC_PULSE_NRD(10) | AT91_SMC_PULSE_NCS_RD(20),
&smc->cs[3].pulse);
writel(AT91_SMC_CYCLE_NWE(20) | AT91_SMC_CYCLE_NRD(20),
&smc->cs[3].cycle);
writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
#ifdef CONFIG_SYS_NAND_DBW_16
AT91_SMC_MODE_DBW_16 |
#else /* CONFIG_SYS_NAND_DBW_8 */
AT91_SMC_MODE_DBW_8 |
#endif
AT91_SMC_MODE_TDF | AT91_SMC_MODE_TDF_CYCLE(15),
&smc->cs[3].mode);
}
#endif
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
@ -48,6 +106,9 @@ int board_init(void)
/* address of boot parameters */
gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
#ifdef CONFIG_CMD_NAND
sam9x60ek_nand_hw_init();
#endif
return 0;
}

28
include/configs/sam9x60ek.h
View File

@ -42,6 +42,26 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_SDRAM_BASE + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
/* NAND flash */
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x40000000
#define CONFIG_SYS_NAND_MASK_ALE BIT(21)
#define CONFIG_SYS_NAND_MASK_CLE BIT(22)
#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PD4
#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PD5
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_MTD_DEVICE
#endif
/* PMECC & PMERRLOC */
#define CONFIG_ATMEL_NAND_HWECC
#define CONFIG_ATMEL_NAND_HW_PMECC
#define CONFIG_PMECC_CAP 8
#define CONFIG_PMECC_SECTOR_SIZE 512
#define CONFIG_SYS_LOAD_ADDR 0x22000000 /* load address */
#ifdef CONFIG_SD_BOOT
@ -50,6 +70,14 @@
"fatload mmc 0:1 0x21000000 at91-sam9x60ek.dtb;" \
"fatload mmc 0:1 0x22000000 zImage;" \
"bootz 0x22000000 - 0x21000000"
#elif defined(CONFIG_NAND_BOOT)
/* bootstrap + u-boot + env + linux in nandflash */
#define CONFIG_ENV_OFFSET_REDUND 0x100000
#define CONFIG_BOOTCOMMAND "nand read " \
"0x22000000 0x200000 0x600000; " \
"nand read 0x21000000 0x180000 0x20000; " \
"bootz 0x22000000 - 0x21000000"
#endif
/*