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Merge with git://www.denx.de/git/u-boot.git

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This commit is contained in:
Stefan Roese 2007-07-04 08:11:37 +02:00
commit 8e990cb076
130 changed files with 2449 additions and 511 deletions
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39
CHANGELOG
View File

@ -1,3 +1,42 @@
commit 2dc64451b4c08ffd619372abfdc2506a2e2363b9
Author: Igor Lisitsin <igor@emcraft.com>
Date: Wed Apr 18 14:55:19 2007 +0400
Adapt log buffer code to support Linux 2.6
A new environment variable, "logversion", selects the log buffer
behaviour. If it is not set or set to a value other than 2, then the
old, Linux 2.4.4, behaviour is selected.
Signed-off-by: Igor Lisitsin <igor@emcraft.com>
--
commit a11e06965ec91270c51853407ff1261d3c740386
Author: Igor Lisitsin <igor@emcraft.com>
Date: Wed Mar 28 19:06:19 2007 +0400
Extend POST support for PPC440
Added memory, CPU, UART, I2C and SPR POST tests for PPC440.
Signed-off-by: Igor Lisitsin <igor@emcraft.com>
--
commit 02032e8f14751a1a751b09240a4f1cf9f8a2077f
Author: Rafal Jaworowski <raj@semihalf.com>
Date: Fri Jun 22 14:58:04 2007 +0200
[ppc] Fix build breakage for all non-4xx PowerPC variants.
- adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros
- minor 4xx cleanup
commit 83b4cfa3d629dff0264366263c5e94d9a50ad80b
Author: Wolfgang Denk <wd@denx.de>
Date: Wed Jun 20 18:14:24 2007 +0200
Coding style cleanup. Refresh CHANGELOG.
commit b3f9ec86e388207fd03dcdf7b145b9ed080bf024
Author: Stefan Roese <sr@denx.de>
Date: Tue Jun 19 17:22:44 2007 +0200

11
MAKEALL
View File

@ -150,6 +150,14 @@ LIST_85xx=" \
TQM8560 \
"
#########################################################################
## MPC86xx Systems
#########################################################################
LIST_86xx=" \
MPC8641HPCN \
"
#########################################################################
## 74xx/7xx Systems
#########################################################################
@ -170,6 +178,7 @@ LIST_ppc="${LIST_5xx} ${LIST_5xxx} \
${LIST_8220} ${LIST_824x} ${LIST_8260} \
${LIST_83xx} \
${LIST_85xx} \
${LIST_86xx} \
${LIST_4xx} \
${LIST_74xx} ${LIST_7xx}"
@ -356,7 +365,7 @@ do
microblaze| \
mips|mips_el| \
nios|nios2| \
ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|4xx|7xx|74xx| \
ppc|5xx|5xxx|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx| \
x86|I486)
for target in `eval echo '$LIST_'${arg}`
do

14
board/amcc/acadia/acadia.c
View File

@ -31,13 +31,13 @@ static void acadia_gpio_init(void)
/*
* GPIO0 setup (select GPIO or alternate function)
*/
out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */
out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */
out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */
out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */
/*
* Ultra (405EZ) was nice enough to add another GPIO controller

4
board/amcc/bamboo/bamboo.c
View File

@ -416,7 +416,7 @@ int testdram(void)
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
@ -457,7 +457,7 @@ int pci_pre_init(struct pci_controller *hose)
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init

8
board/amcc/ebony/ebony.c
View File

@ -207,14 +207,14 @@ long int fixed_sdram(void)
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long strap;
/*--------------------------------------------------------------------------+
* The ebony board is always configured as the host & requires the
* PCI arbiter to be enabled.
* The ebony board is always configured as the host & requires the
* PCI arbiter to be enabled.
*--------------------------------------------------------------------------*/
strap = mfdcr(cpc0_strp1);
if ((strap & 0x00100000) == 0) {
@ -224,7 +224,7 @@ int pci_pre_init(struct pci_controller *hose)
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init

4
board/amcc/katmai/katmai.c
View File

@ -292,7 +292,7 @@ int testdram (void)
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
unsigned long strap;
@ -309,7 +309,7 @@ int pci_pre_init(struct pci_controller * hose )
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init

4
board/amcc/luan/luan.c
View File

@ -161,7 +161,7 @@ int testdram(void)
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI)
int pci_pre_init( struct pci_controller *hose )
{
unsigned long strap;
@ -179,7 +179,7 @@ int pci_pre_init( struct pci_controller *hose )
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
#endif /* defined(CONFIG_PCI) */
/*************************************************************************

4
board/amcc/ocotea/ocotea.c
View File

@ -306,7 +306,7 @@ long int fixed_sdram (void)
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
unsigned long strap;
@ -323,7 +323,7 @@ int pci_pre_init(struct pci_controller * hose )
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init

27
board/amcc/sequoia/sequoia.c
View File

@ -426,23 +426,10 @@ int testdram(void)
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
#if 0
/*--------------------------------------------------------------------------+
* Cactus is always configured as the host & requires the
* PCI arbiter to be enabled ???
*--------------------------------------------------------------------------*/
unsigned long strap;
mfsdr(sdr_sdstp1, strap);
if ((strap & SDR0_SDSTP1_PAE_MASK) == 0) {
printf("PCI: SDR0_STRP1[PAE] not set.\n");
printf("PCI: Configuration aborted.\n");
return 0;
}
#endif
/*-------------------------------------------------------------------------+
| Set priority for all PLB3 devices to 0.
@ -480,7 +467,7 @@ int pci_pre_init(struct pci_controller *hose)
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init
@ -586,3 +573,13 @@ int is_pci_host(struct pci_controller *hose)
return (1);
}
#endif /* defined(CONFIG_PCI) */
#if defined(CONFIG_POST)
/*
* Returns 1 if keys pressed to start the power-on long-running tests
* Called from board_init_f().
*/
int post_hotkeys_pressed(void)
{
return 0; /* No hotkeys supported */
}
#endif /* CONFIG_POST */

4
board/amcc/taishan/taishan.c
View File

@ -236,7 +236,7 @@ int testdram (void)
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
unsigned long strap;
@ -253,7 +253,7 @@ int pci_pre_init(struct pci_controller * hose )
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init

4
board/amcc/yosemite/yosemite.c
View File

@ -385,7 +385,7 @@ int testdram(void)
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
@ -426,7 +426,7 @@ int pci_pre_init(struct pci_controller *hose)
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init

4
board/amcc/yucca/yucca.c
View File

@ -604,7 +604,7 @@ int testdram (void)
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
unsigned long strap;
@ -621,7 +621,7 @@ int pci_pre_init(struct pci_controller * hose )
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init

2
board/bf537-stamp/ether_bf537.c
View File

@ -48,7 +48,7 @@
#define TXBUF_BASE_ADDR 0xFF800000
#define TX_BUF_CNT 1
#define TOUT_LOOP 1000000
#define TOUT_LOOP 1000000
ADI_ETHER_BUFFER *txbuf[TX_BUF_CNT];
ADI_ETHER_BUFFER *rxbuf[PKTBUFSRX];

6
board/bf537-stamp/flash-defines.h
View File

@ -44,9 +44,9 @@
#define ERASE_SECT 6
#define READ 7
#define GET_SECTNUM 8
#define FLASH_START_L 0x0000
#define FLASH_START_H 0x2000
#define FLASH_MAN_ST 2
#define FLASH_START_L 0x0000
#define FLASH_START_H 0x2000
#define FLASH_MAN_ST 2
#define RESET_VAL 0xF0
flash_info_t flash_info[CFG_MAX_FLASH_BANKS];

2
board/bf537-stamp/stm_m25p64.c
View File

@ -9,7 +9,7 @@
/* Application definitions */
#define NUM_SECTORS 128 /* number of sectors */
#define NUM_SECTORS 128 /* number of sectors */
#define SECTOR_SIZE 0x10000
#define NOP_NUM 1000

12
board/bf537-stamp/u-boot.lds.S
View File

@ -33,7 +33,7 @@ SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib);
__DYNAMIC = 0; */
MEMORY
{
ram : ORIGIN = (CFG_MONITOR_BASE), LENGTH = (256 * 1024)
ram : ORIGIN = (CFG_MONITOR_BASE), LENGTH = (256 * 1024)
l1_code : ORIGIN = 0xFFA00000, LENGTH = 0xC000
l1_data : ORIGIN = 0xFF900000, LENGTH = 0x4000
}
@ -47,11 +47,11 @@ SECTIONS
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
@ -68,7 +68,7 @@ SECTIONS
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector before the environment sector. If it throws */
/* the sector before the environment sector. If it throws */
/* an error during compilation remove an object here to get */
/* it linked after the configuration sector. */

10
board/cds/mpc8548cds/mpc8548cds.c
View File

@ -345,23 +345,23 @@ int last_stage_init(void)
/* This is needed to get the RGMII working for the 1.3+
* CDS cards */
if (get_board_version() == 0x13) {
miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
miiphy_write(CONFIG_TSEC1_NAME,
TSEC1_PHY_ADDR, 29, 18);
miiphy_read(CONFIG_MPC85XX_TSEC1_NAME,
miiphy_read(CONFIG_TSEC1_NAME,
TSEC1_PHY_ADDR, 30, &temp);
temp = (temp & 0xf03f);
temp |= 2 << 9; /* 36 ohm */
temp |= 2 << 6; /* 39 ohm */
miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
miiphy_write(CONFIG_TSEC1_NAME,
TSEC1_PHY_ADDR, 30, temp);
miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
miiphy_write(CONFIG_TSEC1_NAME,
TSEC1_PHY_ADDR, 29, 3);
miiphy_write(CONFIG_MPC85XX_TSEC1_NAME,
miiphy_write(CONFIG_TSEC1_NAME,
TSEC1_PHY_ADDR, 30, 0x8000);
}

76
board/esd/cpci405/cpci405.c
View File

@ -23,9 +23,11 @@
#include <common.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <command.h>
#include <malloc.h>
#include <net.h>
#include <pci.h>
DECLARE_GLOBAL_DATA_PTR;
@ -179,11 +181,15 @@ int board_early_init_f (void)
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
mtdcr(uicer, 0x00000000); /* disable all ints */
mtdcr(uiccr, 0x00000000); /* set all to be non-critical*/
#ifdef CONFIG_CPCI405_6U
if (cpci405_version() == 3) {
mtdcr(uicpr, 0xFFFFFF99); /* set int polarities */
} else {
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
}
#else
mtdcr(uicpr, 0xFFFFFF81); /* set int polarities */
#endif
mtdcr(uictr, 0x10000000); /* set int trigger levels */
mtdcr(uicvcr, 0x00000001); /* set vect base=0,INT0 highest priority*/
mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */
@ -227,10 +233,10 @@ int cpci405_version(void)
*/
cntrl0Reg = mfdcr(cntrl0);
mtdcr(cntrl0, cntrl0Reg | 0x03000000);
out32(GPIO0_ODR, in32(GPIO0_ODR) & ~0x00180000);
out32(GPIO0_TCR, in32(GPIO0_TCR) & ~0x00180000);
out_be32((void*)GPIO0_ODR, in_be32((void*)GPIO0_ODR) & ~0x00180000);
out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) & ~0x00180000);
udelay(1000); /* wait some time before reading input */
value = in32(GPIO0_IR) & 0x00180000; /* get config bits */
value = in_be32((void*)GPIO0_IR) & 0x00180000; /* get config bits */
/*
* Restore GPIO settings
@ -245,7 +251,7 @@ int cpci405_version(void)
/* CS2==0 && CS3==1 -> version 2 */
return 2;
case 0x00100000:
/* CS2==1 && CS3==0 -> version 3 */
/* CS2==1 && CS3==0 -> version 3 or 6U board */
return 3;
case 0x00000000:
/* CS2==0 && CS3==0 -> version 4 */
@ -283,7 +289,6 @@ int misc_init_r (void)
* On CPCI-405 version 2 the environment is saved in eeprom!
* FPGA can be gzip compressed (malloc) and booted this late.
*/
if (cpci405_version() >= 2) {
/*
* Setup GPIO pins (CS6+CS7 as GPIO)
@ -354,6 +359,7 @@ int misc_init_r (void)
SET_FPGA(FPGA_PRG | FPGA_CLK | FPGA_DATA);
udelay(1000); /* wait 1ms */
#ifdef CONFIG_CPCI405_6U
if (cpci405_version() == 3) {
volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
volatile unsigned char *leds = (unsigned char *)CFG_LED_ADDR;
@ -375,6 +381,7 @@ int misc_init_r (void)
udelay(100);
*fpga_mode &= ~(CFG_FPGA_MODE_DUART_RESET);
}
#endif
}
else {
puts("\n*** U-Boot Version does not match Board Version!\n");
@ -493,12 +500,6 @@ int checkboard (void)
#endif
putc ('\n');
/*
* Disable sleep mode in LXT971
*/
lxt971_no_sleep();
return 0;
}
@ -511,24 +512,22 @@ long int initdram (int board_type)
mtdcr(memcfga, mem_mb0cf);
val = mfdcr(memcfgd);
#if 0
printf("\nmb0cf=%x\n", val); /* test-only */
printf("strap=%x\n", mfdcr(strap)); /* test-only */
#endif
return (4*1024*1024 << ((val & 0x000e0000) >> 17));
}
/* ------------------------------------------------------------------------- */
int testdram (void)
void reset_phy(void)
{
/* TODO: XXX XXX XXX */
printf ("test: 16 MB - ok\n");
#ifdef CONFIG_LXT971_NO_SLEEP
return (0);
/*
* Disable sleep mode in LXT971
*/
lxt971_no_sleep();
#endif
}
/* ------------------------------------------------------------------------- */
#ifdef CONFIG_CPCI405_VER2
@ -552,6 +551,41 @@ void ide_set_reset(int on)
#endif /* CONFIG_CPCI405_VER2 */
#if defined(CONFIG_PCI)
void cpci405_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
{
unsigned char int_line = 0xff;
/*
* Write pci interrupt line register (cpci405 specific)
*/
switch (PCI_DEV(dev) & 0x03) {
case 0:
int_line = 27 + 2;
break;
case 1:
int_line = 27 + 3;
break;
case 2:
int_line = 27 + 0;
break;
case 3:
int_line = 27 + 1;
break;
}
pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
}
int pci_pre_init(struct pci_controller *hose)
{
hose->fixup_irq = cpci405_pci_fixup_irq;
return 1;
}
#endif /* defined(CONFIG_PCI) */
#ifdef CONFIG_CPCI405AB
#define ONE_WIRE_CLEAR (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \

4
board/lwmon5/lwmon5.c
View File

@ -304,7 +304,7 @@ int testdram(void)
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
@ -345,7 +345,7 @@ int pci_pre_init(struct pci_controller *hose)
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init

4
board/pcs440ep/pcs440ep.c
View File

@ -217,7 +217,7 @@ int testdram(void)
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long addr;
@ -258,7 +258,7 @@ int pci_pre_init(struct pci_controller *hose)
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init

4
board/prodrive/alpr/alpr.c
View File

@ -172,7 +172,7 @@ int testdram (void)
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
unsigned long strap;
@ -192,7 +192,7 @@ int pci_pre_init(struct pci_controller * hose )
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init

4
board/prodrive/p3p440/p3p440.c
View File

@ -176,7 +176,7 @@ int misc_init_r (void)
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller *hose)
{
unsigned long strap;
@ -193,7 +193,7 @@ int pci_pre_init(struct pci_controller *hose)
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init

4
board/sandburst/common/sb_common.c
View File

@ -313,7 +313,7 @@ long int fixed_sdram (void)
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
unsigned long strap;
@ -330,7 +330,7 @@ int pci_pre_init(struct pci_controller * hose )
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init

2
board/smdk2400/lowlevel_init.S
View File

@ -117,7 +117,7 @@
#define TREFMD 0x0 /* CBR(CAS before RAS)/auto refresh */
#define Trp 0x0 /* 2 clk */
#define Trc 0x3 /* 7 clk */
#define Tchr 0x2 /* 3 clk */
#define Tchr 0x2 /* 3 clk */
#define REFCNT 1113 /* period=15.6 us, HCLK=60Mhz, (2048+1-15.6*66) */

4
board/xpedite1k/xpedite1k.c
View File

@ -209,7 +209,7 @@ long int fixed_sdram (void)
* certain pre-initialization actions.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI)
int pci_pre_init(struct pci_controller * hose )
{
unsigned long strap;
@ -227,7 +227,7 @@ int pci_pre_init(struct pci_controller * hose )
#endif
return 1;
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
#endif /* defined(CONFIG_PCI) */
/*************************************************************************
* pci_target_init

4
common/Makefile
View File

@ -38,8 +38,8 @@ COBJS = main.o ACEX1K.o altera.o bedbug.o circbuf.o cmd_autoscript.o \
cmd_mem.o cmd_mii.o cmd_misc.o cmd_mmc.o \
cmd_nand.o cmd_net.o cmd_nvedit.o \
cmd_pci.o cmd_pcmcia.o cmd_portio.o \
cmd_reginfo.o cmd_reiser.o cmd_scsi.o cmd_spi.o cmd_universe.o \
cmd_usb.o cmd_vfd.o \
cmd_reginfo.o cmd_reiser.o cmd_sata.o cmd_scsi.o cmd_spi.o \
cmd_universe.o cmd_usb.o cmd_vfd.o \
command.o console.o cyclon2.o devices.o dlmalloc.o docecc.o \
environment.o env_common.o \
env_nand.o env_dataflash.o env_flash.o env_eeprom.o \

120
common/cmd_log.c
View File

@ -1,5 +1,5 @@
/*
* (C) Copyright 2002
* (C) Copyright 2002-2007
* Detlev Zundel, DENX Software Engineering, dzu@denx.de.
*
* Code used from linux/kernel/printk.c
@ -60,45 +60,40 @@ static char buf[1024];
/* This combination will not print messages with the default loglevel */
static unsigned console_loglevel = 3;
static unsigned default_message_loglevel = 4;
static unsigned char *log_buf = NULL;
static unsigned long *ext_log_size;
static unsigned long *ext_log_start;
static unsigned long *ext_logged_chars;
#define log_size (*ext_log_size)
#define log_start (*ext_log_start)
#define logged_chars (*ext_logged_chars)
static unsigned log_version = 1;
static logbuff_t *log;
/* Forced by code, eh! */
#define LOGBUFF_MAGIC 0xc0de4ced
/* The mapping used here has to be the same as in setup_ext_logbuff ()
in linux/kernel/printk */
void logbuff_init_ptrs (void)
{
unsigned long *ext_tag;
unsigned long post_word;
unsigned long tag, post_word;
char *s;
log_buf = (unsigned char *)(gd->bd->bi_memsize-LOGBUFF_LEN);
ext_tag = (unsigned long *)(log_buf)-4;
ext_log_start = (unsigned long *)(log_buf)-3;
ext_log_size = (unsigned long *)(log_buf)-2;
ext_logged_chars = (unsigned long *)(log_buf)-1;
log = (logbuff_t *)(gd->bd->bi_memsize-LOGBUFF_LEN) - 1;
/* Set up log version */
if ((s = getenv ("logversion")) != NULL)
log_version = (int)simple_strtoul (s, NULL, 10);
if (log_version == 2)
tag = log->v2.tag;
else
tag = log->v1.tag;
post_word = post_word_load();
#ifdef CONFIG_POST
/* The post routines have setup the word so we can simply test it */
if (post_word_load () & POST_COLDBOOT) {
logged_chars = log_size = log_start = 0;
*ext_tag = LOGBUFF_MAGIC;
}
if (tag != LOGBUFF_MAGIC || (post_word & POST_COLDBOOT)) {
logbuff_reset ();
}
#else
/* No post routines, so we do our own checking */
if (post_word != LOGBUFF_MAGIC) {
logged_chars = log_size = log_start = 0;
if (tag != LOGBUFF_MAGIC || post_word != LOGBUFF_MAGIC) {
logbuff_reset ();
post_word_store (LOGBUFF_MAGIC);
*ext_tag = LOGBUFF_MAGIC;
}
}
#endif
if (log_version == 2 && (long)log->v2.start > (long)log->v2.con)
log->v2.start = log->v2.con;
/* Initialize default loglevel if present */
if ((s = getenv ("loglevel")) != NULL)
console_loglevel = (int)simple_strtoul (s, NULL, 10);
@ -106,6 +101,15 @@ void logbuff_init_ptrs (void)
gd->post_log_word |= LOGBUFF_INITIALIZED;
}
void logbuff_reset (void)
{
memset (log, 0, sizeof (logbuff_t));
if (log_version == 2)
log->v2.tag = LOGBUFF_MAGIC;
else
log->v1.tag = LOGBUFF_MAGIC;
}
int drv_logbuff_init (void)
{
device_t logdev;
@ -162,7 +166,7 @@ void logbuff_log(char *msg)
int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
char *s;
unsigned long i;
unsigned long i, start, size;
if (strcmp(argv[1],"append") == 0) {
/* Log concatenation of all arguments separated by spaces */
@ -177,21 +181,34 @@ int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
case 2:
if (strcmp(argv[1],"show") == 0) {
for (i=0; i < (log_size&LOGBUFF_MASK); i++) {
s = (char *)log_buf+((log_start+i)&LOGBUFF_MASK);
if (log_version == 2) {
start = log->v2.start;
size = log->v2.end - log->v2.start;
}
else {
start = log->v1.start;
size = log->v1.size;
}
for (i=0; i < (size&LOGBUFF_MASK); i++) {
s = (char *)log->buf+((start+i)&LOGBUFF_MASK);
putc (*s);
}
return 0;
} else if (strcmp(argv[1],"reset") == 0) {
log_start = 0;
log_size = 0;
logged_chars = 0;
logbuff_reset ();
return 0;
} else if (strcmp(argv[1],"info") == 0) {
printf ("Logbuffer at %08lx\n", (unsigned long)log_buf);
printf ("log_start = %08lx\n", log_start);
printf ("log_size = %08lx\n", log_size);
printf ("logged_chars = %08lx\n", logged_chars);
printf ("Logbuffer at %08lx\n", (unsigned long)log->buf);
if (log_version == 2) {
printf ("log_start = %08lx\n", log->v2.start);
printf ("log_end = %08lx\n", log->v2.end);
printf ("logged_chars = %08lx\n", log->v2.chars);
}
else {
printf ("log_start = %08lx\n", log->v1.start);
printf ("log_size = %08lx\n", log->v1.size);
printf ("logged_chars = %08lx\n", log->v1.chars);
}
return 0;
}
printf ("Usage:\n%s\n", cmdtp->usage);
@ -202,7 +219,7 @@ int do_log (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
return 1;
}
}
#if defined(CONFIG_LOGBUFFER)
U_BOOT_CMD(
log, 255, 1, do_log,
"log - manipulate logbuffer\n",
@ -211,7 +228,7 @@ U_BOOT_CMD(
"log show - show contents\n"
"log append <msg> - append <msg> to the logbuffer\n"
);
#endif /* CONFIG_LOGBUFFER */
static int logbuff_printk(const char *line)
{
int i;
@ -241,13 +258,22 @@ static int logbuff_printk(const char *line)
}
line_feed = 0;
for (; p < buf_end; p++) {
log_buf[(log_start+log_size) & LOGBUFF_MASK] = *p;
if (log_size < LOGBUFF_LEN)
log_size++;
else
log_start++;
logged_chars++;
if (log_version == 2) {
log->buf[log->v2.end & LOGBUFF_MASK] = *p;
log->v2.end++;
if (log->v2.end - log->v2.start > LOGBUFF_LEN)
log->v2.start++;
log->v2.chars++;
}
else {
log->buf[(log->v1.start + log->v1.size) &
LOGBUFF_MASK] = *p;
if (log->v1.size < LOGBUFF_LEN)
log->v1.size++;
else
log->v1.start++;
log->v1.chars++;
}
if (*p == '\n') {
line_feed = 1;
break;

712
common/cmd_sata.c Normal file
View File

@ -0,0 +1,712 @@
/*
* Copyright (C) Procsys. All rights reserved.
* Author: Mushtaq Khan <mushtaq_k@procsys.com>
* <mushtaqk_921@yahoo.co.in>
*
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* with the reference to libata in kernel 2.4.32
*
*/
/*
* File contains SATA read-write and other utility functions.
*/
#include <common.h>
#include <asm/io.h>
#include <pci.h>
#include <command.h>
#include <config.h>
#include <ide.h>
#include <ata.h>
#ifdef CFG_SATA_SUPPORTED
/*For debug prints set macro DEBUG_SATA to 1 */
#define DEBUG_SATA 0
/*Macro for SATA library specific declarations */
#define SATA_DECL
#include <sata.h>
#undef SATA_DECL
static u8 __inline__
sata_inb (unsigned long ioaddr)
{
return inb (ioaddr);
}
static void __inline__
sata_outb (unsigned char val, unsigned long ioaddr)
{
outb (val, ioaddr);
}
static void
output_data (struct sata_ioports *ioaddr, ulong * sect_buf, int words)
{
outsw (ioaddr->data_addr, sect_buf, words << 1);
}
static int
input_data (struct sata_ioports *ioaddr, ulong * sect_buf, int words)
{
insw (ioaddr->data_addr, sect_buf, words << 1);
return 0;
}
static void
sata_cpy (unsigned char *dst, unsigned char *src, unsigned int len)
{
unsigned char *end, *last;
last = dst;
end = src + len - 1;
/* reserve space for '\0' */
if (len < 2)
goto OUT;
/* skip leading white space */
while ((*src) && (src < end) && (*src == ' '))
++src;
/* copy string, omitting trailing white space */
while ((*src) && (src < end)) {
*dst++ = *src;
if (*src++ != ' ')
last = dst;
}
OUT:
*last = '\0';
}
int
sata_bus_softreset (int num)
{
u8 dev = 0, status = 0, i;
port[num].dev_mask = 0;
for (i = 0; i < CFG_SATA_DEVS_PER_BUS; i++) {
if (!(sata_devchk (&port[num].ioaddr, i))) {
PRINTF ("dev_chk failed for dev#%d\n", i);
} else {
port[num].dev_mask |= (1 << i);
PRINTF ("dev_chk passed for dev#%d\n", i);
}
}
if (!(port[num].dev_mask)) {
printf ("no devices on port%d\n", num);
return 1;
}
dev_select (&port[num].ioaddr, dev);
port[num].ctl_reg = 0x08; /*Default value of control reg */
sata_outb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
udelay (10);
sata_outb (port[num].ctl_reg | ATA_SRST, port[num].ioaddr.ctl_addr);
udelay (10);
sata_outb (port[num].ctl_reg, port[num].ioaddr.ctl_addr);
/* spec mandates ">= 2ms" before checking status.
* We wait 150ms, because that was the magic delay used for
* ATAPI devices in Hale Landis's ATADRVR, for the period of time
* between when the ATA command register is written, and then
* status is checked. Because waiting for "a while" before
* checking status is fine, post SRST, we perform this magic
* delay here as well.
*/
msleep (150);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 300);
while ((status & ATA_BUSY)) {
msleep (100);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 3);
}
if (status & ATA_BUSY)
printf ("ata%u is slow to respond,plz be patient\n", port);
while ((status & ATA_BUSY)) {
msleep (100);
status = sata_chk_status (&port[num].ioaddr);
}
if (status & ATA_BUSY) {
printf ("ata%u failed to respond : ", port);
printf ("bus reset failed\n");
return 1;
}
return 0;
}
void
sata_identify (int num, int dev)
{
u8 cmd = 0, status = 0, devno = num * CFG_SATA_DEVS_PER_BUS + dev;
u16 iobuf[ATA_SECT_SIZE];
u64 n_sectors = 0;
u8 mask = 0;
memset (iobuf, 0, sizeof (iobuf));
hd_driveid_t *iop = (hd_driveid_t *) iobuf;
if (dev == 0)
mask = 0x01;
else
mask = 0x02;
if (!(port[num].dev_mask & mask)) {
printf ("dev%d is not present on port#%d\n", dev, num);
return;
}
printf ("port=%d dev=%d\n", num, dev);
dev_select (&port[num].ioaddr, dev);
status = 0;
cmd = ATA_CMD_IDENT; /*Device Identify Command */
sata_outb (cmd, port[num].ioaddr.command_addr);
sata_inb (port[num].ioaddr.altstatus_addr);
udelay (10);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 1000);
if (status & ATA_ERR) {
printf ("\ndevice not responding\n");
port[num].dev_mask &= ~mask;
return;
}
input_data (&port[num].ioaddr, (ulong *) iobuf, ATA_SECTORWORDS);
PRINTF ("\nata%u: dev %u cfg 49:%04x 82:%04x 83:%04x 84:%04x85:%04x"
"86:%04x" "87:%04x 88:%04x\n", num, dev, iobuf[49],
iobuf[82], iobuf[83], iobuf[84], iobuf[85], iobuf[86],
iobuf[87], iobuf[88]);
/* we require LBA and DMA support (bits 8 & 9 of word 49) */
if (!ata_id_has_dma (iobuf) || !ata_id_has_lba (iobuf)) {
PRINTF ("ata%u: no dma/lba\n", num);
}
ata_dump_id (iobuf);
if (ata_id_has_lba48 (iobuf)) {
n_sectors = ata_id_u64 (iobuf, 100);
} else {
n_sectors = ata_id_u32 (iobuf, 60);
}
PRINTF ("no. of sectors %u\n", ata_id_u64 (iobuf, 100));
PRINTF ("no. of sectors %u\n", ata_id_u32 (iobuf, 60));
if (n_sectors == 0) {
port[num].dev_mask &= ~mask;
return;
}
sata_cpy (sata_dev_desc[devno].revision, iop->fw_rev,
sizeof (sata_dev_desc[devno].revision));
sata_cpy (sata_dev_desc[devno].vendor, iop->model,
sizeof (sata_dev_desc[devno].vendor));
sata_cpy (sata_dev_desc[devno].product, iop->serial_no,
sizeof (sata_dev_desc[devno].product));
strswab (sata_dev_desc[devno].revision);
strswab (sata_dev_desc[devno].vendor);
if ((iop->config & 0x0080) == 0x0080) {
sata_dev_desc[devno].removable = 1;
} else {
sata_dev_desc[devno].removable = 0;
}
sata_dev_desc[devno].lba = iop->lba_capacity;
PRINTF ("lba=0x%x", sata_dev_desc[devno].lba);
#ifdef CONFIG_LBA48
if (iop->command_set_2 & 0x0400) {
sata_dev_desc[devno].lba48 = 1;
lba = (unsigned long long) iop->lba48_capacity[0] |
((unsigned long long) iop->lba48_capacity[1] << 16) |
((unsigned long long) iop->lba48_capacity[2] << 32) |
((unsigned long long) iop->lba48_capacity[3] << 48);
} else {
sata_dev_desc[devno].lba48 = 0;
}
#endif
/* assuming HD */
sata_dev_desc[devno].type = DEV_TYPE_HARDDISK;
sata_dev_desc[devno].blksz = ATA_BLOCKSIZE;
sata_dev_desc[devno].lun = 0; /* just to fill something in... */
}
void
set_Feature_cmd (int num, int dev)
{
u8 mask = 0x00, status = 0;
if (dev == 0)
mask = 0x01;
else
mask = 0x02;
if (!(port[num].dev_mask & mask)) {
PRINTF ("dev%d is not present on port#%d\n", dev, num);
return;
}
dev_select (&port[num].ioaddr, dev);
sata_outb (SETFEATURES_XFER, port[num].ioaddr.feature_addr);
sata_outb (XFER_PIO_4, port[num].ioaddr.nsect_addr);
sata_outb (0, port[num].ioaddr.lbal_addr);
sata_outb (0, port[num].ioaddr.lbam_addr);
sata_outb (0, port[num].ioaddr.lbah_addr);
sata_outb (ATA_DEVICE_OBS, port[num].ioaddr.device_addr);
sata_outb (ATA_CMD_SETF, port[num].ioaddr.command_addr);
udelay (50);
msleep (150);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 5000);
if ((status & (ATA_STAT_BUSY | ATA_STAT_ERR))) {
printf ("Error : status 0x%02x\n", status);
port[num].dev_mask &= ~mask;
}
}
void
sata_port (struct sata_ioports *ioport)
{
ioport->data_addr = ioport->cmd_addr + ATA_REG_DATA;
ioport->error_addr = ioport->cmd_addr + ATA_REG_ERR;
ioport->feature_addr = ioport->cmd_addr + ATA_REG_FEATURE;
ioport->nsect_addr = ioport->cmd_addr + ATA_REG_NSECT;
ioport->lbal_addr = ioport->cmd_addr + ATA_REG_LBAL;
ioport->lbam_addr = ioport->cmd_addr + ATA_REG_LBAM;
ioport->lbah_addr = ioport->cmd_addr + ATA_REG_LBAH;
ioport->device_addr = ioport->cmd_addr + ATA_REG_DEVICE;
ioport->status_addr = ioport->cmd_addr + ATA_REG_STATUS;
ioport->command_addr = ioport->cmd_addr + ATA_REG_CMD;
}
int
sata_devchk (struct sata_ioports *ioaddr, int dev)
{
u8 nsect, lbal;
dev_select (ioaddr, dev);
sata_outb (0x55, ioaddr->nsect_addr);
sata_outb (0xaa, ioaddr->lbal_addr);
sata_outb (0xaa, ioaddr->nsect_addr);
sata_outb (0x55, ioaddr->lbal_addr);
sata_outb (0x55, ioaddr->nsect_addr);
sata_outb (0xaa, ioaddr->lbal_addr);
nsect = sata_inb (ioaddr->nsect_addr);
lbal = sata_inb (ioaddr->lbal_addr);
if ((nsect == 0x55) && (lbal == 0xaa))
return 1; /* we found a device */
else
return 0; /* nothing found */
}
void
dev_select (struct sata_ioports *ioaddr, int dev)
{
u8 tmp = 0;
if (dev == 0)
tmp = ATA_DEVICE_OBS;
else
tmp = ATA_DEVICE_OBS | ATA_DEV1;
sata_outb (tmp, ioaddr->device_addr);
sata_inb (ioaddr->altstatus_addr);
udelay (5);
}
u8
sata_busy_wait (struct sata_ioports *ioaddr, int bits, unsigned int max)
{
u8 status;
do {
udelay (1000);
status = sata_chk_status (ioaddr);
max--;
} while ((status & bits) && (max > 0));
return status;
}
u8
sata_chk_status (struct sata_ioports * ioaddr)
{
return sata_inb (ioaddr->status_addr);
}
void
msleep (int count)
{
int i;
for (i = 0; i < count; i++)
udelay (1000);
}
ulong
sata_read (int device, ulong blknr,lbaint_t blkcnt, void * buff)
{
ulong n = 0, *buffer = (ulong *)buff;
u8 dev = 0, num = 0, mask = 0, status = 0;
#ifdef CONFIG_LBA48
unsigned char lba48 = 0;
if (blknr & 0x0000fffff0000000) {
if (!sata_dev_desc[devno].lba48) {
printf ("Drive doesn't support 48-bit addressing\n");
return 0;
}
/* more than 28 bits used, use 48bit mode */
lba48 = 1;
}
#endif
/*Port Number */
num = device / CFG_SATA_DEVS_PER_BUS;
/*dev on the port */
if (device >= CFG_SATA_DEVS_PER_BUS)
dev = device - CFG_SATA_DEVS_PER_BUS;
else
dev = device;
if (dev == 0)
mask = 0x01;
else
mask = 0x02;
if (!(port[num].dev_mask & mask)) {
printf ("dev%d is not present on port#%d\n", dev, num);
return 0;
}
/* Select device */
dev_select (&port[num].ioaddr, dev);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
if (status & ATA_BUSY) {
printf ("ata%u failed to respond\n", port[num].port_no);
return n;
}
while (blkcnt-- > 0) {
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
if (status & ATA_BUSY) {
printf ("ata%u failed to respond\n", 0);
return n;
}
#ifdef CONFIG_LBA48
if (lba48) {
/* write high bits */
sata_outb (0, port[num].ioaddr.nsect_addr);
sata_outb ((blknr >> 24) & 0xFF,
port[num].ioaddr.lbal_addr);
sata_outb ((blknr >> 32) & 0xFF,
port[num].ioaddr.lbam_addr);
sata_outb ((blknr >> 40) & 0xFF,
port[num].ioaddr.lbah_addr);
}
#endif
sata_outb (1, port[num].ioaddr.nsect_addr);
sata_outb (((blknr) >> 0) & 0xFF,
port[num].ioaddr.lbal_addr);
sata_outb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
sata_outb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
#ifdef CONFIG_LBA48
if (lba48) {
sata_outb (ATA_LBA, port[num].ioaddr.device_addr);
sata_outb (ATA_CMD_READ_EXT,
port[num].ioaddr.command_addr);
} else
#endif
{
sata_outb (ATA_LBA | ((blknr >> 24) & 0xF),
port[num].ioaddr.device_addr);
sata_outb (ATA_CMD_READ,
port[num].ioaddr.command_addr);
}
msleep (50);
/*may take up to 4 sec */
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000);
if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
!= ATA_STAT_DRQ) {
u8 err = 0;
printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
device, (ulong) blknr, status);
err = sata_inb (port[num].ioaddr.error_addr);
printf ("Error reg = 0x%x\n", err);
return (n);
}
input_data (&port[num].ioaddr, buffer, ATA_SECTORWORDS);
sata_inb (port[num].ioaddr.altstatus_addr);
udelay (50);
++n;
++blknr;
buffer += ATA_SECTORWORDS;
}
return n;
}
ulong
sata_write (int device, ulong blknr,lbaint_t blkcnt, void * buff)
{
ulong n = 0, *buffer = (ulong *)buff;
unsigned char status = 0, num = 0, dev = 0, mask = 0;
#ifdef CONFIG_LBA48
unsigned char lba48 = 0;
if (blknr & 0x0000fffff0000000) {
if (!sata_dev_desc[devno].lba48) {
printf ("Drive doesn't support 48-bit addressing\n");
return 0;
}
/* more than 28 bits used, use 48bit mode */
lba48 = 1;
}
#endif
/*Port Number */
num = device / CFG_SATA_DEVS_PER_BUS;
/*dev on the Port */
if (device >= CFG_SATA_DEVS_PER_BUS)
dev = device - CFG_SATA_DEVS_PER_BUS;
else
dev = device;
if (dev == 0)
mask = 0x01;
else
mask = 0x02;
/* Select device */
dev_select (&port[num].ioaddr, dev);
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
if (status & ATA_BUSY) {
printf ("ata%u failed to respond\n", port[num].port_no);
return n;
}
while (blkcnt-- > 0) {
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 500);
if (status & ATA_BUSY) {
printf ("ata%u failed to respond\n",
port[num].port_no);
return n;
}
#ifdef CONFIG_LBA48
if (lba48) {
/* write high bits */
sata_outb (0, port[num].ioaddr.nsect_addr);
sata_outb ((blknr >> 24) & 0xFF,
port[num].ioaddr.lbal_addr);
sata_outb ((blknr >> 32) & 0xFF,
port[num].ioaddr.lbam_addr);
sata_outb ((blknr >> 40) & 0xFF,
port[num].ioaddr.lbah_addr);
}
#endif
sata_outb (1, port[num].ioaddr.nsect_addr);
sata_outb ((blknr >> 0) & 0xFF, port[num].ioaddr.lbal_addr);
sata_outb ((blknr >> 8) & 0xFF, port[num].ioaddr.lbam_addr);
sata_outb ((blknr >> 16) & 0xFF, port[num].ioaddr.lbah_addr);
#ifdef CONFIG_LBA48
if (lba48) {
sata_outb (ATA_LBA, port[num].ioaddr.device_addr);
sata_outb (ATA_CMD_WRITE_EXT,
port[num].ioaddr.command_addr);
} else
#endif
{
sata_outb (ATA_LBA | ((blknr >> 24) & 0xF),
port[num].ioaddr.device_addr);
sata_outb (ATA_CMD_WRITE,
port[num].ioaddr.command_addr);
}
msleep (50);
/*may take up to 4 sec */
status = sata_busy_wait (&port[num].ioaddr, ATA_BUSY, 4000);
if ((status & (ATA_STAT_DRQ | ATA_STAT_BUSY | ATA_STAT_ERR))
!= ATA_STAT_DRQ) {
printf ("Error no DRQ dev %d blk %ld: sts 0x%02x\n",
device, (ulong) blknr, status);
return (n);
}
output_data (&port[num].ioaddr, buffer, ATA_SECTORWORDS);
sata_inb (port[num].ioaddr.altstatus_addr);
udelay (50);
++n;
++blknr;
buffer += ATA_SECTORWORDS;
}
return n;
}
block_dev_desc_t *sata_get_dev (int dev);
block_dev_desc_t *
sata_get_dev (int dev)
{
return ((block_dev_desc_t *) & sata_dev_desc[dev]);
}
int
do_sata (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
{
switch (argc) {
case 0:
case 1:
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
case 2:
if (strncmp (argv[1], "init", 4) == 0) {
int rcode = 0;
rcode = init_sata ();
if (rcode)
printf ("Sata initialization Failed\n");
return rcode;
} else if (strncmp (argv[1], "inf", 3) == 0) {
int i;
putc ('\n');
for (i = 0; i < CFG_SATA_MAXDEVICES; ++i) {
/*List only known devices */
if (sata_dev_desc[i].type ==
DEV_TYPE_UNKNOWN)
continue;
printf ("sata dev %d: ", i);
dev_print (&sata_dev_desc[i]);
}
return 0;
}
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
case 3:
if (strcmp (argv[1], "dev") == 0) {
int dev = (int) simple_strtoul (argv[2], NULL, 10);
if (dev >= CFG_SATA_MAXDEVICES) {
printf ("\nSata dev %d not available\n",
dev);
return 1;
}
printf ("\nSATA dev %d: ", dev);
dev_print (&sata_dev_desc[dev]);
if (sata_dev_desc[dev].type == DEV_TYPE_UNKNOWN)
return 1;
curr_dev = dev;
return 0;
} else if (strcmp (argv[1], "part") == 0) {
int dev = (int) simple_strtoul (argv[2], NULL, 10);
if (dev >= CFG_SATA_MAXDEVICES) {
printf ("\nSata dev %d not available\n",
dev);
return 1;
}
PRINTF ("\nSATA dev %d: ", dev);
if (sata_dev_desc[dev].part_type !=
PART_TYPE_UNKNOWN) {
print_part (&sata_dev_desc[dev]);
} else {
printf ("\nSata dev %d partition type "
"unknown\n", dev);
return 1;
}
return 0;
}
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
default:
if (argc < 5) {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
if (strcmp (argv[1], "read") == 0) {
ulong addr = simple_strtoul (argv[2], NULL, 16);
ulong cnt = simple_strtoul (argv[4], NULL, 16);
ulong n;
lbaint_t blk = simple_strtoul (argv[3], NULL, 16);
memset ((int *) addr, 0, cnt * 512);
printf ("\nSATA read: dev %d blk # %ld,"
"count %ld ... ", curr_dev, blk, cnt);
n = sata_read (curr_dev, blk, cnt, (ulong *) addr);
/* flush cache after read */
flush_cache (addr, cnt * 512);
printf ("%ld blocks read: %s\n", n,
(n == cnt) ? "OK" : "ERR");
if (n == cnt)
return 1;
else
return 0;
} else if (strcmp (argv[1], "write") == 0) {
ulong addr = simple_strtoul (argv[2], NULL, 16);
ulong cnt = simple_strtoul (argv[4], NULL, 16);
ulong n;
lbaint_t blk = simple_strtoul (argv[3], NULL, 16);
printf ("\nSata write: dev %d blk # %ld,"
"count %ld ... ", curr_dev, blk, cnt);
n = sata_write (curr_dev, blk, cnt, (ulong *) addr);
printf ("%ld blocks written: %s\n", n,
(n == cnt) ? "OK" : "ERR");
if (n == cnt)
return 1;
else
return 0;
} else {
printf ("Usage:\n%s\n", cmdtp->usage);
return 1;
}
} /*End OF SWITCH */
}
U_BOOT_CMD (sata, 5, 1, do_sata,
"sata init\n"
"sata info\n"
"sata part device\n"
"sata dev device\n"
"sata read addr blk# cnt\n"
"sata write addr blk# cnt\n", "cmd for init,rw and dev-info\n");
#endif

12
common/main.c
View File

@ -113,7 +113,7 @@ static __inline__ int abortboot(int bootdelay)
u_int i;
# ifdef CONFIG_AUTOBOOT_PROMPT
printf (CONFIG_AUTOBOOT_PROMPT, bootdelay);
printf(CONFIG_AUTOBOOT_PROMPT, bootdelay);
# endif
# ifdef CONFIG_AUTOBOOT_DELAY_STR
@ -187,7 +187,7 @@ static __inline__ int abortboot(int bootdelay)
}
# if DEBUG_BOOTKEYS
if (!abort)
puts ("key timeout\n");
puts("key timeout\n");
# endif
#ifdef CONFIG_SILENT_CONSOLE
@ -244,13 +244,13 @@ static __inline__ int abortboot(int bootdelay)
# endif
break;
}
udelay (10000);
udelay(10000);
}
printf ("\b\b\b%2d ", bootdelay);
printf("\b\b\b%2d ", bootdelay);
}
putc ('\n');
putc('\n');
#ifdef CONFIG_SILENT_CONSOLE
if (abort)
@ -962,7 +962,7 @@ int readline (const char *const prompt)
n = 0;
continue;
case 0x17: /* ^W - erase word */
case 0x17: /* ^W - erase word */
p=delete_char(console_buffer, p, &col, &n, plen);
while ((n > 0) && (*p != ' ')) {
p=delete_char(console_buffer, p, &col, &n, plen);

4
cpu/74xx_7xx/start.S
View File

@ -125,7 +125,7 @@ _start_of_vectors:
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
@ -143,7 +143,7 @@ Alignment:
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */

2
cpu/i386/start.S
View File

@ -149,7 +149,7 @@ data_ok:
.progress3:
/* clear bss section in ram, size must be 4-byte aligned */
movl $_i386boot_bss_start, %eax /* BSS start */
movl $_i386boot_bss_start, %edi /* MK_CHG BSS start */
movl $_i386boot_bss_size, %ecx /* BSS size */
movl %ecx, %eax
andl $3, %eax

6
cpu/mpc5xx/start.S
View File

@ -155,7 +155,7 @@ in_flash:
/* Initialize some SPRs that are hard to access from C */
/*----------------------------------------------------------------------*/
lis r3, CFG_IMMR@h /* Pass IMMR as arg1 to C routine */
lis r3, CFG_IMMR@h /* Pass IMMR as arg1 to C routine */
lis r2, CFG_INIT_SP_ADDR@h
ori r1, r2, CFG_INIT_SP_ADDR@l /* Set up the stack in internal SRAM */
/* Note: R0 is still 0 here */
@ -210,7 +210,7 @@ _start_of_vectors:
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
@ -228,7 +228,7 @@ Alignment:
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */

4
cpu/mpc5xxx/start.S
View File

@ -208,7 +208,7 @@ _start_of_vectors:
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
@ -227,7 +227,7 @@ Alignment:
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */

4
cpu/mpc8220/start.S
View File

@ -169,7 +169,7 @@ _start_of_vectors:
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
@ -188,7 +188,7 @@ Alignment:
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */

4
cpu/mpc824x/start.S
View File

@ -220,7 +220,7 @@ _start_of_vectors:
/* Alignment exception. */
. = EXC_OFF_ALIGN
Alignment:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
@ -238,7 +238,7 @@ Alignment:
/* Program check exception */
. = EXC_OFF_PROGRAM
ProgramCheck:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */

8
cpu/mpc8260/start.S
View File

@ -279,7 +279,7 @@ _start_of_vectors:
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
@ -298,7 +298,7 @@ Alignment:
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */
@ -676,13 +676,13 @@ init_debug:
bdnz 1b
/* Load the Instruction Address Breakpoint Register (IABR). */
/* */
/* */
/* The address to load is stored in the first word of dual port */
/* ram and should be preserved while the power is on, so you */
/* can plug addresses into that location then reset the cpu and */
/* this code will load that address into the IABR after the */
/* reset. */
/* */
/* */
/* When the program counter matches the contents of the IABR, */
/* an exception is generated (before the instruction at that */
/* location completes). The vector for this exception is 0x1300 */

8
cpu/mpc83xx/cpu.c
View File

@ -415,7 +415,7 @@ static const struct {
"clock-frequency",
fdt_set_busfreq
},
#ifdef CONFIG_MPC83XX_TSEC1
#ifdef CONFIG_TSEC1
{ "/" OF_SOC "/ethernet@24000,
"mac-address",
fdt_set_eth0
@ -425,7 +425,7 @@ static const struct {
fdt_set_eth0
},
#endif
#ifdef CONFIG_MPC83XX_TSEC2
#ifdef CONFIG_TSEC2
{ "/" OF_SOC "/ethernet@25000,
"mac-address",
fdt_set_eth1
@ -525,7 +525,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
if (p != NULL)
*p = cpu_to_be32(clock);
#ifdef CONFIG_MPC83XX_TSEC1
#ifdef CONFIG_TSEC1
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enetaddr, 6);
@ -535,7 +535,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
memcpy(p, bd->bi_enetaddr, 6);
#endif
#ifdef CONFIG_MPC83XX_TSEC2
#ifdef CONFIG_TSEC2
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enet1addr, 6);

4
cpu/mpc83xx/start.S
View File

@ -263,7 +263,7 @@ _start_of_vectors:
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
@ -282,7 +282,7 @@ Alignment:
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */

2
cpu/mpc85xx/cpu.c
View File

@ -280,7 +280,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
if (p != NULL)
*p = cpu_to_be32(clock);
#if defined(CONFIG_MPC85XX_TSEC1)
#if defined(CONFIG_TSEC1)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
if (p)
memcpy(p, bd->bi_enetaddr, 6);

4
cpu/mpc85xx/start.S
View File

@ -457,7 +457,7 @@ _start_of_vectors:
/* Alignment exception. */
. = 0x0600
Alignment:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
@ -475,7 +475,7 @@ Alignment:
/* Program check exception */
. = 0x0700
ProgramCheck:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */

8
cpu/mpc86xx/cpu.c
View File

@ -278,7 +278,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
if (p != NULL)
*p = cpu_to_be32(clock);
#if defined(CONFIG_MPC86XX_TSEC1)
#if defined(CONFIG_TSEC1)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@24000/mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enetaddr, 6);
@ -287,7 +287,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
memcpy(p, bd->bi_enetaddr, 6);
#endif
#if defined(CONFIG_MPC86XX_TSEC2)
#if defined(CONFIG_TSEC2)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@25000/mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enet1addr, 6);
@ -296,7 +296,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
memcpy(p, bd->bi_enet1addr, 6);
#endif
#if defined(CONFIG_MPC86XX_TSEC3)
#if defined(CONFIG_TSEC3)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@26000/mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enet2addr, 6);
@ -305,7 +305,7 @@ ft_cpu_setup(void *blob, bd_t *bd)
memcpy(p, bd->bi_enet2addr, 6);
#endif
#if defined(CONFIG_MPC86XX_TSEC4)
#if defined(CONFIG_TSEC4)
p = ft_get_prop(blob, "/" OF_SOC "/ethernet@27000/mac-address", &len);
if (p != NULL)
memcpy(p, bd->bi_enet3addr, 6);

4
cpu/mpc86xx/start.S
View File

@ -116,7 +116,7 @@ _start_of_vectors:
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
@ -134,7 +134,7 @@ Alignment:
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */

4
cpu/mpc8xx/start.S
View File

@ -224,7 +224,7 @@ _start_of_vectors:
/* Alignment exception. */
. = 0x600
Alignment:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
mfspr r4,DAR
stw r4,_DAR(r21)
mfspr r5,DSISR
@ -242,7 +242,7 @@ Alignment:
/* Program check exception */
. = 0x700
ProgramCheck:
EXCEPTION_PROLOG
EXCEPTION_PROLOG(SRR0, SRR1)
addi r3,r1,STACK_FRAME_OVERHEAD
li r20,MSR_KERNEL
rlwimi r20,r23,0,16,16 /* copy EE bit from saved MSR */

30
cpu/ppc4xx/405gp_pci.c
View File

@ -77,11 +77,21 @@
#include <asm/processor.h>
#include <pci.h>
#ifdef CONFIG_PCI
DECLARE_GLOBAL_DATA_PTR;
#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
/*
* Board-specific pci initialization
* Platform code can reimplement pci_pre_init() if needed
*/
int __pci_pre_init(struct pci_controller *hose)
{
return 1;
}
int pci_pre_init(struct pci_controller *hose) __attribute__((weak, alias("__pci_pre_init")));
#ifdef CONFIG_PCI
#if defined(CONFIG_405GP) || defined(CONFIG_405EP)
#if defined(CONFIG_PMC405)
ushort pmc405_pci_subsys_deviceid(void);
@ -191,6 +201,13 @@ void pci_405gp_init(struct pci_controller *hose)
if (hose->pci_fb)
pciauto_region_init(hose->pci_fb);
/* Let board change/modify hose & do initial checks */
if (pci_pre_init (hose) == 0) {
printf("PCI: Board-specific initialization failed.\n");
printf("PCI: Configuration aborted.\n");
return;
}
pci_register_hose(hose);
/*--------------------------------------------------------------------------+
@ -416,14 +433,12 @@ void pci_init_board(void)
#endif
#endif /* CONFIG_PCI */
#endif /* CONFIG_405GP */
/*-----------------------------------------------------------------------------+
* CONFIG_440
*-----------------------------------------------------------------------------*/
#if defined(CONFIG_440) && defined(CONFIG_PCI)
#if defined(CONFIG_440)
static struct pci_controller ppc440_hose = {0};
@ -496,14 +511,12 @@ void pci_440_init (struct pci_controller *hose)
pci_setup_indirect(hose, PCIX0_CFGADR, PCIX0_CFGDATA);
#if defined(CFG_PCI_PRE_INIT)
/* Let board change/modify hose & do initial checks */
if (pci_pre_init (hose) == 0) {
printf("PCI: Board-specific initialization failed.\n");
printf("PCI: Configuration aborted.\n");
return;
}
#endif
pci_register_hose( hose );
@ -575,4 +588,5 @@ void pci_init_board(void)
#endif
}
#endif /* CONFIG_440 & CONFIG_PCI */
#endif /* CONFIG_440 */
#endif /* CONFIG_PCI */

4
cpu/ppc4xx/44x_spd_ddr.c
View File

@ -1340,14 +1340,14 @@ static unsigned long program_bxcr(unsigned long *dimm_populated,
*/
cr |= SDRAM_BXCR_SDBE;
for (i = 0; i < num_banks; i++) {
for (i = 0; i < num_banks; i++) {
bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes =
(4 << 20) * bank_size_id;
bank_parms[ctrl_bank_num[dimm_num]+i].cr = cr;
debug("DIMM%d-bank %d (SDRAM0_B%dCR): bank_size_bytes=%d\n",
dimm_num, i, ctrl_bank_num[dimm_num]+i,
bank_parms[ctrl_bank_num[dimm_num]+i].bank_size_bytes);
}
}
}
}

4
cpu/ppc4xx/44x_spd_ddr2.c
View File

@ -58,8 +58,8 @@
#define SDRAM_DDR2 2
#define SDRAM_NONE 0
#define MAXDIMMS 2
#define MAXRANKS 4
#define MAXDIMMS 2
#define MAXRANKS 4
#define MAXBXCF 4
#define MAX_SPD_BYTES 256 /* Max number of bytes on the DIMM's SPD EEPROM */

2
cpu/ppc4xx/config.mk
View File

@ -24,7 +24,7 @@
PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing
PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -ffixed-r29 -mstring -msoft-float
cfg=$(shell grep configs $(TOPDIR)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')
is440=$(shell grep CONFIG_440 $(TOPDIR)/include/$(cfg))
ifneq (,$(findstring CONFIG_440,$(is440)))

4
cpu/ppc4xx/cpu_init.c
View File

@ -153,7 +153,7 @@ cpu_init_f (void)
*/
asm volatile(" bl 0f" ::: "lr");
asm volatile("0: mflr 3" ::: "r3");
asm volatile(" addi 4, 0, 14" ::: "r4");
asm volatile(" addi 4, 0, 14" ::: "r4");
asm volatile(" mtctr 4" ::: "ctr");
asm volatile("1: icbt 0, 3");
asm volatile(" addi 3, 3, 32" ::: "r3");
@ -211,6 +211,8 @@ cpu_init_f (void)
val = mfspr(tcr);
#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
val |= 0xb8000000; /* generate system reset after 1.34 seconds */
#elif defined(CONFIG_440EPX)
val |= 0xb0000000; /* generate system reset after 1.34 seconds */
#else
val |= 0xf0000000; /* generate system reset after 2.684 seconds */
#endif

1
cpu/ppc4xx/start.S
View File

@ -60,7 +60,6 @@
* address and (s)dram will be positioned at address 0
*/
#include <config.h>
#include <mpc8xx.h>
#include <ppc4xx.h>
#include <version.h>

8
cpu/ppc4xx/tlb.c
View File

@ -101,6 +101,7 @@ static void program_tlb_addr(unsigned long phys_addr,
TLB_WORD0_SIZE_256MB, tlb_i)) == 0) {
mem_size -= TLB_256MB_SIZE;
phys_addr += TLB_256MB_SIZE;
virt_addr += TLB_256MB_SIZE;
}
} else if (((phys_addr & TLB_16MB_ALIGN_MASK) == phys_addr) &&
(mem_size >= TLB_16MB_SIZE)) {
@ -109,6 +110,7 @@ static void program_tlb_addr(unsigned long phys_addr,
TLB_WORD0_SIZE_16MB, tlb_i)) == 0) {
mem_size -= TLB_16MB_SIZE;
phys_addr += TLB_16MB_SIZE;
virt_addr += TLB_16MB_SIZE;
}
} else if (((phys_addr & TLB_1MB_ALIGN_MASK) == phys_addr) &&
(mem_size >= TLB_1MB_SIZE)) {
@ -117,6 +119,7 @@ static void program_tlb_addr(unsigned long phys_addr,
TLB_WORD0_SIZE_1MB, tlb_i)) == 0) {
mem_size -= TLB_1MB_SIZE;
phys_addr += TLB_1MB_SIZE;
virt_addr += TLB_1MB_SIZE;
}
} else if (((phys_addr & TLB_256KB_ALIGN_MASK) == phys_addr) &&
(mem_size >= TLB_256KB_SIZE)) {
@ -125,6 +128,7 @@ static void program_tlb_addr(unsigned long phys_addr,
TLB_WORD0_SIZE_256KB, tlb_i)) == 0) {
mem_size -= TLB_256KB_SIZE;
phys_addr += TLB_256KB_SIZE;
virt_addr += TLB_256KB_SIZE;
}
} else if (((phys_addr & TLB_64KB_ALIGN_MASK) == phys_addr) &&
(mem_size >= TLB_64KB_SIZE)) {
@ -133,6 +137,7 @@ static void program_tlb_addr(unsigned long phys_addr,
TLB_WORD0_SIZE_64KB, tlb_i)) == 0) {
mem_size -= TLB_64KB_SIZE;
phys_addr += TLB_64KB_SIZE;
virt_addr += TLB_64KB_SIZE;
}
} else if (((phys_addr & TLB_16KB_ALIGN_MASK) == phys_addr) &&
(mem_size >= TLB_16KB_SIZE)) {
@ -141,6 +146,7 @@ static void program_tlb_addr(unsigned long phys_addr,
TLB_WORD0_SIZE_16KB, tlb_i)) == 0) {
mem_size -= TLB_16KB_SIZE;
phys_addr += TLB_16KB_SIZE;
virt_addr += TLB_16KB_SIZE;
}
} else if (((phys_addr & TLB_4KB_ALIGN_MASK) == phys_addr) &&
(mem_size >= TLB_4KB_SIZE)) {
@ -149,6 +155,7 @@ static void program_tlb_addr(unsigned long phys_addr,
TLB_WORD0_SIZE_4KB, tlb_i)) == 0) {
mem_size -= TLB_4KB_SIZE;
phys_addr += TLB_4KB_SIZE;
virt_addr += TLB_4KB_SIZE;
}
} else if (((phys_addr & TLB_1KB_ALIGN_MASK) == phys_addr) &&
(mem_size >= TLB_1KB_SIZE)) {
@ -157,6 +164,7 @@ static void program_tlb_addr(unsigned long phys_addr,
TLB_WORD0_SIZE_1KB, tlb_i)) == 0) {
mem_size -= TLB_1KB_SIZE;
phys_addr += TLB_1KB_SIZE;
virt_addr += TLB_1KB_SIZE;
}
} else {
printf("ERROR: no TLB size exists for the base address 0x%0X.\n",

87
cpu/ppc4xx/traps.c Normal file → Executable file
View File

@ -145,6 +145,9 @@ void
MachineCheckException(struct pt_regs *regs)
{
unsigned long fixup, val;
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
u32 value2;
#endif
/* Probing PCI using config cycles cause this exception
* when a device is not present. Catch it and return to
@ -203,7 +206,89 @@ MachineCheckException(struct pt_regs *regs)
/* Clear MCSR */
mtspr(SPRN_MCSR, val);
}
#endif
#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
mfsdram(DDR0_00, val) ;
printf("DDR0: DDR0_00 %p\n", val);
val = (val >> 16) & 0xff;
if (val & 0x80)
printf("DDR0: At least one interrupt active\n");
if (val & 0x40)
printf("DDR0: DRAM initialization complete.\n");
if (val & 0x20)
printf("DDR0: Multiple uncorrectable ECC events.\n");
if (val & 0x10)
printf("DDR0: Single uncorrectable ECC event.\n");
if (val & 0x08)
printf("DDR0: Multiple correctable ECC events.\n");
if (val & 0x04)
printf("DDR0: Single correctable ECC event.\n");
if (val & 0x02)
printf("Multiple accesses outside the defined"
" physical memory space detected\n");
if (val & 0x01)
printf("DDR0: Single access outside the defined"
" physical memory space detected.\n");
mfsdram(DDR0_01, val);
val = (val >> 8) & 0x7;
switch (val ) {
case 0:
printf("DDR0: Write Out-of-Range command\n");
break;
case 1:
printf("DDR0: Read Out-of-Range command\n");
break;
case 2:
printf("DDR0: Masked write Out-of-Range command\n");
break;
case 4:
printf("DDR0: Wrap write Out-of-Range command\n");
break;
case 5:
printf("DDR0: Wrap read Out-of-Range command\n");
break;
default:
mfsdram(DDR0_01, value2);
printf("DDR0: No DDR0 error know 0x%x %p\n", val, value2);
}
mfsdram(DDR0_23, val);
if ( (val >> 16) & 0xff)
printf("DDR0: Syndrome for correctable ECC event 0x%x\n",
(val >> 16) & 0xff);
mfsdram(DDR0_23, val);
if ( (val >> 8) & 0xff)
printf("DDR0: Syndrome for uncorrectable ECC event 0x%x\n",
(val >> 8) & 0xff);
mfsdram(DDR0_33, val);
if (val)
printf("DDR0: Address of command that caused an "
"Out-of-Range interrupt %p\n", val);
mfsdram(DDR0_34, val);
if (val)
printf("DDR0: Address of uncorrectable ECC event %p\n", val);
mfsdram(DDR0_35, val);
if (val)
printf("DDR0: Address of uncorrectable ECC event %p\n", val);
mfsdram(DDR0_36, val);
if (val)
printf("DDR0: Data of uncorrectable ECC event 0x%08x\n", val);
mfsdram(DDR0_37, val);
if (val)
printf("DDR0: Data of uncorrectable ECC event 0x%08x\n", val);
mfsdram(DDR0_38, val);
if (val)
printf("DDR0: Address of correctable ECC event %p\n", val);
mfsdram(DDR0_39, val);
if (val)
printf("DDR0: Address of correctable ECC event %p\n", val);
mfsdram(DDR0_40, val);
if (val)
printf("DDR0: Data of correctable ECC event 0x%08x\n", val);
mfsdram(DDR0_41, val);
if (val)
printf("DDR0: Data of correctable ECC event 0x%08x\n", val);
#endif /* CONFIG_440EPX */
#endif /* CONFIG_440 */
show_regs(regs);
print_backtrace((unsigned long *)regs->gpr[1]);
panic("machine check");

13
doc/README.ppc440
View File

@ -146,12 +146,13 @@ that maps in a single PCI I/O space and PCI memory space. The I/O
space begins at PCI I/O address 0 and the PCI memory space is
256 MB starting at PCI address CFG_PCI_TARGBASE. After the
pci_controller structure is initialized, the cpu-specific code will
call the routine pci_pre_init() if the CFG_PCI_PRE_INIT flag is
defined. This routine is implemented by board-specific code & is where
the board can over-ride/extend the default pci_controller structure
settings and do other pre-initialization tasks. If pci_pre_init()
returns a value of zero, PCI initialization is aborted; otherwise the
controller structure is registered and initialization continues.
call the routine pci_pre_init(). This routine is implemented by
board-specific code & is where the board can over-ride/extend the
default pci_controller structure settings and exspecially provide
a routine to map the PCI interrupts and do other pre-initialization
tasks. If pci_pre_init() returns a value of zero, PCI initialization
is aborted; otherwise the controller structure is registered and
initialization continues.
The default 440GP PCI target configuration is minimal -- it assumes that
the strapping registers are set as necessary. Since the strapping bits

2
drivers/Makefile
View File

@ -27,7 +27,7 @@ include $(TOPDIR)/config.mk
LIB = $(obj)libdrivers.a
COBJS = 3c589.o 5701rls.o ali512x.o atmel_usart.o \
COBJS = 3c589.o 5701rls.o ali512x.o ata_piix.o atmel_usart.o \
bcm570x.o bcm570x_autoneg.o cfb_console.o cfi_flash.o \
cs8900.o ct69000.o dataflash.o dc2114x.o dm9000x.o \
e1000.o eepro100.o enc28j60.o \

216
drivers/ata_piix.c Normal file
View File

@ -0,0 +1,216 @@
/*
* Copyright (C) Procsys. All rights reserved.
* Author: Mushtaq Khan <mushtaq_k@procsys.com>
* <mushtaqk_921@yahoo.co.in>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
* with the reference to ata_piix driver in kernel 2.4.32
*/
/*
* This file contains SATA controller and SATA drive initialization functions
*/
#include <common.h>
#include <pci.h>
#include <command.h>
#include <config.h>
#include <asm/byteorder.h>
#include <ide.h>
#include <ata.h>
#ifdef CFG_ATA_PIIX /*ata_piix driver */
#define DEBUG_SATA 0 /*For debug prints set DEBUG_SATA to 1 */
#define DRV_DECL /*For file specific declarations */
#include <sata.h>
#undef DRV_DECL
/*Macros realted to PCI*/
#define PCI_SATA_BUS 0x00
#define PCI_SATA_DEV 0x1f
#define PCI_SATA_FUNC 0x02
#define PCI_SATA_BASE1 0x10
#define PCI_SATA_BASE2 0x14
#define PCI_SATA_BASE3 0x18
#define PCI_SATA_BASE4 0x1c
#define PCI_SATA_BASE5 0x20
#define PCI_PMR 0x90
#define PCI_PI 0x09
#define PCI_PCS 0x92
#define PCI_DMA_CTL 0x48
#define PORT_PRESENT (1<<0)
#define PORT_ENABLED (1<<4)
u32 bdf;
u32 iobase1 = 0; /*Primary cmd block */
u32 iobase2 = 0; /*Primary ctl block */
u32 iobase3 = 0; /*Sec cmd block */
u32 iobase4 = 0; /*sec ctl block */
u32 iobase5 = 0; /*BMDMA*/
int
pci_sata_init (void)
{
u32 bus = PCI_SATA_BUS;
u32 dev = PCI_SATA_DEV;
u32 fun = PCI_SATA_FUNC;
u16 cmd = 0;
u8 lat = 0, pcibios_max_latency = 0xff;
u8 pmr; /*Port mapping reg */
u8 pi; /*Prgming Interface reg */
bdf = PCI_BDF (bus, dev, fun);
pci_read_config_dword (bdf, PCI_SATA_BASE1, &iobase1);
pci_read_config_dword (bdf, PCI_SATA_BASE2, &iobase2);
pci_read_config_dword (bdf, PCI_SATA_BASE3, &iobase3);
pci_read_config_dword (bdf, PCI_SATA_BASE4, &iobase4);
pci_read_config_dword (bdf, PCI_SATA_BASE5, &iobase5);
if ((iobase1 == 0xFFFFFFFF) || (iobase2 == 0xFFFFFFFF) ||
(iobase3 == 0xFFFFFFFF) || (iobase4 == 0xFFFFFFFF) ||
(iobase5 == 0xFFFFFFFF)) {
printf ("error no base addr for SATA controller\n");
return 1;
/*ERROR*/}
iobase1 &= 0xFFFFFFFE;
iobase2 &= 0xFFFFFFFE;
iobase3 &= 0xFFFFFFFE;
iobase4 &= 0xFFFFFFFE;
iobase5 &= 0xFFFFFFFE;
/*check for mode */
pci_read_config_byte (bdf, PCI_PMR, &pmr);
if (pmr > 1) {
printf ("combined mode not supported\n");
return 1;
}
pci_read_config_byte (bdf, PCI_PI, &pi);
if ((pi & 0x05) != 0x05) {
printf ("Sata is in Legacy mode\n");
return 1;
} else {
printf ("sata is in Native mode\n");
}
/*MASTER CFG AND IO CFG */
pci_read_config_word (bdf, PCI_COMMAND, &cmd);
cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_IO;
pci_write_config_word (bdf, PCI_COMMAND, cmd);
pci_read_config_byte (dev, PCI_LATENCY_TIMER, &lat);
if (lat < 16)
lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
else if (lat > pcibios_max_latency)
lat = pcibios_max_latency;
pci_write_config_byte (dev, PCI_LATENCY_TIMER, lat);
return 0;
}
int
sata_bus_probe (int port_no)
{
int orig_mask, mask;
u16 pcs;
mask = (PORT_PRESENT << port_no);
pci_read_config_word (bdf, PCI_PCS, &pcs);
orig_mask = (int) pcs & 0xff;
if ((orig_mask & mask) != mask)
return 0;
else
return 1;
}
int
init_sata (void)
{
u8 i, rv = 0;
for (i = 0; i < CFG_SATA_MAXDEVICES; i++) {
sata_dev_desc[i].type = DEV_TYPE_UNKNOWN;
sata_dev_desc[i].if_type = IF_TYPE_IDE;
sata_dev_desc[i].dev = i;
sata_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
sata_dev_desc[i].blksz = 0;
sata_dev_desc[i].lba = 0;
sata_dev_desc[i].block_read = sata_read;
}
rv = pci_sata_init ();
if (rv == 1) {
printf ("pci initialization failed\n");
return 1;
}
port[0].port_no = 0;
port[0].ioaddr.cmd_addr = iobase1;
port[0].ioaddr.altstatus_addr = port[0].ioaddr.ctl_addr =
iobase2 | ATA_PCI_CTL_OFS;
port[0].ioaddr.bmdma_addr = iobase5;
port[1].port_no = 1;
port[1].ioaddr.cmd_addr = iobase3;
port[1].ioaddr.altstatus_addr = port[1].ioaddr.ctl_addr =
iobase4 | ATA_PCI_CTL_OFS;
port[1].ioaddr.bmdma_addr = iobase5 + 0x8;
for (i = 0; i < CFG_SATA_MAXBUS; i++)
sata_port (&port[i].ioaddr);
for (i = 0; i < CFG_SATA_MAXBUS; i++) {
if (!(sata_bus_probe (i))) {
port[i].port_state = 0;
printf ("SATA#%d port is not present \n", i);
} else {
printf ("SATA#%d port is present\n", i);
if (sata_bus_softreset (i)) {
port[i].port_state = 0;
} else {
port[i].port_state = 1;
}
}
}
for (i = 0; i < CFG_SATA_MAXBUS; i++) {
u8 j, devno;
if (port[i].port_state == 0)
continue;
for (j = 0; j < CFG_SATA_DEVS_PER_BUS; j++) {
sata_identify (i, j);
set_Feature_cmd (i, j);
devno = i * CFG_SATA_DEVS_PER_BUS + j;
if ((sata_dev_desc[devno].lba > 0) &&
(sata_dev_desc[devno].blksz > 0)) {
dev_print (&sata_dev_desc[devno]);
/* initialize partition type */
init_part (&sata_dev_desc[devno]);
if (curr_dev < 0)
curr_dev =
i * CFG_SATA_DEVS_PER_BUS + j;
}
}
}
return 0;
}
#endif

46
drivers/tsec.c
View File

@ -65,33 +65,31 @@ struct tsec_info_struct {
* FEC_PHYIDX
*/
static struct tsec_info_struct tsec_info[] = {
#if defined(CONFIG_MPC85XX_TSEC1) || defined(CONFIG_MPC83XX_TSEC1)
#if defined(CONFIG_MPC8544DS)
#if defined(CONFIG_TSEC1)
#if defined(CONFIG_MPC8544DS) || defined(CONFIG_MPC8641HPCN)
{TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
#else
{TSEC1_PHY_ADDR, TSEC_GIGABIT, TSEC1_PHYIDX},
#endif
#elif defined(CONFIG_MPC86XX_TSEC1)
{TSEC1_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC1_PHYIDX},
#else
{0, 0, 0},
#endif
#if defined(CONFIG_MPC85XX_TSEC2) || defined(CONFIG_MPC83XX_TSEC2)
{TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
#elif defined(CONFIG_MPC86XX_TSEC2)
#if defined(CONFIG_TSEC2)
#if defined(CONFIG_MPC8641HPCN)
{TSEC2_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC2_PHYIDX},
#else
{TSEC2_PHY_ADDR, TSEC_GIGABIT, TSEC2_PHYIDX},
#endif
{0, 0, 0},
#endif
#ifdef CONFIG_MPC85XX_FEC
{FEC_PHY_ADDR, 0, FEC_PHYIDX},
#else
#if defined(CONFIG_MPC85XX_TSEC3) || defined(CONFIG_MPC83XX_TSEC3) || defined(CONFIG_MPC86XX_TSEC3)
#if defined(CONFIG_TSEC3)
{TSEC3_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC3_PHYIDX},
#else
{0, 0, 0},
#endif
#if defined(CONFIG_MPC85XX_TSEC4) || defined(CONFIG_MPC83XX_TSEC4) || defined(CONFIG_MPC86XX_TSEC4)
#if defined(CONFIG_TSEC4)
{TSEC4_PHY_ADDR, TSEC_GIGABIT | TSEC_REDUCED, TSEC4_PHYIDX},
#else
{0, 0, 0},
@ -928,6 +926,33 @@ struct phy_info phy_info_BCM5461S = {
},
};
struct phy_info phy_info_BCM5464S = {
0x02060b1, /* 5464 ID */
"Broadcom BCM5464S",
0, /* not clear to me what minor revisions we can shift away */
(struct phy_cmd[]) { /* config */
/* Reset and configure the PHY */
{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
{MIIM_GBIT_CONTROL, MIIM_GBIT_CONTROL_INIT, NULL},
{MIIM_ANAR, MIIM_ANAR_INIT, NULL},
{MIIM_CONTROL, MIIM_CONTROL_RESET, NULL},
{MIIM_CONTROL, MIIM_CONTROL_INIT, &mii_cr_init},
{miim_end,}
},
(struct phy_cmd[]) { /* startup */
/* Status is read once to clear old link state */
{MIIM_STATUS, miim_read, NULL},
/* Auto-negotiate */
{MIIM_STATUS, miim_read, &mii_parse_sr},
/* Read the status */
{MIIM_BCM54xx_AUXSTATUS, miim_read, &mii_parse_BCM54xx_sr},
{miim_end,}
},
(struct phy_cmd[]) { /* shutdown */
{miim_end,}
},
};
struct phy_info phy_info_M88E1011S = {
0x01410c6,
"Marvell 88E1011S",
@ -1292,6 +1317,7 @@ struct phy_info *phy_info[] = {
&phy_info_cis8204,
&phy_info_cis8201,
&phy_info_BCM5461S,
&phy_info_BCM5464S,
&phy_info_M88E1011S,
&phy_info_M88E1111S,
&phy_info_M88E1145,

1
include/74xx_7xx.h
View File

@ -34,6 +34,7 @@
* Exception offsets (PowerPC standard)
*/
#define EXC_OFF_SYS_RESET 0x0100 /* default system reset offset */
#define _START_OFFSET EXC_OFF_SYS_RESET
/*----------------------------------------------------------------
* l2cr values

46
include/asm-ppc/processor.h
View File

@ -35,18 +35,18 @@
#define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */
#define MSR_UBLE (1<<10) /* BTB lock enable (e500) */
#define MSR_BE (1<<9) /* Branch Trace */
#define MSR_DE (1<<9) /* Debug Exception Enable */
#define MSR_DE (1<<9) /* Debug Exception Enable */
#define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
#define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
#define MSR_IR (1<<5) /* Instruction Relocate */
#define MSR_IR (1<<5) /* Instruction Relocate */
#define MSR_IS (1<<5) /* Book E Instruction space */
#define MSR_DR (1<<4) /* Data Relocate */
#define MSR_DR (1<<4) /* Data Relocate */
#define MSR_DS (1<<4) /* Book E Data space */
#define MSR_PE (1<<3) /* Protection Enable */
#define MSR_PX (1<<2) /* Protection Exclusive Mode */
#define MSR_PMM (1<<2) /* Performance monitor mark bit (e500) */
#define MSR_RI (1<<1) /* Recoverable Exception */
#define MSR_LE (1<<0) /* Little Endian */
#define MSR_LE (1<<0) /* Little Endian */
#ifdef CONFIG_APUS_FAST_EXCEPT
#define MSR_ MSR_ME|MSR_IP|MSR_RI
@ -123,9 +123,9 @@
#define DBCR_EDM 0x80000000
#define DBCR_IDM 0x40000000
#define DBCR_RST(x) (((x) & 0x3) << 28)
#define DBCR_RST_NONE 0
#define DBCR_RST_CORE 1
#define DBCR_RST_CHIP 2
#define DBCR_RST_NONE 0
#define DBCR_RST_CORE 1
#define DBCR_RST_CHIP 2
#define DBCR_RST_SYSTEM 3
#define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */
#define DBCR_BT 0x04000000 /* Branch Taken Debug Event */
@ -266,7 +266,7 @@
#define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
#define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
#define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
#define SPRN_IMMR 0x27E /* Internal Memory Map Register */
#define SPRN_LDSTCR 0x3F8 /* Load/Store Control Register */
#define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
#define SPRN_LR 0x008 /* Link Register */
@ -495,17 +495,17 @@
#define DBCR0 SPRN_DBCR0 /* Debug Control Register 0 */
#define DBCR1 SPRN_DBCR1 /* Debug Control Register 1 */
#define DBSR SPRN_DBSR /* Debug Status Register */
#define DCMP SPRN_DCMP /* Data TLB Compare Register */
#define DEC SPRN_DEC /* Decrement Register */
#define DMISS SPRN_DMISS /* Data TLB Miss Register */
#define DCMP SPRN_DCMP /* Data TLB Compare Register */
#define DEC SPRN_DEC /* Decrement Register */
#define DMISS SPRN_DMISS /* Data TLB Miss Register */
#define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */
#define EAR SPRN_EAR /* External Address Register */
#define EAR SPRN_EAR /* External Address Register */
#define ESR SPRN_ESR /* Exception Syndrome Register */
#define HASH1 SPRN_HASH1 /* Primary Hash Address Register */
#define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */
#define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */
#define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */
#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
#define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
#define IAC1 SPRN_IAC1 /* Instruction Address Register 1 */
#define IAC2 SPRN_IAC2 /* Instruction Address Register 2 */
#define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */
@ -522,13 +522,13 @@
#define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */
#define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */
#define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */
#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */
#define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */
#define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Lower Register */
#define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
#define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
#define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
#define LDSTCR SPRN_LDSTCR /* Load/Store Control Register */
#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
#define L2CR SPRN_L2CR /* PPC 750 L2 control register */
#define LR SPRN_LR
#define MBAR SPRN_MBAR /* System memory base address */
#if defined(CONFIG_MPC86xx)
@ -540,7 +540,7 @@
#define SVR SPRN_SVR /* System-On-Chip Version Register */
#define PVR SPRN_PVR /* Processor Version */
#define RPA SPRN_RPA /* Required Physical Address Register */
#define SDR1 SPRN_SDR1 /* MMU hash base register */
#define SDR1 SPRN_SDR1 /* MMU hash base register */
#define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */
#define SPR1 SPRN_SPRG1
#define SPR2 SPRN_SPRG2
@ -611,7 +611,7 @@
#define IVOR35 SPRN_IVOR35
#define MCSRR0 SPRN_MCSRR0
#define MCSRR1 SPRN_MCSRR1
#define L1CSR0 SPRN_L1CSR0
#define L1CSR0 SPRN_L1CSR0
#define L1CSR1 SPRN_L1CSR1
#define MCSR SPRN_MCSR
#define MMUCSR0 SPRN_MMUCSR0
@ -620,7 +620,7 @@
#define PID1 SPRN_PID1
#define PID2 SPRN_PID2
#define MAS0 SPRN_MAS0
#define MAS1 SPRN_MAS1
#define MAS1 SPRN_MAS1
#define MAS2 SPRN_MAS2
#define MAS3 SPRN_MAS3
#define MAS4 SPRN_MAS4
@ -632,7 +632,7 @@
#define DCRN_BEAR 0x090 /* Bus Error Address Register */
#define DCRN_BESR 0x091 /* Bus Error Syndrome Register */
#define BESR_DSES 0x80000000 /* Data-Side Error Status */
#define BESR_DSES 0x80000000 /* Data-Side Error Status */
#define BESR_DMES 0x40000000 /* DMA Error Status */
#define BESR_RWS 0x20000000 /* Read/Write Status */
#define BESR_ETMASK 0x1C000000 /* Error Type */
@ -689,8 +689,8 @@
#define IOCR_E3LP 0x01000000
#define IOCR_E4TE 0x00800000
#define IOCR_E4LP 0x00400000
#define IOCR_EDT 0x00080000
#define IOCR_SOR 0x00040000
#define IOCR_EDT 0x00080000
#define IOCR_SOR 0x00040000
#define IOCR_EDO 0x00008000
#define IOCR_2XC 0x00004000
#define IOCR_ATC 0x00002000
@ -815,7 +815,7 @@
#define PVR_823 PVR_821
#define PVR_850 PVR_821
#define PVR_860 PVR_821
#define PVR_7400 0x000C0000
#define PVR_7400 0x000C0000
#define PVR_8240 0x00810100
/*

60
include/ata.h
View File

@ -83,6 +83,66 @@
#define ATA_DEVICE(x) ((x & 1)<<4)
#define ATA_LBA 0xE0
enum {
ATA_MAX_DEVICES = 1, /* per bus/port */
ATA_MAX_PRD = 256, /* we could make these 256/256 */
ATA_SECT_SIZE = 256, /*256 words per sector */
/* bits in ATA command block registers */
ATA_HOB = (1 << 7), /* LBA48 selector */
ATA_NIEN = (1 << 1), /* disable-irq flag */
/*ATA_LBA = (1 << 6), */ /* LBA28 selector */
ATA_DEV1 = (1 << 4), /* Select Device 1 (slave) */
ATA_DEVICE_OBS = (1 << 7) | (1 << 5), /* obs bits in dev reg */
ATA_DEVCTL_OBS = (1 << 3), /* obsolete bit in devctl reg */
ATA_BUSY = (1 << 7), /* BSY status bit */
ATA_DRDY = (1 << 6), /* device ready */
ATA_DF = (1 << 5), /* device fault */
ATA_DRQ = (1 << 3), /* data request i/o */
ATA_ERR = (1 << 0), /* have an error */
ATA_SRST = (1 << 2), /* software reset */
ATA_ABORTED = (1 << 2), /* command aborted */
/* ATA command block registers */
ATA_REG_DATA = 0x00,
ATA_REG_ERR = 0x01,
ATA_REG_NSECT = 0x02,
ATA_REG_LBAL = 0x03,
ATA_REG_LBAM = 0x04,
ATA_REG_LBAH = 0x05,
ATA_REG_DEVICE = 0x06,
ATA_REG_STATUS = 0x07,
ATA_PCI_CTL_OFS = 0x02,
/* and their aliases */
ATA_REG_FEATURE = ATA_REG_ERR,
ATA_REG_CMD = ATA_REG_STATUS,
ATA_REG_BYTEL = ATA_REG_LBAM,
ATA_REG_BYTEH = ATA_REG_LBAH,
ATA_REG_DEVSEL = ATA_REG_DEVICE,
ATA_REG_IRQ = ATA_REG_NSECT,
/* SETFEATURES stuff */
SETFEATURES_XFER = 0x03,
XFER_UDMA_7 = 0x47,
XFER_UDMA_6 = 0x46,
XFER_UDMA_5 = 0x45,
XFER_UDMA_4 = 0x44,
XFER_UDMA_3 = 0x43,
XFER_UDMA_2 = 0x42,
XFER_UDMA_1 = 0x41,
XFER_UDMA_0 = 0x40,
XFER_MW_DMA_2 = 0x22,
XFER_MW_DMA_1 = 0x21,
XFER_MW_DMA_0 = 0x20,
XFER_PIO_4 = 0x0C,
XFER_PIO_3 = 0x0B,
XFER_PIO_2 = 0x0A,
XFER_PIO_1 = 0x09,
XFER_PIO_0 = 0x08,
XFER_SW_DMA_2 = 0x12,
XFER_SW_DMA_1 = 0x11,
XFER_SW_DMA_0 = 0x10,
XFER_PIO_SLOW = 0x00
};
/*
* ATA Commands (only mandatory commands listed here)
*/

9
include/common.h
View File

@ -38,7 +38,7 @@ typedef volatile unsigned char vu_char;
#include <linux/string.h>
#include <asm/ptrace.h>
#include <stdarg.h>
#if defined(CONFIG_PCI) && defined(CONFIG_440)
#if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000))
#include <pci.h>
#endif
#if defined(CONFIG_8xx)
@ -248,10 +248,11 @@ void pci_init (void);
void pci_init_board(void);
void pciinfo (int, int);
#if defined(CONFIG_PCI) && defined(CONFIG_440)
# if defined(CFG_PCI_PRE_INIT)
#if defined(CONFIG_PCI) && (defined(CONFIG_4xx) && !defined(CONFIG_AP1000))
int pci_pre_init (struct pci_controller * );
# endif
#endif
#if defined(CONFIG_PCI) && defined(CONFIG_440)
# if defined(CFG_PCI_TARGET_INIT)
void pci_target_init (struct pci_controller *);
# endif

4
include/configs/CPCI405.h
View File

@ -55,6 +55,10 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1
#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \
CONFIG_BOOTP_DNS | \

5
include/configs/CPCI4052.h
View File

@ -37,6 +37,7 @@
#define CONFIG_4xx 1 /* ...member of PPC4xx family */
#define CONFIG_CPCI405 1 /* ...on a CPCI405 board */
#define CONFIG_CPCI405_VER2 1 /* ...version 2 */
#undef CONFIG_CPCI405_6U /* enable this for 6U boards */
#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
@ -56,6 +57,10 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */

4
include/configs/CPCI405AB.h
View File

@ -57,6 +57,10 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */

4
include/configs/CPCI405DT.h
View File

@ -56,6 +56,10 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_PHY_ADDR 0 /* PHY address */
#define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */
#define CONFIG_NET_MULTI 1
#undef CONFIG_HAS_ETH1
#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */

1
include/configs/JSE.h
View File

@ -49,6 +49,7 @@
/* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */
#define CONFIG_SYSTEMACE 1
#define CFG_SYSTEMACE_BASE 0xf0000000
#define CFG_SYSTEMACE_WIDTH 8
#define CONFIG_DOS_PARTITION 1
/* Use the On-Chip-Memory (OCM) as a temporary stack for the startup code. */

1
include/configs/KAREF.h
View File

@ -263,7 +263,6 @@
#define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE)
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/
#define CFG_PCI_TARGET_INIT /* let board init pci target*/
#define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */

1
include/configs/METROBOX.h
View File

@ -332,7 +332,6 @@
#define CFG_PCI_TARGBASE (CFG_PCI_MEMBASE)
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init*/
#define CFG_PCI_TARGET_INIT /* let board init pci target*/
#define CFG_PCI_SUBSYS_VENDORID 0x17BA /* Sandburst */

8
include/configs/MPC8313ERDB.h
View File

@ -303,11 +303,11 @@
#endif
#define CONFIG_GMII 1 /* MII PHY management */
#define CONFIG_MPC83XX_TSEC1 1
#define CONFIG_TSEC1 1
#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC83XX_TSEC2 1
#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0x1c
#define TSEC2_PHY_ADDR 4
#define TSEC1_PHYIDX 0

8
include/configs/MPC8349EMDS.h
View File

@ -432,10 +432,10 @@
#endif
#define CONFIG_GMII 1 /* MII PHY management */
#define CONFIG_MPC83XX_TSEC1 1
#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC83XX_TSEC2 1
#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0

14
include/configs/MPC8349ITX.h
View File

@ -374,18 +374,18 @@ boards, we say we have two, but don't display a message if we find only one. */
#define CONFIG_MII
#define CONFIG_PHY_GIGE /* In case CFG_CMD_MII is specified */
#define CONFIG_MPC83XX_TSEC1
#define CONFIG_TSEC1
#ifdef CONFIG_MPC83XX_TSEC1
#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
#ifdef CONFIG_TSEC1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CFG_TSEC1_OFFSET 0x24000
#define TSEC1_PHY_ADDR 0x1c /* VSC8201 uses address 0x1c */
#define TSEC1_PHYIDX 0
#endif
#ifdef CONFIG_MPC83XX_TSEC2
#ifdef CONFIG_TSEC2
#define CONFIG_HAS_ETH1
#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
#define CONFIG_TSEC2_NAME "TSEC1"
#define CFG_TSEC2_OFFSET 0x25000
#define CONFIG_UNKNOWN_TSEC /* TSEC2 is proprietary */
#define TSEC2_PHY_ADDR 4
@ -628,11 +628,11 @@ boards, we say we have two, but don't display a message if we find only one. */
*/
#define CONFIG_ENV_OVERWRITE
#ifdef CONFIG_MPC83XX_TSEC1
#ifdef CONFIG_TSEC1
#define CONFIG_ETHADDR 00:E0:0C:00:8C:01
#endif
#ifdef CONFIG_MPC83XX_TSEC2
#ifdef CONFIG_TSEC2
#define CONFIG_ETH1ADDR 00:E0:0C:00:8C:02
#endif

8
include/configs/MPC8540ADS.h
View File

@ -366,10 +366,10 @@
#endif
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0

8
include/configs/MPC8540EVAL.h
View File

@ -212,10 +212,10 @@
#elif defined(CONFIG_TSEC_ENET)
#define CONFIG_NET_MULTI 1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#define CONFIG_MPC85XX_FEC 1
#define CONFIG_MPC85XX_FEC_NAME "FEC"
#define TSEC1_PHY_ADDR 7

8
include/configs/MPC8541CDS.h
View File

@ -373,10 +373,10 @@ extern unsigned long get_clock_freq(void);
#endif
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1

8
include/configs/MPC8544DS.h
View File

@ -359,10 +359,10 @@ extern unsigned long get_board_sys_clk(unsigned long dummy);
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC1"
#define CONFIG_MPC85XX_TSEC3 1
#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC3"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC1"
#define CONFIG_TSEC3 1
#define CONFIG_TSEC3_NAME "eTSEC3"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0

16
include/configs/MPC8548CDS.h
View File

@ -391,14 +391,14 @@ extern unsigned long get_clock_freq(void);
#endif
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0"
#define CONFIG_MPC85XX_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1"
#define CONFIG_MPC85XX_TSEC3 1
#define CONFIG_MPC85XX_TSEC3_NAME "eTSEC2"
#undef CONFIG_MPC85XX_TSEC4
#define CONFIG_MPC85XX_TSEC4_NAME "eTSEC3"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "eTSEC1"
#define CONFIG_TSEC3 1
#define CONFIG_TSEC3_NAME "eTSEC2"
#undef CONFIG_TSEC4
#define CONFIG_TSEC4_NAME "eTSEC3"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0

8
include/configs/MPC8555CDS.h
View File

@ -373,10 +373,10 @@ extern unsigned long get_clock_freq(void);
#endif
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1

8
include/configs/MPC8560ADS.h
View File

@ -356,10 +356,10 @@
#endif
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1

12
include/configs/MPC8568MDS.h
View File

@ -353,12 +353,12 @@ extern unsigned long get_clock_freq(void);
#endif
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "eTSEC0"
#define CONFIG_MPC85XX_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "eTSEC1"
#undef CONFIG_MPC85XX_TSEC3
#undef CONFIG_MPC85XX_TSEC4
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "eTSEC1"
#undef CONFIG_TSEC3
#undef CONFIG_TSEC4
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 2

16
include/configs/MPC8641HPCN.h
View File

@ -359,14 +359,14 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC86XX_TSEC1 1
#define CONFIG_MPC86XX_TSEC1_NAME "eTSEC1"
#define CONFIG_MPC86XX_TSEC2 1
#define CONFIG_MPC86XX_TSEC2_NAME "eTSEC2"
#define CONFIG_MPC86XX_TSEC3 1
#define CONFIG_MPC86XX_TSEC3_NAME "eTSEC3"
#define CONFIG_MPC86XX_TSEC4 1
#define CONFIG_MPC86XX_TSEC4_NAME "eTSEC4"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "eTSEC1"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "eTSEC2"
#define CONFIG_TSEC3 1
#define CONFIG_TSEC3_NAME "eTSEC3"
#define CONFIG_TSEC4 1
#define CONFIG_TSEC4_NAME "eTSEC4"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1

8
include/configs/PM854.h
View File

@ -262,10 +262,10 @@
#endif
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0

8
include/configs/PM856.h
View File

@ -258,10 +258,10 @@
#endif
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#undef CONFIG_MPC85XX_FEC
#define TSEC1_PHY_ADDR 0
#define TSEC2_PHY_ADDR 1

4
include/configs/TQM5200.h
View File

@ -44,7 +44,7 @@
#define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM 0x02 /* Software reboot */
#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
@ -238,7 +238,7 @@
"fdt_file=/tftpboot/tqm5200/tqm5200.dtb\0" \
"u-boot=/tftpboot/tqm5200/u-boot.bin\0"
#else
#define CUSTOM_ENV_SETTINGS \
#define CUSTOM_ENV_SETTINGS \
"bootfile=cam5200/uImage\0" \
"u-boot=cam5200/u-boot.bin\0" \
"setup=tftp 200000 cam5200/setup.img; autoscr 200000\0"

8
include/configs/TQM834x.h
View File

@ -248,10 +248,10 @@ extern int tqm834x_num_flash_banks;
#define CONFIG_NET_MULTI
#endif
#define CONFIG_MPC83XX_TSEC1 1
#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC83XX_TSEC2 1
#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0

8
include/configs/TQM85xx.h
View File

@ -258,10 +258,10 @@
#define CONFIG_NET_MULTI 1
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#define TSEC1_PHY_ADDR 2
#define TSEC2_PHY_ADDR 1
#define TSEC1_PHYIDX 0

1
include/configs/XPEDITE1K.h
View File

@ -238,7 +238,6 @@ extern void out32(unsigned int, unsigned long);
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */

5
include/configs/alpr.h
View File

@ -95,7 +95,7 @@
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
@ -257,7 +257,7 @@
#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
#define CONFIG_LOOPW 1 /* enable loopw command */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
@ -275,7 +275,6 @@
#define CONFIG_PCI_BOOTDELAY 1 /* enable pci bootdelay variable*/
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#define CFG_PCI_MASTER_INIT

15
include/configs/bamboo.h
View File

@ -74,9 +74,9 @@
* Initial RAM & stack pointer (placed in SDRAM)
*----------------------------------------------------------------------*/
#define CFG_INIT_RAM_DCACHE 1 /* d-cache as init ram */
#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CFG_INIT_RAM_ADDR 0x70000000 /* DCache */
#define CFG_INIT_RAM_END (4 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
@ -115,8 +115,8 @@
/*-----------------------------------------------------------------------
* FLASH related
*----------------------------------------------------------------------*/
#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
#define CFG_MAX_FLASH_BANKS 3 /* number of banks */
#define CFG_MAX_FLASH_SECT 256 /* sectors per device */
#undef CFG_FLASH_CHECKSUM
#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
@ -126,11 +126,11 @@
#define CFG_FLASH_ADDR1 0x2aa
#define CFG_FLASH_WORD_SIZE unsigned char
#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */
#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */
#define CFG_FLASH_2ND_16BIT_DEV 1 /* bamboo has 8 and 16bit device */
#define CFG_FLASH_2ND_ADDR 0x87800000 /* bamboo has 8 and 16bit device */
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
@ -389,7 +389,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT

3
include/configs/ebony.h
View File

@ -122,7 +122,7 @@
#define CFG_FLASH_WORD_SIZE unsigned char
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
@ -270,7 +270,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */

1
include/configs/katmai.h
View File

@ -314,7 +314,6 @@
#undef CONFIG_PCI_CONFIG_HOST_BRIDGE
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT 1 /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#undef CFG_PCI_MASTER_INIT

1
include/configs/luan.h
View File

@ -273,7 +273,6 @@
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#undef CFG_PCI_MASTER_INIT

5
include/configs/lwmon5.h
View File

@ -117,7 +117,7 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
@ -288,7 +288,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT
@ -360,7 +359,7 @@
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15 */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \

3
include/configs/ocotea.h
View File

@ -137,7 +137,7 @@
#define CFG_FLASH_WORD_SIZE unsigned char
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
@ -294,7 +294,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */

3
include/configs/p3p440.h
View File

@ -227,7 +227,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#define CONFIG_DISABLE_PISE_TEST /* disable PISE test (PCIX only)*/
@ -286,7 +285,7 @@
#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */

3
include/configs/pcs440ep.h
View File

@ -104,7 +104,7 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
@ -267,7 +267,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT

8
include/configs/sbc8349.h
View File

@ -401,10 +401,10 @@
#define CONFIG_NET_MULTI 1
#endif
#define CONFIG_MPC83XX_TSEC1 1
#define CONFIG_MPC83XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC83XX_TSEC2 1
#define CONFIG_MPC83XX_TSEC2_NAME "TSEC1"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#define CONFIG_PHY_BCM5421S 1
#define TSEC1_PHY_ADDR 0x19
#define TSEC2_PHY_ADDR 0x1a

9
include/configs/sc520_cdp.h
View File

@ -181,6 +181,15 @@
#undef CONFIG_IDE_RESET /* reset for ide unsupported... */
#undef CONFIG_IDE_RESET_ROUTINE /* no special reset function */
/************************************************************
*SATA/Native Stuff
************************************************************/
#define CFG_SATA_SUPPORTED 1
#define CFG_SATA_MAXBUS 2 /*Max Sata buses supported */
#define CFG_SATA_DEVS_PER_BUS 2 /*Max no. of devices per bus/port */
#define CFG_SATA_MAXDEVICES (CFG_SATA_MAXBUS* CFG_SATA_DEVS_PER_BUS)
#define CFG_ATA_PIIX 1 /*Supports ata_piix driver */
/************************************************************
* ATAPI support (experimental)
************************************************************/

18
include/configs/sequoia.h
View File

@ -59,6 +59,7 @@
#define CFG_MONITOR_BASE TEXT_BASE
#define CFG_NAND_ADDR 0xd0000000 /* NAND Flash */
#define CFG_OCM_BASE 0xe0010000 /* ocm */
#define CFG_OCM_DATA_ADDR CFG_OCM_BASE
#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */
#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */
#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000
@ -81,7 +82,7 @@
#define CFG_INIT_RAM_END (4 << 10)
#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */
#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
/*-----------------------------------------------------------------------
* Serial Port
@ -126,7 +127,7 @@
#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
@ -328,6 +329,18 @@
CFG_CMD_SDRAM | \
CMD_USB)
/* POST support */
#define CONFIG_POST (CFG_POST_MEMORY | \
CFG_POST_CPU | \
CFG_POST_UART | \
CFG_POST_I2C | \
CFG_POST_SPR)
#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
#define CONFIG_LOGBUFFER
#define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
#define CONFIG_SUPPORT_VFAT
/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
@ -371,7 +384,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT

8
include/configs/stxgp3.h
View File

@ -230,10 +230,10 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#undef CONFIG_MPS85XX_FEC
#define TSEC1_PHY_ADDR 2

8
include/configs/stxssa.h
View File

@ -256,10 +256,10 @@
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_MPC85XX_TSEC1 1
#define CONFIG_MPC85XX_TSEC1_NAME "TSEC0"
#define CONFIG_MPC85XX_TSEC2 1
#define CONFIG_MPC85XX_TSEC2_NAME "TSEC1"
#define CONFIG_TSEC1 1
#define CONFIG_TSEC1_NAME "TSEC0"
#define CONFIG_TSEC2 1
#define CONFIG_TSEC2_NAME "TSEC1"
#undef CONFIG_MPS85XX_FEC
#define TSEC1_PHY_ADDR 2

5
include/configs/taishan.h
View File

@ -218,8 +218,8 @@
#define CONFIG_EMAC_NR_START 2 /* start with EMAC 2 (skip 0&1) */
#define CONFIG_MII 1 /* MII PHY management */
#define CONFIG_NET_MULTI 1
#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
#define CONFIG_PHY2_ADDR 0x1
#define CONFIG_PHY3_ADDR 0x3
#define CONFIG_ET1011C_PHY 1
@ -298,7 +298,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE */
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT /* let board init pci target */
#define CFG_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */

3
include/configs/yosemite.h
View File

@ -123,7 +123,7 @@
#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
#ifdef CFG_ENV_IS_IN_FLASH
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
@ -312,7 +312,6 @@
#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
/* Board-specific PCI */
#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */
#define CFG_PCI_TARGET_INIT
#define CFG_PCI_MASTER_INIT

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