ppc4xx: Add AMCC Canyonlands support (460EX) (1/3)

This patch adds support for the AMCC Canyonlands 460EX evaluation
board.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2008-03-11 16:51:17 +01:00
parent 43c60992cd
commit 8e1a3fe545
6 changed files with 915 additions and 0 deletions

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#
# (C) Copyright 2008
# Stefan Roese, DENX Software Engineering, sr@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
include $(TOPDIR)/config.mk
LIB = $(obj)lib$(BOARD).a
COBJS := $(BOARD).o
COBJS += bootstrap.o
SOBJS := init.o
SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c)
OBJS := $(addprefix $(obj),$(COBJS))
SOBJS := $(addprefix $(obj),$(SOBJS))
$(LIB): $(OBJS) $(SOBJS)
$(AR) $(ARFLAGS) $@ $(OBJS)
clean:
rm -f $(SOBJS) $(OBJS)
distclean: clean
rm -f $(LIB) core *.bak .depend
#########################################################################
# defines $(obj).depend target
include $(SRCTREE)/rules.mk
sinclude $(obj).depend
#########################################################################

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/*
* (C) Copyright 2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*
*/
#include <common.h>
#include <command.h>
#include <i2c.h>
#include <asm/io.h>
/*
* NOR and NAND boot options change bytes 6, 7, 8, 9, 11. The
* values are independent of the rest of the clock settings.
*/
#define NAND_COMPATIBLE 0x01
#define NOR_COMPATIBLE 0x02
#define I2C_EEPROM_ADDR 0x52
static char *config_labels[] = {
"CPU: 600 PLB: 200 OPB: 100 EBC: 100",
"CPU: 800 PLB: 200 OPB: 100 EBC: 100",
NULL
};
static u8 boot_configs[][17] = {
{
(NOR_COMPATIBLE),
0x86, 0x80, 0xce, 0x1f, 0x79, 0x80, 0x00, 0xa0, 0x40, 0x08,
0x23, 0x50, 0x0d, 0x95, 0x00, 0x00
},
{
(NOR_COMPATIBLE),
0x86, 0x80, 0xba, 0x14, 0x99, 0x80, 0x00, 0xa0, 0x40, 0x08,
0x23, 0x50, 0x0d, 0x95, 0x00, 0x00
},
{
0,
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
}
};
/*
* Bytes 6,8,9,11 change for NAND boot
*/
static u8 nand_boot[] = {
0xd0, 0xa0, 0x68, 0x58
};
static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
{
u8 *buf, b_nand;
int x, y, nbytes, selcfg;
extern char console_buffer[];
if (argc < 2) {
printf("Usage:\n%s\n", cmdtp->usage);
return 1;
}
if ((strcmp(argv[1], "nor") != 0) &&
(strcmp(argv[1], "nand") != 0)) {
printf("Unsupported boot-device - only nor|nand support\n");
return 1;
}
/* set the nand flag based on provided input */
if ((strcmp(argv[1], "nand") == 0))
b_nand = 1;
else
b_nand = 0;
printf("Available configurations: \n\n");
if (b_nand) {
for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
/* filter on nand compatible */
if (boot_configs[x][0] & NAND_COMPATIBLE) {
printf(" %d - %s\n", (y+1), config_labels[x]);
y++;
}
}
} else {
for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
/* filter on nor compatible */
if (boot_configs[x][0] & NOR_COMPATIBLE) {
printf(" %d - %s\n", (y+1), config_labels[x]);
y++;
}
}
}
do {
nbytes = readline(" Selection [1-x / quit]: ");
if (nbytes) {
if (strcmp(console_buffer, "quit") == 0)
return 0;
selcfg = simple_strtol(console_buffer, NULL, 10);
if ((selcfg < 1) || (selcfg > y))
nbytes = 0;
}
} while (nbytes == 0);
y = (selcfg - 1);
for (x = 0; boot_configs[x][0] != 0; x++) {
if (b_nand) {
if (boot_configs[x][0] & NAND_COMPATIBLE) {
if (y > 0)
y--;
else if (y < 1)
break;
}
} else {
if (boot_configs[x][0] & NOR_COMPATIBLE) {
if (y > 0)
y--;
else if (y < 1)
break;
}
}
}
buf = &boot_configs[x][1];
if (b_nand) {
buf[6] = nand_boot[0];
buf[8] = nand_boot[1];
buf[9] = nand_boot[2];
buf[11] = nand_boot[3];
}
if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0)
printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR);
udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
printf("Done\n");
printf("Please power-cycle the board for the changes to take effect\n");
return 0;
}
U_BOOT_CMD(
bootstrap, 2, 0, do_bootstrap,
"bootstrap - program the I2C bootstrap EEPROM\n",
"<nand|nor> - strap to boot from NAND or NOR flash\n"
);

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/*
* (C) Copyright 2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <common.h>
#include <ppc440.h>
#include <libfdt.h>
#include <fdt_support.h>
#include <asm/processor.h>
#include <asm/io.h>
#include <asm/mmu.h>
#include <asm/4xx_pcie.h>
extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
u32 sdr0_cust0;
/*------------------------------------------------------------------+
* Setup the interrupt controller polarities, triggers, etc.
*------------------------------------------------------------------*/
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic0er, 0x00000000); /* disable all */
mtdcr(uic0cr, 0x00000005); /* ATI & UIC1 crit are critical */
mtdcr(uic0pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic0tr, 0x00000000); /* per ref-board manual */
mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic0sr, 0xffffffff); /* clear all */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic1er, 0x00000000); /* disable all */
mtdcr(uic1cr, 0x00000000); /* all non-critical */
mtdcr(uic1pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic1tr, 0x00000000); /* per ref-board manual */
mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic1sr, 0xffffffff); /* clear all */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(uic2er, 0x00000000); /* disable all */
mtdcr(uic2cr, 0x00000000); /* all non-critical */
mtdcr(uic2pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic2tr, 0x00000000); /* per ref-board manual */
mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic2sr, 0xffffffff); /* clear all */
mtdcr(uic3sr, 0xffffffff); /* clear all */
mtdcr(uic3er, 0x00000000); /* disable all */
mtdcr(uic3cr, 0x00000000); /* all non-critical */
mtdcr(uic3pr, 0xffffffff); /* per ref-board manual */
mtdcr(uic3tr, 0x00000000); /* per ref-board manual */
mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
mtdcr(uic3sr, 0xffffffff); /* clear all */
/* SDR Setting - enable NDFC */
mfsdr(SDR0_CUST0, sdr0_cust0);
sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL |
SDR0_CUST0_NDFC_ENABLE |
SDR0_CUST0_NDFC_BW_8_BIT |
SDR0_CUST0_NDFC_ARE_MASK |
SDR0_CUST0_NDFC_BAC_ENCODE(3) |
(0x80000000 >> (28 + CFG_NAND_CS));
mtsdr(SDR0_CUST0, sdr0_cust0);
/*
* Configure PFC (Pin Function Control) registers
* UART0: 4 pins
*/
mtsdr(SDR0_PFC1, 0x00040000);
/* Enable PCI host functionality in SDR0_PCI0 */
mtsdr(SDR0_PCI0, 0xe0000000);
/* Enable ethernet and take out of reset */
out_8((void *)CFG_BCSR_BASE + 6, 0);
/* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
out_8((void *)CFG_BCSR_BASE + 5, 0);
/* Enable USB host & USB-OTG */
out_8((void *)CFG_BCSR_BASE + 7, 0);
mtsdr(SDR0_SRST1, 0); /* Pull AHB out of reset default=1 */
return 0;
}
int checkboard (void)
{
char *s = getenv("serial#");
u32 pvr = get_pvr();
if ((pvr == PVR_460GT_RA) || (pvr == PVR_460GT_SE_RA))
printf("Board: Glacier - AMCC PPC460GT Evaluation Board");
else
printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
if (s != NULL) {
puts(", serial# ");
puts(s);
}
putc('\n');
return (0);
}
/*
* Override the default functions in cpu/ppc4xx/44x_spd_ddr2.c with
* board specific values.
*/
u32 ddr_wrdtr(u32 default_val) {
return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823);
}
u32 ddr_clktr(u32 default_val) {
return (SDRAM_CLKTR_CLKP_90_DEG_ADV);
}
#if defined(CFG_DRAM_TEST)
int testdram(void)
{
unsigned long *mem = (unsigned long *)0;
const unsigned long kend = (1024 / sizeof(unsigned long));
unsigned long k, n;
mtmsr(0);
for (k = 0; k < CFG_KBYTES_SDRAM;
++k, mem += (1024 / sizeof(unsigned long))) {
if ((k & 1023) == 0) {
printf("%3d MB\r", k / 1024);
}
memset(mem, 0xaaaaaaaa, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0xaaaaaaaa) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
memset(mem, 0x55555555, 1024);
for (n = 0; n < kend; ++n) {
if (mem[n] != 0x55555555) {
printf("SDRAM test fails at: %08x\n",
(uint) & mem[n]);
return 1;
}
}
}
printf("SDRAM test passes\n");
return 0;
}
#endif
/*************************************************************************
* pci_target_init
*
* The bootstrap configuration provides default settings for the pci
* inbound map (PIM). But the bootstrap config choices are limited and
* may not be sufficient for a given board.
*
************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller * hose )
{
/*-------------------------------------------------------------------+
* Disable everything
*-------------------------------------------------------------------*/
out_le32((void *)PCIX0_PIM0SA, 0); /* disable */
out_le32((void *)PCIX0_PIM1SA, 0); /* disable */
out_le32((void *)PCIX0_PIM2SA, 0); /* disable */
out_le32((void *)PCIX0_EROMBA, 0); /* disable expansion rom */
/*-------------------------------------------------------------------+
* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
* strapping options to not support sizes such as 128/256 MB.
*-------------------------------------------------------------------*/
out_le32((void *)PCIX0_PIM0LAL, CFG_SDRAM_BASE);
out_le32((void *)PCIX0_PIM0LAH, 0);
out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
out_le32((void *)PCIX0_BAR0, 0);
/*-------------------------------------------------------------------+
* Program the board's subsystem id/vendor id
*-------------------------------------------------------------------*/
out_le16((void *)PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
out_le16((void *)PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
}
#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
#if defined(CONFIG_PCI)
/*
* is_pci_host
*
* This routine is called to determine if a pci scan should be
* performed. With various hardware environments (especially cPCI and
* PPMC) it's insufficient to depend on the state of the arbiter enable
* bit in the strap register, or generic host/adapter assumptions.
*
* Rather than hard-code a bad assumption in the general 440 code, the
* 440 pci code requires the board to decide at runtime.
*
* Return 0 for adapter mode, non-zero for host (monarch) mode.
*/
int is_pci_host(struct pci_controller *hose)
{
/* Board is always configured as host. */
return (1);
}
static struct pci_controller pcie_hose[2] = {{0},{0}};
void pcie_setup_hoses(int busno)
{
struct pci_controller *hose;
int i, bus;
int ret = 0;
char *env;
unsigned int delay;
/*
* assume we're called after the PCIX hose is initialized, which takes
* bus ID 0 and therefore start numbering PCIe's from 1.
*/
bus = busno;
for (i = 0; i <= 1; i++) {
if (is_end_point(i))
ret = ppc4xx_init_pcie_endport(i);
else
ret = ppc4xx_init_pcie_rootport(i);
if (ret) {
printf("PCIE%d: initialization as %s failed\n", i,
is_end_point(i) ? "endpoint" : "root-complex");
continue;
}
hose = &pcie_hose[i];
hose->first_busno = bus;
hose->last_busno = bus;
hose->current_busno = bus;
/* setup mem resource */
pci_set_region(hose->regions + 0,
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
CFG_PCIE_MEMSIZE,
PCI_REGION_MEM);
hose->region_count = 1;
pci_register_hose(hose);
if (is_end_point(i)) {
ppc4xx_setup_pcie_endpoint(hose, i);
/*
* Reson for no scanning is endpoint can not generate
* upstream configuration accesses.
*/
} else {
ppc4xx_setup_pcie_rootpoint(hose, i);
env = getenv ("pciscandelay");
if (env != NULL) {
delay = simple_strtoul(env, NULL, 10);
if (delay > 5)
printf("Warning, expect noticable delay before "
"PCIe scan due to 'pciscandelay' value!\n");
mdelay(delay * 1000);
}
/*
* Config access can only go down stream
*/
hose->last_busno = pci_hose_scan(hose);
bus = hose->last_busno + 1;
}
}
}
#endif /* CONFIG_PCI */
int board_early_init_r (void)
{
/*
* Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
* boot EBC mapping only supports a maximum of 16MBytes
* (4.ff00.0000 - 4.ffff.ffff).
* To solve this problem, the FLASH has to get remapped to another
* EBC address which accepts bigger regions:
*
* 0xfc00.0000 -> 4.cc00.0000
*
* For this we have to remap the CS0 and re-relocate the envrironment,
* since the original FLASH location which was needed upon startup is
* now not correct anymore.
*/
/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
mtebc(pb0cr, CFG_FLASH_BASE_PHYS_L | 0xda000);
/* Remove TLB entry of boot EBC mapping */
remove_tlb(CFG_BOOT_BASE_ADDR, 16 << 20);
/* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
program_tlb(CFG_FLASH_BASE_PHYS, CFG_FLASH_BASE, CFG_FLASH_SIZE,
TLB_WORD2_I_ENABLE);
/*
* Now accessing of the whole 64Mbytes of NOR FLASH at virtual address
* 0xfc00.0000 is possible
*/
return 0;
}
int misc_init_r(void)
{
u32 sdr0_srst1 = 0;
u32 eth_cfg;
/*
* Set EMAC mode/configuration (GMII, SGMII, RGMII...).
* This is board specific, so let's do it here.
*/
mfsdr(SDR0_ETH_CFG, eth_cfg);
/* disable SGMII mode */
eth_cfg &= ~(SDR0_ETH_CFG_SGMII2_ENABLE |
SDR0_ETH_CFG_SGMII1_ENABLE |
SDR0_ETH_CFG_SGMII0_ENABLE);
/* Set the for 2 RGMII mode */
/* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
eth_cfg &= ~SDR0_ETH_CFG_GMC0_BRIDGE_SEL;
eth_cfg |= SDR0_ETH_CFG_GMC1_BRIDGE_SEL;
mtsdr(SDR0_ETH_CFG, eth_cfg);
/*
* The AHB Bridge core is held in reset after power-on or reset
* so enable it now
*/
mfsdr(SDR0_SRST1, sdr0_srst1);
sdr0_srst1 &= ~SDR0_SRST1_AHB;
mtsdr(SDR0_SRST1, sdr0_srst1);
return 0;
}
#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
void ft_board_setup(void *blob, bd_t *bd)
{
u32 val[4];
int rc;
ft_cpu_setup(blob, bd);
/* Fixup NOR mapping */
val[0] = 0; /* chip select number */
val[1] = 0; /* always 0 */
val[2] = gd->bd->bi_flashstart;
val[3] = gd->bd->bi_flashsize;
rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
val, sizeof(val), 1);
if (rc)
printf("Unable to update property NOR mapping, err=%s\n",
fdt_strerror(rc));
}
#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */

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#
# (C) Copyright 2008
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
#
# See file CREDITS for list of people who contributed to this
# project.
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; either version 2 of
# the License, or (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
# MA 02111-1307 USA
#
#
# AMCC 460EX/460GT Evaluation Board (Canyonlands) board
#
sinclude $(TOPDIR)/board/$(BOARDDIR)/config.tmp
ifndef TEXT_BASE
TEXT_BASE = 0xFFFA0000
endif
ifeq ($(CONFIG_NAND_U_BOOT),y)
LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
endif
ifeq ($(CONFIG_PCIBOOT_U_BOOT),y)
LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds
endif
PLATFORM_CPPFLAGS += -DCONFIG_440=1
ifeq ($(debug),1)
PLATFORM_CPPFLAGS += -DDEBUG
endif
ifeq ($(dbcr),1)
PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
endif

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/*
* (C) Copyright 2008
* Stefan Roese, DENX Software Engineering, sr@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
#include <ppc_asm.tmpl>
#include <config.h>
#include <asm-ppc/mmu.h>
/**************************************************************************
* TLB TABLE
*
* This table is used by the cpu boot code to setup the initial tlb
* entries. Rather than make broad assumptions in the cpu source tree,
* this table lets each board set things up however they like.
*
* Pointer to the table is returned in r1
*
*************************************************************************/
.section .bootpg,"ax"
.globl tlbtab
tlbtab:
tlbtab_start
/*
* BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to
* use the speed up boot process. It is patched after relocation to
* enable SA_I
*/
tlbentry(CFG_BOOT_BASE_ADDR, SZ_16M, CFG_BOOT_BASE_ADDR, 4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */
/*
* TLB entries for SDRAM are not needed on this platform.
* They are dynamically generated in the SPD DDR(2) detection
* routine.
*/
#ifdef CFG_INIT_RAM_DCACHE
/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
#endif
tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
/* PCIe UTL register */
tlbentry(CFG_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_R|AC_W|SA_G|SA_I)
/* TLB-entry for NAND */
tlbentry(CFG_NAND_ADDR, SZ_16M, CFG_NAND_ADDR, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
/* TLB-entry for CPLD */
tlbentry(CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 4, AC_R|AC_W|SA_G|SA_I)
/* TLB-entry for OCM */
tlbentry(CFG_OCM_BASE, SZ_4K, 0x00040000, 4, AC_R|AC_W|AC_X)
/* TLB-entry for Local Configuration registers => peripherals */
tlbentry(CFG_LOCAL_CONF_REGS, SZ_16M, CFG_LOCAL_CONF_REGS, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
tlbtab_end
#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
/*
* For NAND booting the first TLB has to be reconfigured to full size
* and with caching disabled after running from RAM!
*/
#define TLB00 TLB0(CFG_BOOT_BASE_ADDR, SZ_256M)
#define TLB01 TLB1(CFG_BOOT_BASE_ADDR, 1)
#define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
.globl reconfig_tlb0
reconfig_tlb0:
sync
isync
addi r4,r0,0x0000 /* TLB entry #0 */
lis r5,TLB00@h
ori r5,r5,TLB00@l
tlbwe r5,r4,0x0000 /* Save it out */
lis r5,TLB01@h
ori r5,r5,TLB01@l
tlbwe r5,r4,0x0001 /* Save it out */
lis r5,TLB02@h
ori r5,r5,TLB02@l
tlbwe r5,r4,0x0002 /* Save it out */
sync
isync
blr
#endif

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@ -0,0 +1,146 @@
/*
* (C) Copyright 2008
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
OUTPUT_ARCH(powerpc)
SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib);
/* Do we need any of these for elf?
__DYNAMIC = 0; */
SECTIONS
{
.resetvec 0xFFFFFFFC :
{
*(.resetvec)
} = 0xffff
.bootpg 0xFFFFF000 :
{
cpu/ppc4xx/start.o (.bootpg)
} = 0xffff
/* Read-only sections, merged into text segment: */
. = + SIZEOF_HEADERS;
.interp : { *(.interp) }
.hash : { *(.hash) }
.dynsym : { *(.dynsym) }
.dynstr : { *(.dynstr) }
.rel.text : { *(.rel.text) }
.rela.text : { *(.rela.text) }
.rel.data : { *(.rel.data) }
.rela.data : { *(.rela.data) }
.rel.rodata : { *(.rel.rodata) }
.rela.rodata : { *(.rela.rodata) }
.rel.got : { *(.rel.got) }
.rela.got : { *(.rela.got) }
.rel.ctors : { *(.rel.ctors) }
.rela.ctors : { *(.rela.ctors) }
.rel.dtors : { *(.rel.dtors) }
.rela.dtors : { *(.rela.dtors) }
.rel.bss : { *(.rel.bss) }
.rela.bss : { *(.rela.bss) }
.rel.plt : { *(.rel.plt) }
.rela.plt : { *(.rela.plt) }
.init : { *(.init) }
.plt : { *(.plt) }
.text :
{
/* WARNING - the following is hand-optimized to fit within */
/* the sector layout of our flash chips! XXX FIXME XXX */
cpu/ppc4xx/start.o (.text)
board/amcc/canyonlands/init.o (.text)
*(.text)
*(.fixup)
*(.got1)
}
_etext = .;
PROVIDE (etext = .);
.rodata :
{
*(.rodata)
*(.rodata1)
*(.rodata.str1.4)
}
.fini : { *(.fini) } =0
.ctors : { *(.ctors) }
.dtors : { *(.dtors) }
/* Read-write section, merged into data segment: */
. = (. + 0x00FF) & 0xFFFFFF00;
_erotext = .;
PROVIDE (erotext = .);
.reloc :
{
*(.got)
_GOT2_TABLE_ = .;
*(.got2)
_FIXUP_TABLE_ = .;
*(.fixup)
}
__got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
__fixup_entries = (. - _FIXUP_TABLE_)>>2;
.data :
{
*(.data)
*(.data1)
*(.sdata)
*(.sdata2)
*(.dynamic)
CONSTRUCTORS
}
_edata = .;
PROVIDE (edata = .);
. = .;
__u_boot_cmd_start = .;
.u_boot_cmd : { *(.u_boot_cmd) }
__u_boot_cmd_end = .;
. = .;
__start___ex_table = .;
__ex_table : { *(__ex_table) }
__stop___ex_table = .;
. = ALIGN(256);
__init_begin = .;
.text.init : { *(.text.init) }
.data.init : { *(.data.init) }
. = ALIGN(256);
__init_end = .;
__bss_start = .;
.bss :
{
*(.sbss) *(.scommon)
*(.dynbss)
*(.bss)
*(COMMON)
}
ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
_end = . ;
PROVIDE (end = .);
}