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mpc83xx: cosmetic: MPC837XEMDS.h checkpatch compliance

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Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Joe Hershberger 2011-10-11 23:57:18 -05:00 committed by Kim Phillips
parent 9a9865508f
commit 8d85808fa1
1 changed files with 166 additions and 117 deletions
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183
include/configs/MPC837XEMDS.h
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@ -146,44 +146,45 @@
*/ */
#define CONFIG_SYS_DDR_SIZE 512 /* MB */ #define CONFIG_SYS_DDR_SIZE 512 /* MB */
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f #define CONFIG_SYS_DDR_CS0_BNDS 0x0000001f
#define CONFIG_SYS_DDR_CS0_CONFIG ( CSCONFIG_EN \ #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
| 0x00010000 /* ODT_WR to CSn */ \ | 0x00010000 /* ODT_WR to CSn */ \
| CSCONFIG_ROW_BIT_14 | CSCONFIG_COL_BIT_10 ) | CSCONFIG_ROW_BIT_14 \
| CSCONFIG_COL_BIT_10)
/* 0x80010202 */ /* 0x80010202 */
#define CONFIG_SYS_DDR_TIMING_3 0x00000000 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
#define CONFIG_SYS_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
| ( 0 << TIMING_CFG0_WRT_SHIFT ) \ | (0 << TIMING_CFG0_WRT_SHIFT) \
| ( 0 << TIMING_CFG0_RRT_SHIFT ) \ | (0 << TIMING_CFG0_RRT_SHIFT) \
| ( 0 << TIMING_CFG0_WWT_SHIFT ) \ | (0 << TIMING_CFG0_WWT_SHIFT) \
| ( 6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT ) \ | (6 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
| ( 2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT ) \ | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
| ( 8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT ) \ | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
| ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
/* 0x00620802 */ /* 0x00620802 */
#define CONFIG_SYS_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ #define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
| ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
| ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
| ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ | (5 << TIMING_CFG1_CASLAT_SHIFT) \
| (13 << TIMING_CFG1_REFREC_SHIFT ) \ | (13 << TIMING_CFG1_REFREC_SHIFT) \
| ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ | (3 << TIMING_CFG1_WRREC_SHIFT) \
| ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
| ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) | (2 << TIMING_CFG1_WRTORD_SHIFT))
/* 0x3935d322 */ /* 0x3935d322 */
#define CONFIG_SYS_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ #define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \
| ( 6 << TIMING_CFG2_CPO_SHIFT ) \ | (6 << TIMING_CFG2_CPO_SHIFT) \
| ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
| ( 4 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ | (4 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
| ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
| ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
| ( 8 << TIMING_CFG2_FOUR_ACT_SHIFT) ) | (8 << TIMING_CFG2_FOUR_ACT_SHIFT))
/* 0x131088c8 */ /* 0x131088c8 */
#define CONFIG_SYS_DDR_INTERVAL ( ( 0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT ) \ #define CONFIG_SYS_DDR_INTERVAL ((0x03E0 << SDRAM_INTERVAL_REFINT_SHIFT) \
| ( 0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
/* 0x03E00100 */ /* 0x03E00100 */
#define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000 #define CONFIG_SYS_DDR_SDRAM_CFG 0x43000000
#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
#define CONFIG_SYS_DDR_MODE ( ( 0x0448 << SDRAM_MODE_ESD_SHIFT ) \ #define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \
| ( 0x1432 << SDRAM_MODE_SD_SHIFT ) ) | (0x1432 << SDRAM_MODE_SD_SHIFT))
/* ODT 150ohm CL=3, AL=1 on SDRAM */ /* ODT 150ohm CL=3, AL=1 on SDRAM */
#define CONFIG_SYS_DDR_MODE2 0x00000000 #define CONFIG_SYS_DDR_MODE2 0x00000000
#endif #endif
@ -216,7 +217,8 @@
#define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
/* /*
* Local Bus Configuration & Clock Setup * Local Bus Configuration & Clock Setup
@ -235,13 +237,14 @@
#define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */ #define CONFIG_SYS_FLASH_SIZE 32 /* max FLASH size is 32M */
#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */ /* Window base at flash base */
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ #define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */
#define CONFIG_SYS_BR0_PRELIM ( CONFIG_SYS_FLASH_BASE /* Flash Base address */ \ #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
| (2 << BR_PS_SHIFT) /* 16 bit port size */ \ | (2 << BR_PS_SHIFT) /* 16 bit port */ \
| BR_V ) /* valid */ | BR_V) /* valid */
#define CONFIG_SYS_OR0_PRELIM ( (~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ #define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
| OR_UPM_XAM \ | OR_UPM_XAM \
| OR_GPCM_CSNT \ | OR_GPCM_CSNT \
| OR_GPCM_ACS_DIV2 \ | OR_GPCM_ACS_DIV2 \
@ -249,7 +252,7 @@
| OR_GPCM_SCY_15 \ | OR_GPCM_SCY_15 \
| OR_GPCM_TRLX \ | OR_GPCM_TRLX \
| OR_GPCM_EHTR \ | OR_GPCM_EHTR \
| OR_GPCM_EAD ) | OR_GPCM_EAD)
/* 0xFE000FF7 */ /* 0xFE000FF7 */
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
@ -263,10 +266,12 @@
* BCSR on the Local Bus * BCSR on the Local Bus
*/ */
#define CONFIG_SYS_BCSR 0xF8000000 #define CONFIG_SYS_BCSR 0xF8000000
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR /* Access window base at BCSR base */ /* Access window base at BCSR base */
#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_BCSR
#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */ #define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* Access window size 32K */
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00000801) /* Port size=8bit, MSEL=GPCM */ /* Port size=8bit, MSEL=GPCM */
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_BCSR | 0x00000801)
#define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */ #define CONFIG_SYS_OR1_PRELIM 0xFFFFE9f7 /* length 32K */
/* /*
@ -278,19 +283,19 @@
#define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_NAND_FSL_ELBC 1
#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */ #define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
#define CONFIG_SYS_BR3_PRELIM ( CONFIG_SYS_NAND_BASE \ #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE \
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \ | BR_PS_8 /* 8 bit port */ \
| BR_MS_FCM /* MSEL = FCM */ \ | BR_MS_FCM /* MSEL = FCM */ \
| BR_V ) /* valid */ | BR_V) /* valid */
#define CONFIG_SYS_OR3_PRELIM ( 0xFFFF8000 /* length 32K */ \ #define CONFIG_SYS_OR3_PRELIM (0xFFFF8000 /* length 32K */ \
| OR_FCM_BCTLD \ | OR_FCM_BCTLD \
| OR_FCM_CST \ | OR_FCM_CST \
| OR_FCM_CHT \ | OR_FCM_CHT \
| OR_FCM_SCY_1 \ | OR_FCM_SCY_1 \
| OR_FCM_RST \ | OR_FCM_RST \
| OR_FCM_TRLX \ | OR_FCM_TRLX \
| OR_FCM_EHTR ) | OR_FCM_EHTR)
/* 0xFFFF919E */ /* 0xFFFF919E */
#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_NAND_BASE
@ -454,7 +459,8 @@ extern int board_pci_host_broken(void);
*/ */
#ifndef CONFIG_SYS_RAMBOOT #ifndef CONFIG_SYS_RAMBOOT
#define CONFIG_ENV_IS_IN_FLASH 1 #define CONFIG_ENV_IS_IN_FLASH 1
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) #define CONFIG_ENV_ADDR \
(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
#define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SIZE 0x2000
#else #else
@ -526,9 +532,11 @@ extern int board_pci_host_broken(void);
#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
#endif #endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ /* Print Buffer Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ /* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
/* /*
@ -555,53 +563,93 @@ extern int board_pci_host_broken(void);
#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) #define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP) | BATL_PP_10 \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP) | BATL_PP_10 \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_10 | \ #define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | BATL_PP_10 \
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP) | BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \
| BATU_BL_8M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
/* BCSR: cache-inhibit and guarded */ /* BCSR: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR | BATL_PP_10 | \ #define CONFIG_SYS_IBAT3L (CONFIG_SYS_BCSR \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | BATL_PP_10 \
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR | BATU_BL_128K | BATU_VS | BATU_VP) | BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT3U (CONFIG_SYS_BCSR \
| BATU_BL_128K \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
/* FLASH: icache cacheable, but dcache-inhibit and guarded */ /* FLASH: icache cacheable, but dcache-inhibit and guarded */
#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \
#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP) | BATL_PP_10 \
#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ | BATL_MEMCOHERENCE)
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \
| BATU_BL_32M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \
| BATL_PP_10 \
| BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
/* Stack in dcache: cacheable, no memory coherence */ /* Stack in dcache: cacheable, no memory coherence */
#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) #define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \
| BATU_BL_128K \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
#ifdef CONFIG_PCI #ifdef CONFIG_PCI
/* PCI MEM space: cacheable */ /* PCI MEM space: cacheable */
#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) | BATL_PP_10 \
| BATL_MEMCOHERENCE)
#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L #define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
/* PCI MMIO space: cache-inhibit and guarded */ /* PCI MMIO space: cache-inhibit and guarded */
#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \ #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \
BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) | BATL_PP_10 \
#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP) | BATL_CACHEINHIBIT \
| BATL_GUARDEDSTORAGE)
#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \
| BATU_BL_256M \
| BATU_VS \
| BATU_VP)
#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
#else #else
@ -650,7 +698,8 @@ extern int board_pci_host_broken(void);
#define CONFIG_NFSBOOTCOMMAND \ #define CONFIG_NFSBOOTCOMMAND \
"setenv bootargs root=/dev/nfs rw " \ "setenv bootargs root=/dev/nfs rw " \
"nfsroot=$serverip:$rootpath " \ "nfsroot=$serverip:$rootpath " \
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
"$netdev:off " \
"console=$consoledev,$baudrate $othbootargs;" \ "console=$consoledev,$baudrate $othbootargs;" \
"tftp $loadaddr $bootfile;" \ "tftp $loadaddr $bootfile;" \
"tftp $fdtaddr $fdtfile;" \ "tftp $fdtaddr $fdtfile;" \