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https://github.com/brain-hackers/u-boot-brain
synced 2024-06-09 23:36:03 +09:00
clk: stm32mp1: add debug information
Add support of clk dump command and display information during probe (under CONFIG_DISPLAY_CPUINFO). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
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@ -19,6 +19,7 @@ CONFIG_SYS_PROMPT="STM32MP> "
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# CONFIG_CMD_IMPORTENV is not set
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# CONFIG_CMD_IMPORTENV is not set
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CONFIG_CMD_MEMINFO=y
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CONFIG_CMD_MEMINFO=y
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CONFIG_CMD_ADC=y
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CONFIG_CMD_ADC=y
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CONFIG_CMD_CLK=y
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CONFIG_CMD_FUSE=y
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CONFIG_CMD_FUSE=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_GPIO=y
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CONFIG_CMD_GPT=y
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CONFIG_CMD_GPT=y
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@ -666,8 +666,8 @@ static const u8 stm32mp1_axi_div[8] = {
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1, 2, 3, 4, 4, 4, 4, 4
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1, 2, 3, 4, 4, 4, 4, 4
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};
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};
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#ifdef DEBUG
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static const __maybe_unused
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static const char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
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char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
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[_HSI] = "HSI",
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[_HSI] = "HSI",
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[_HSE] = "HSE",
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[_HSE] = "HSE",
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[_CSI] = "CSI",
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[_CSI] = "CSI",
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@ -705,7 +705,8 @@ static const char * const stm32mp1_clk_parent_name[_PARENT_NB] = {
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[_DSI_PHY] = "DSI_PHY_PLL",
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[_DSI_PHY] = "DSI_PHY_PLL",
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};
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};
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static const char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
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static const __maybe_unused
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char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
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[_I2C12_SEL] = "I2C12",
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[_I2C12_SEL] = "I2C12",
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[_I2C35_SEL] = "I2C35",
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[_I2C35_SEL] = "I2C35",
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[_I2C46_SEL] = "I2C46",
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[_I2C46_SEL] = "I2C46",
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@ -724,7 +725,6 @@ static const char * const stm32mp1_clk_parent_sel_name[_PARENT_SEL_NB] = {
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[_DSI_SEL] = "DSI",
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[_DSI_SEL] = "DSI",
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[_ADC12_SEL] = "ADC12",
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[_ADC12_SEL] = "ADC12",
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};
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};
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#endif
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static const struct stm32mp1_clk_data stm32mp1_data = {
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static const struct stm32mp1_clk_data stm32mp1_data = {
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.gate = stm32mp1_clk_gate,
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.gate = stm32mp1_clk_gate,
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@ -1870,6 +1870,54 @@ static void stm32mp1_osc_init(struct udevice *dev)
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}
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}
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}
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}
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static void __maybe_unused stm32mp1_clk_dump(struct stm32mp1_clk_priv *priv)
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{
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char buf[32];
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int i, s, p;
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printf("Clocks:\n");
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for (i = 0; i < _PARENT_NB; i++) {
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printf("- %s : %s MHz\n",
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stm32mp1_clk_parent_name[i],
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strmhz(buf, stm32mp1_clk_get(priv, i)));
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}
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printf("Source Clocks:\n");
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for (i = 0; i < _PARENT_SEL_NB; i++) {
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p = (readl(priv->base + priv->data->sel[i].offset) >>
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priv->data->sel[i].src) & priv->data->sel[i].msk;
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if (p < priv->data->sel[i].nb_parent) {
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s = priv->data->sel[i].parent[p];
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printf("- %s(%d) => parent %s(%d)\n",
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stm32mp1_clk_parent_sel_name[i], i,
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stm32mp1_clk_parent_name[s], s);
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} else {
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printf("- %s(%d) => parent index %d is invalid\n",
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stm32mp1_clk_parent_sel_name[i], i, p);
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}
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}
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}
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#ifdef CONFIG_CMD_CLK
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int soc_clk_dump(void)
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{
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struct udevice *dev;
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struct stm32mp1_clk_priv *priv;
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int ret;
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ret = uclass_get_device_by_driver(UCLASS_CLK,
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DM_GET_DRIVER(stm32mp1_clock),
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&dev);
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if (ret)
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return ret;
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priv = dev_get_priv(dev);
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stm32mp1_clk_dump(priv);
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return 0;
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}
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#endif
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static int stm32mp1_clk_probe(struct udevice *dev)
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static int stm32mp1_clk_probe(struct udevice *dev)
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{
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{
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int result = 0;
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int result = 0;
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@ -1893,6 +1941,33 @@ static int stm32mp1_clk_probe(struct udevice *dev)
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result = stm32mp1_clktree(dev);
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result = stm32mp1_clktree(dev);
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#endif
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#endif
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#ifndef CONFIG_SPL_BUILD
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#if defined(DEBUG)
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/* display debug information for probe after relocation */
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if (gd->flags & GD_FLG_RELOC)
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stm32mp1_clk_dump(priv);
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#endif
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#if defined(CONFIG_DISPLAY_CPUINFO)
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if (gd->flags & GD_FLG_RELOC) {
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char buf[32];
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printf("Clocks:\n");
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printf("- MPU : %s MHz\n",
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strmhz(buf, stm32mp1_clk_get(priv, _CK_MPU)));
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printf("- MCU : %s MHz\n",
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strmhz(buf, stm32mp1_clk_get(priv, _CK_MCU)));
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printf("- AXI : %s MHz\n",
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strmhz(buf, stm32mp1_clk_get(priv, _ACLK)));
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printf("- PER : %s MHz\n",
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strmhz(buf, stm32mp1_clk_get(priv, _CK_PER)));
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/* DDRPHYC father */
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printf("- DDR : %s MHz\n",
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strmhz(buf, stm32mp1_clk_get(priv, _PLL2_R)));
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}
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#endif /* CONFIG_DISPLAY_CPUINFO */
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#endif
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return result;
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return result;
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}
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}
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