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x86: Use consistent name XXX_ADDR for binary blob flash address

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Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
This commit is contained in:
Bin Meng 2014-12-17 15:50:42 +08:00 committed by Simon Glass
parent 405d8205d7
commit 8c5224c9f5
6 changed files with 7 additions and 7 deletions
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2
Makefile
View File

@ -958,7 +958,7 @@ IFDTOOL_ME_FLAGS += -i ME:$(srctree)/board/$(BOARDDIR)/me.bin
endif
ifneq ($(CONFIG_HAVE_MRC),)
IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_START):$(srctree)/board/$(BOARDDIR)/mrc.bin
IFDTOOL_FLAGS += -w $(CONFIG_X86_MRC_ADDR):$(srctree)/board/$(BOARDDIR)/mrc.bin
endif
ifneq ($(CONFIG_X86_OPTION_ROM_ADDR),)

2
arch/x86/cpu/ivybridge/sdram.c
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@ -177,7 +177,7 @@ int sdram_initialise(struct pei_data *pei_data)
debug("PEI data at %p, size %x:\n", pei_data, sizeof(*pei_data));
data = (char *)CONFIG_X86_MRC_START;
data = (char *)CONFIG_X86_MRC_ADDR;
if (data) {
int rv;
int (*func)(struct pei_data *);

4
arch/x86/cpu/queensbay/Kconfig
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@ -29,7 +29,7 @@ config FSP_FILE
The filename of the file to use as Firmware Support Package binary
in the board directory.
config FSP_LOCATION
config FSP_ADDR
hex "Firmware Support Package binary location"
depends on HAVE_FSP
default 0xfffc0000
@ -65,7 +65,7 @@ config CMC_FILE
The filename of the file to use as Chipset Micro Code state machine
binary in the board directory.
config CMC_LOCATION
config CMC_ADDR
hex "Chipset Micro Code state machine binary location"
depends on HAVE_CMC
default 0xfffb0000

2
arch/x86/cpu/queensbay/fsp_support.c
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@ -64,7 +64,7 @@ u32 __attribute__((optimize("O0"))) find_fsp_header(void)
volatile register u8 *fsp asm("eax");
/* Initalize the FSP base */
fsp = (u8 *)CONFIG_FSP_LOCATION;
fsp = (u8 *)CONFIG_FSP_ADDR;
/* Check the FV signature, _FVH */
if (((struct fv_header_t *)fsp)->sign == 0x4856465F) {

2
arch/x86/cpu/queensbay/tnc_car.S
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@ -29,7 +29,7 @@ find_fsp_header_ret:
mov %eax, %ebp
/* sanity test */
cmp $CONFIG_FSP_LOCATION, %eax
cmp $CONFIG_FSP_ADDR, %eax
jb die
/* calculate TempRamInitEntry address */

2
include/configs/chromebook_link.h
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@ -25,7 +25,7 @@
#define CONFIG_X86_RESET_VECTOR
#define CONFIG_NR_DRAM_BANKS 8
#define CONFIG_X86_MRC_START 0xfffa0000
#define CONFIG_X86_MRC_ADDR 0xfffa0000
#define CONFIG_CACHE_MRC_SIZE_KB 512
#define CONFIG_COREBOOT_SERIAL