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Code Issues Projects Releases Wiki Activity

Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvell

Browse Source 
- Espressobin: Disable slot when emmc is not present (Pali)
- DS414; config header cleanup (Phil)
- PCI: auto-config enhancement (Phil)
- pci_mvebu: Also map IO region (Phil)
- serial: a3720: Implement pending method for output direction (Pali)
- turris_mox: Enable a few commands (Marek)
- helios4 & ClearFog changes (Dennis)
- Plus some minor misc changes
This commit is contained in:
Tom Rini 2021-01-27 11:39:31 -05:00
commit 8b195f4b71
16 changed files with 143 additions and 48 deletions
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23
arch/arm/dts/armada-388-helios4-u-boot.dtsi
View File

@ -1,13 +1,5 @@
// SPDX-License-Identifier: GPL-2.0+
/ {
aliases {
i2c0 = &i2c0;
i2c1 = &i2c1;
spi1 = &spi1;
};
};
&eth0 {
phy-reset-gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
};
@ -20,7 +12,6 @@
};
&w25q32 {
status = "okay";
u-boot,dm-spl;
};
@ -37,5 +28,17 @@
};
&sdhci {
u-boot,dm-spl;
u-boot,dm-spl;
};
&i2c0 {
u-boot,dm-spl;
eeprom@52 {
u-boot,dm-spl;
};
eeprom@53 {
u-boot,dm-spl;
};
};

14
arch/arm/dts/armada-388-helios4.dts
View File

@ -22,10 +22,14 @@
};
aliases {
/* So that mvebu u-boot can update the MAC addresses */
/* So that mvebu u-boot can update the MAC address */
ethernet1 = &eth0;
spi1 = &spi1;
i2c0 = &i2c0;
i2c1 = &i2c1;
};
chosen {
stdout-path = "serial0:115200n8";
};
@ -306,3 +310,11 @@
};
};
};
&w25q32 {
status = "okay";
};
&spi1 {
status = "okay";
};

1
arch/arm/mach-mvebu/Kconfig
View File

@ -299,5 +299,6 @@ config SECURED_MODE_CSK_INDEX
depends on SECURED_MODE_IMAGE
source "board/solidrun/clearfog/Kconfig"
source "board/kobol/helios4/Kconfig"
endif

15
board/Marvell/mvebu_armada-37xx/board.c
View File

@ -5,6 +5,7 @@
#include <common.h>
#include <dm.h>
#include <dm/device-internal.h>
#include <env.h>
#include <i2c.h>
#include <init.h>
@ -84,12 +85,10 @@ int board_init(void)
#ifdef CONFIG_BOARD_LATE_INIT
int board_late_init(void)
{
struct udevice *dev;
struct mmc *mmc_dev;
bool ddr4, emmc;
if (env_get("fdtfile"))
return 0;
if (!of_machine_is_compatible("globalscale,espressobin"))
return 0;
@ -101,6 +100,16 @@ int board_late_init(void)
mmc_dev = find_mmc_device(1);
emmc = (mmc_dev && mmc_init(mmc_dev) == 0);
/* if eMMC is not present then remove it from DM */
if (!emmc && mmc_dev) {
dev = mmc_dev->dev;
device_remove(dev, DM_REMOVE_NORMAL);
device_unbind(dev);
}
if (env_get("fdtfile"))
return 0;
if (ddr4 && emmc)
env_set("fdtfile", "marvell/armada-3720-espressobin-v7-emmc.dtb");
else if (ddr4)

24
board/kobol/helios4/Kconfig Normal file
View File

@ -0,0 +1,24 @@
menu "Helios4 configuration"
depends on TARGET_HELIOS4
config ENV_SIZE
hex "Environment Size"
default 0x10000
config ENV_OFFSET
hex "Environment offset"
default 0xF0000
config ENV_SECT_SIZE
hex "Environment Sector-Size"
# Use SPI or SATA flash erase block size of 4 KiB
default 0x1000 if MVEBU_SPL_BOOT_DEVICE_SPI || MVEBU_SPL_BOOT_DEVICE_SATA
# Use optimistic 64 KiB erase block, will vary between actual media
default 0x10000 if MVEBU_SPL_BOOT_DEVICE_MMC || MVEBU_SPL_BOOT_DEVICE_UART
config SYS_SPI_U_BOOT_OFFS
hex "address of u-boot payload in SPI flash"
default 0x20000
depends on MVEBU_SPL_BOOT_DEVICE_SPI
endmenu

4
board/solidrun/clearfog/Kconfig
View File

@ -50,9 +50,9 @@ config ENV_OFFSET
config ENV_SECT_SIZE
hex "Environment Sector-Size"
# Use SPI flash erase block size of 4 KiB
default 0x1000 if MVEBU_SPL_BOOT_DEVICE_SPI
default 0x1000 if MVEBU_SPL_BOOT_DEVICE_SPI || MVEBU_SPL_BOOT_DEVICE_SATA
# Use optimistic 64 KiB erase block, will vary between actual media
default 0x10000 if MVEBU_SPL_BOOT_DEVICE_MMC
default 0x10000 if MVEBU_SPL_BOOT_DEVICE_MMC || MVEBU_SPL_BOOT_DEVICE_UART
config SYS_SPI_U_BOOT_OFFS
hex "address of u-boot payload in SPI flash"

2
configs/helios4_defconfig
View File

@ -9,8 +9,6 @@ CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_NR_DRAM_BANKS=2
CONFIG_TARGET_HELIOS4=y
CONFIG_MVEBU_SPL_BOOT_DEVICE_MMC=y
CONFIG_ENV_SIZE=0x2000
CONFIG_ENV_OFFSET=0xFE000
CONFIG_DM_GPIO=y
CONFIG_SPL_TEXT_BASE=0x40000030
CONFIG_SPL_SERIAL_SUPPORT=y

3
configs/turris_mox_defconfig
View File

@ -31,7 +31,8 @@ CONFIG_CMD_MMC=y
CONFIG_CMD_PCI=y
CONFIG_CMD_SPI=y
CONFIG_CMD_USB=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_WDT=y
CONFIG_CMD_SETEXPR=y
CONFIG_CMD_TFTPPUT=y
CONFIG_CMD_CACHE=y
CONFIG_CMD_TIME=y

11
doc/README.distro
View File

@ -224,6 +224,17 @@ fdt_addr_r:
A size of 1MB for the FDT/DTB seems reasonable.
fdtfile:
Mandatory. the name of the DTB file for the specific board for instance
the espressobin v5 board the value is "marvell/armada-3720-espressobin.dtb"
while on a clearfog pro it is "armada-388-clearfog-pro.dtb" in the case of
a board providing its firmware based DTB this value can be used to override
the DTB with a different DTB. fdtfile will automatically be set for you if
it matches the format ${soc}-${board}.dtb which covers most 32 bit use cases.
AArch64 generally does not match as the Linux kernel put the dtb files under
SoC vendor directories.
ramdisk_addr_r:
Mandatory. The location in RAM where the initial ramdisk will be loaded to

2
drivers/gpio/Kconfig
View File

@ -374,7 +374,7 @@ config SIFIVE_GPIO
config MVEBU_GPIO
bool "Marvell MVEBU GPIO driver"
depends on DM_GPIO && ARCH_MVEBU
depends on DM_GPIO && (ARCH_MVEBU || ARCH_KIRKWOOD)
default y
help
Say yes here to support Marvell MVEBU (Armada XP/38x) GPIOs.

19
drivers/mmc/xenon_sdhci.c
View File

@ -338,6 +338,16 @@ static void xenon_mmc_enable_slot(struct sdhci_host *host, u8 slot)
sdhci_writel(host, var, SDHC_SYS_OP_CTRL);
}
/* Disable specific slot */
static void xenon_mmc_disable_slot(struct sdhci_host *host, u8 slot)
{
u32 var;
var = sdhci_readl(host, SDHC_SYS_OP_CTRL);
var &= ~(SLOT_MASK(slot) << SLOT_ENABLE_SHIFT);
sdhci_writel(host, var, SDHC_SYS_OP_CTRL);
}
/* Enable Parallel Transfer Mode */
static void xenon_mmc_enable_parallel_tran(struct sdhci_host *host, u8 slot)
{
@ -503,6 +513,14 @@ static int xenon_sdhci_probe(struct udevice *dev)
return ret;
}
static int xenon_sdhci_remove(struct udevice *dev)
{
struct sdhci_host *host = dev_get_priv(dev);
xenon_mmc_disable_slot(host, XENON_MMC_SLOT_ID_HYPERION);
return 0;
}
static int xenon_sdhci_of_to_plat(struct udevice *dev)
{
struct sdhci_host *host = dev_get_priv(dev);
@ -552,6 +570,7 @@ U_BOOT_DRIVER(xenon_sdhci_drv) = {
.ops = &sdhci_ops,
.bind = xenon_sdhci_bind,
.probe = xenon_sdhci_probe,
.remove = xenon_sdhci_remove,
.priv_auto = sizeof(struct xenon_sdhci_priv),
.plat_auto = sizeof(struct xenon_sdhci_plat),
};

5
drivers/pci/pci-aardvark.c
View File

@ -448,7 +448,6 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
advk_writel(pcie, 1, PIO_START);
if (!pcie_advk_wait_pio(pcie)) {
dev_dbg(pcie->dev, "- wait pio timeout\n");
return -EINVAL;
}
@ -630,12 +629,12 @@ static int pcie_advk_probe(struct udevice *dev)
* clock should be gated as well.
*/
if (dm_gpio_is_valid(&pcie->reset_gpio)) {
dev_dbg(pcie->dev, "Toggle PCIE Reset GPIO ...\n");
dev_dbg(dev, "Toggle PCIE Reset GPIO ...\n");
dm_gpio_set_value(&pcie->reset_gpio, 1);
mdelay(200);
dm_gpio_set_value(&pcie->reset_gpio, 0);
} else {
dev_warn(pcie->dev, "PCIE Reset on GPIO support is missing\n");
dev_warn(dev, "PCIE Reset on GPIO support is missing\n");
}
pcie->first_busno = dev_seq(dev);

9
drivers/pci/pci_auto.c
View File

@ -47,16 +47,17 @@ void dm_pciauto_setup_device(struct udevice *dev, int bars_num,
dm_pci_write_config32(dev, bar, 0xffffffff);
dm_pci_read_config32(dev, bar, &bar_response);
/* If BAR is not implemented go to the next BAR */
if (!bar_response)
/* If BAR is not implemented (or invalid) go to the next BAR */
if (!bar_response || bar_response == 0xffffffff)
continue;
found_mem64 = 0;
/* Check the BAR type and set our address mask */
if (bar_response & PCI_BASE_ADDRESS_SPACE) {
bar_size = ((~(bar_response & PCI_BASE_ADDRESS_IO_MASK))
& 0xffff) + 1;
bar_size = bar_response & PCI_BASE_ADDRESS_IO_MASK;
bar_size &= ~(bar_size - 1);
if (!enum_only)
bar_res = io;

28
drivers/pci/pci_mvebu.c
View File

@ -73,6 +73,7 @@ struct mvebu_pcie {
void __iomem *membase;
struct resource mem;
void __iomem *iobase;
struct resource io;
u32 port;
u32 lane;
int devfn;
@ -81,6 +82,8 @@ struct mvebu_pcie {
char name[16];
unsigned int mem_target;
unsigned int mem_attr;
unsigned int io_target;
unsigned int io_attr;
};
/*
@ -90,6 +93,7 @@ struct mvebu_pcie {
*/
static void __iomem *mvebu_pcie_membase = (void __iomem *)MBUS_PCI_MEM_BASE;
#define PCIE_MEM_SIZE (128 << 20)
static void __iomem *mvebu_pcie_iobase = (void __iomem *)MBUS_PCI_IO_BASE;
static inline bool mvebu_pcie_link_up(struct mvebu_pcie *pcie)
{
@ -306,12 +310,24 @@ static int mvebu_pcie_probe(struct udevice *dev)
(u32)pcie->mem.start, PCIE_MEM_SIZE);
}
pcie->io.start = (u32)mvebu_pcie_iobase;
pcie->io.end = pcie->io.start + MBUS_PCI_IO_SIZE - 1;
mvebu_pcie_iobase += MBUS_PCI_IO_SIZE;
if (mvebu_mbus_add_window_by_id(pcie->io_target, pcie->io_attr,
(phys_addr_t)pcie->io.start,
MBUS_PCI_IO_SIZE)) {
printf("PCIe unable to add mbus window for IO at %08x+%08x\n",
(u32)pcie->io.start, MBUS_PCI_IO_SIZE);
}
/* Setup windows and configure host bridge */
mvebu_pcie_setup_wins(pcie);
/* Master + slave enable. */
reg = readl(pcie->base + PCIE_CMD_OFF);
reg |= PCI_COMMAND_MEMORY;
reg |= PCI_COMMAND_IO;
reg |= PCI_COMMAND_MASTER;
reg |= BIT(10); /* disable interrupts */
writel(reg, pcie->base + PCIE_CMD_OFF);
@ -323,7 +339,9 @@ static int mvebu_pcie_probe(struct udevice *dev)
0, 0,
gd->ram_size,
PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
hose->region_count = 2;
pci_set_region(hose->regions + 2, pcie->io.start,
pcie->io.start, MBUS_PCI_IO_SIZE, PCI_REGION_IO);
hose->region_count = 3;
/* Set BAR0 to internal registers */
writel(SOC_REGS_PHY_BASE, pcie->base + PCIE_BAR_LO_OFF(0));
@ -442,6 +460,14 @@ static int mvebu_pcie_of_to_plat(struct udevice *dev)
goto err;
}
ret = mvebu_get_tgt_attr(dev_ofnode(dev->parent), pcie->devfn,
IORESOURCE_IO,
&pcie->io_target, &pcie->io_attr);
if (ret < 0) {
printf("%s: cannot get tgt/attr for IO window\n", pcie->name);
goto err;
}
/* Parse PCIe controller register base from DT */
ret = mvebu_pcie_port_parse_dt(dev_ofnode(dev), pcie);
if (ret < 0)

10
drivers/serial/serial_mvebu_a3700.c
View File

@ -23,6 +23,7 @@ struct mvebu_plat {
#define UART_POSSR_REG 0x14
#define UART_STATUS_RX_RDY 0x10
#define UART_STATUS_TX_EMPTY 0x40
#define UART_STATUS_TXFIFO_FULL 0x800
#define UART_CTRL_RXFIFO_RESET 0x4000
@ -59,8 +60,13 @@ static int mvebu_serial_pending(struct udevice *dev, bool input)
struct mvebu_plat *plat = dev_get_plat(dev);
void __iomem *base = plat->base;
if (readl(base + UART_STATUS_REG) & UART_STATUS_RX_RDY)
return 1;
if (input) {
if (readl(base + UART_STATUS_REG) & UART_STATUS_RX_RDY)
return 1;
} else {
if (!(readl(base + UART_STATUS_REG) & UART_STATUS_TX_EMPTY))
return 1;
}
return 0;
}

21
include/configs/ds414.h
View File

@ -24,31 +24,13 @@
#define CONFIG_SYS_I2C_SLAVE 0x0
#define CONFIG_SYS_I2C_SPEED 100000
/* Environment in SPI NOR flash */
#define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII
/* PCIe support */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_PCI_SCAN_SHOW
#endif
/* USB/EHCI/XHCI configuration */
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
/* FIXME: broken XHCI support
* Below defines should enable support for the two rear USB3 ports. Sadly, this
* does not work because:
* - xhci-pci seems to not support DM_USB, so with that enabled it is not
* found.
* - USB init fails, controller does not respond in time */
#if !defined(CONFIG_USB_XHCI_HCD)
#define CONFIG_EHCI_IS_TDI
#endif
/* why is this only defined in mv-common.h if CONFIG_DM is undefined? */
/*
* mv-common.h should be defined after CMD configs since it used them
@ -95,4 +77,7 @@
#define CONFIG_BOOTCOMMAND "sf read ${loadaddr} 0xd0000 0x700000; bootm"
#define CONFIG_LOADADDR 0x80000
/* increase autoneg timeout, my NIC sucks */
#define PHY_ANEG_TIMEOUT 16000
#endif /* _CONFIG_SYNOLOGY_DS414_H */