powerpc/mpc85xx: Add board support for ucp1020
New QorIQ p1020 based board support from Arcturus Networks Inc. http://www.arcturusnetworks.com/products/ucp1020/ Signed-off-by: Michael Durrant <mdurrant@arcturusnetworks.com> Signed-off-by: Oleksandr G Zhadan <oleks@arcturusnetworks.com> [York Sun: remove patman tags from commit message] Reviewed-by: York Sun <yorksun@freescale.com>
This commit is contained in:
Oleksandr G Zhadan
York Sun
parent
d7732faad3
commit
8b0044ff59
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@ -151,6 +151,9 @@ config TARGET_XPEDITE537X
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config TARGET_XPEDITE550X
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bool "Support xpedite550x"
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config TARGET_UCP1020
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bool "Support uCP1020"
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endchoice
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source "board/freescale/b4860qds/Kconfig"
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@ -192,5 +195,6 @@ source "board/stx/stxssa/Kconfig"
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source "board/xes/xpedite520x/Kconfig"
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source "board/xes/xpedite537x/Kconfig"
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source "board/xes/xpedite550x/Kconfig"
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source "board/Arcturus/ucp1020/Kconfig"
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endmenu
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@ -0,0 +1,44 @@
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if TARGET_UCP1020
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config SYS_BOARD
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string
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default "ucp1020"
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config SYS_VENDOR
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string
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default "Arcturus"
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config SYS_CONFIG_NAME
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string
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default "UCP1020"
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config SPI_FLASH
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bool
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default y
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config SPI_PCI
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bool
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default y
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choice
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prompt "Target image select"
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config TARGET_UCP1020_NOR
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bool "NOR flash u-boot image"
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config TARGET_UCP1020_SPIFLASH
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bool "SPI flash u-boot image"
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endchoice
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if TARGET_UCP1020_SPIFLASH
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config UCBOOT
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bool
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default y
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config SPIFLASH
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bool
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default y
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endif
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endif
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@ -0,0 +1,7 @@
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UCP1020 BOARD
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M: Oleksandr Zhadan and Michael Durrant <arcsupport@arcturusnetworks.com>
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S: Maintained
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F: board/Arcturus/ucp1020/
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F: include/configs/UCP1020.h
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F: configs/UCP1020_defconfig
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F: configs/UCP1020_SPIFLASH_defconfig
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@ -0,0 +1,33 @@
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#
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# Copyright 2013-2015 Arcturus Networks, Inc.
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# based on board/freescale/p1_p2_rdb_pc/Makefile
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# original copyright follows:
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# Copyright 2010-2011 Freescale Semiconductor, Inc.
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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MINIMAL=
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ifdef CONFIG_SPL_BUILD
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ifdef CONFIG_SPL_INIT_MINIMAL
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MINIMAL=y
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endif
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endif
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ifdef MINIMAL
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obj-y += spl_minimal.o tlb.o law.o
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else
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ifdef CONFIG_SPL_BUILD
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obj-y += spl.o
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endif
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obj-y += ucp1020.o
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obj-y += ddr.o
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obj-y += law.o
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obj-y += tlb.o
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obj-y += cmd_arc.o
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endif
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@ -0,0 +1,54 @@
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The uCP1020 product family (ucp1020) is an Arcturus Networks Inc. System on Modules
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product featuring a Freescale P1020 CPU, optionally populated with 1, 2 or 3 Gig-Ethernet PHYs,
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DDR3, NOR Flash, eMMC NAND Flash and/or SPI Flash.
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Information on the generic product family can be found here:
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http://www.arcturusnetworks.com/products/ucp1020
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The UCP1020 several configurable options
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========================================
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- the selection of populated phy(s):
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KSZ9031 (current default for eTSEC 1 and 3)
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- the selection of boot location:
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SPI Flash or NOR flash
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The UCP1020 includes 2 default configurations
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=============================================
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NOR boot image:
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configs/UCP1020_defconfig
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SPI boot image:
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configs/UCP1020_SPIFLASH_defconfig
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The UCP1020 adds an additional command in cmd_arc.c to access and program
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SPI resident factory defaults for serial number, and 1, 2 or 3 Ethernet
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HW Addresses.
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Build example
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=============
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make distclean
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make UCP1020_defconfig
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make
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Default Scripts
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===============
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A default upgrade scripts is included in the default environment variable example:
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B$ run tftpflash
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Dual Environment
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================
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This build enables dual / failover environment environment.
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NOR Flash Partition declarations and scripts
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============================================
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Several scripts are available to allow TFTP of images and programming directly
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into defined NOR flash partitions. Examples:
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B$ run program0
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B$ run program1
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B$ run program2
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@ -0,0 +1,231 @@
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/*
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* Command for accessing Arcturus factory environment.
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*
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* Copyright 2013-2015 Arcturus Networks Inc.
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* http://www.arcturusnetworks.com/products/ucp1020/
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* by Oleksandr G Zhadan et al.
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*
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* SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
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*
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*/
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#include <common.h>
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#include <div64.h>
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#include <malloc.h>
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#include <spi_flash.h>
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#include <asm/io.h>
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#ifndef CONFIG_SF_DEFAULT_SPEED
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# define CONFIG_SF_DEFAULT_SPEED 1000000
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#endif
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#ifndef CONFIG_SF_DEFAULT_MODE
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# define CONFIG_SF_DEFAULT_MODE SPI_MODE0
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#endif
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#ifndef CONFIG_SF_DEFAULT_CS
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# define CONFIG_SF_DEFAULT_CS 0
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#endif
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#ifndef CONFIG_SF_DEFAULT_BUS
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# define CONFIG_SF_DEFAULT_BUS 0
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#endif
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#define MAX_SERIAL_SIZE 15
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#define MAX_HWADDR_SIZE 17
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#define FIRM_ADDR1 (0x200 - sizeof(smac))
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#define FIRM_ADDR2 (0x400 - sizeof(smac))
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#define FIRM_ADDR3 (CONFIG_ENV_SECT_SIZE + 0x200 - sizeof(smac))
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#define FIRM_ADDR4 (CONFIG_ENV_SECT_SIZE + 0x400 - sizeof(smac))
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static struct spi_flash *flash;
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char smac[4][18];
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static int ishwaddr(char *hwaddr)
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{
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if (strlen(hwaddr) == MAX_HWADDR_SIZE)
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if (hwaddr[2] == ':' &&
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hwaddr[5] == ':' &&
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hwaddr[8] == ':' &&
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hwaddr[11] == ':' &&
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hwaddr[14] == ':')
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return 0;
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return -1;
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}
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static int set_arc_product(int argc, char *const argv[])
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{
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int err = 0;
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char *mystrerr = "ERROR: Failed to save factory info in spi location";
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if (argc != 5)
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return -1;
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/* Check serial number */
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if (strlen(argv[1]) != MAX_SERIAL_SIZE)
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return -1;
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/* Check HWaddrs */
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if (ishwaddr(argv[2]) || ishwaddr(argv[3]) || ishwaddr(argv[4]))
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return -1;
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strcpy(smac[3], argv[1]);
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strcpy(smac[2], argv[2]);
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strcpy(smac[1], argv[3]);
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strcpy(smac[0], argv[4]);
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flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
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CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
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/*
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* Save factory defaults
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*/
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if (spi_flash_write(flash, FIRM_ADDR1, sizeof(smac), smac)) {
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printf("%s: %s [1]\n", __func__, mystrerr);
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err++;
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}
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if (spi_flash_write(flash, FIRM_ADDR2, sizeof(smac), smac)) {
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printf("%s: %s [2]\n", __func__, mystrerr);
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err++;
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}
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if (spi_flash_write(flash, FIRM_ADDR3, sizeof(smac), smac)) {
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printf("%s: %s [3]\n", __func__, mystrerr);
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err++;
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}
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if (spi_flash_write(flash, FIRM_ADDR4, sizeof(smac), smac)) {
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printf("%s: %s [4]\n", __func__, mystrerr);
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err++;
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}
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if (err == 4) {
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printf("%s: %s [ALL]\n", __func__, mystrerr);
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return -2;
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}
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return 0;
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}
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int get_arc_info(void)
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{
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int location = 1;
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char *myerr = "ERROR: Failed to read all 4 factory info spi locations";
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flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS,
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CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE);
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if (spi_flash_read(flash, FIRM_ADDR1, sizeof(smac), smac)) {
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location++;
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if (spi_flash_read(flash, FIRM_ADDR2, sizeof(smac), smac)) {
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location++;
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if (spi_flash_read(flash, FIRM_ADDR3, sizeof(smac),
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smac)) {
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location++;
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if (spi_flash_read(flash, FIRM_ADDR4,
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sizeof(smac), smac)) {
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printf("%s: %s\n", __func__, myerr);
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return -2;
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}
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}
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}
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}
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if (smac[3][0] != 0) {
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if (location > 1)
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printf("Using region %d\n", location);
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printf("SERIAL: ");
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if (smac[3][0] == 0xFF) {
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printf("\t<not found>\n");
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} else {
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printf("\t%s\n", smac[3]);
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setenv("SERIAL", smac[3]);
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}
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}
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if (strcmp(smac[2], "00:00:00:00:00:00") == 0)
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return 0;
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printf("HWADDR0:");
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if (smac[2][0] == 0xFF) {
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printf("\t<not found>\n");
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} else {
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char *ret = getenv("ethaddr");
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if (strcmp(ret, __stringify(CONFIG_ETHADDR)) == 0) {
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setenv("ethaddr", smac[2]);
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printf("\t%s (factory)\n", smac[2]);
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} else {
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printf("\t%s\n", ret);
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}
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}
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if (strcmp(smac[1], "00:00:00:00:00:00") == 0) {
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setenv("eth1addr", smac[2]);
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setenv("eth2addr", smac[2]);
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return 0;
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}
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printf("HWADDR1:");
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if (smac[1][0] == 0xFF) {
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printf("\t<not found>\n");
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} else {
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char *ret = getenv("eth1addr");
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if (strcmp(ret, __stringify(CONFIG_ETH1ADDR)) == 0) {
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setenv("eth1addr", smac[1]);
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printf("\t%s (factory)\n", smac[1]);
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} else {
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printf("\t%s\n", ret);
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}
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}
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if (strcmp(smac[0], "00:00:00:00:00:00") == 0) {
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setenv("eth2addr", smac[1]);
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return 0;
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}
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printf("HWADDR2:");
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if (smac[0][0] == 0xFF) {
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printf("\t<not found>\n");
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} else {
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char *ret = getenv("eth2addr");
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if (strcmp(ret, __stringify(CONFIG_ETH2ADDR)) == 0) {
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setenv("eth2addr", smac[0]);
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printf("\t%s (factory)\n", smac[0]);
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} else {
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printf("\t%s\n", ret);
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}
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}
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return 0;
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}
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static int do_arc_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
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{
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const char *cmd;
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int ret = -1;
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cmd = argv[1];
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--argc;
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++argv;
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if (strcmp(cmd, "product") == 0) {
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ret = set_arc_product(argc, argv);
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goto done;
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}
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if (strcmp(cmd, "info") == 0) {
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ret = get_arc_info();
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goto done;
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}
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done:
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if (ret == -1)
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return CMD_RET_USAGE;
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return ret;
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}
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U_BOOT_CMD(arc, 6, 1, do_arc_cmd,
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"Arcturus product command sub-system",
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"product serial hwaddr0 hwaddr1 hwaddr2 - save Arcturus factory env\n"
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"info - show Arcturus factory env\n\n");
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@ -0,0 +1,161 @@
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/*
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* Copyright 2013-2015 Arcturus Networks, Inc.
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* http://www.arcturusnetworks.com/products/ucp1020/
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* based on board/freescale/p1_p2_rdb_pc/spl.c
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* original copyright follows:
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* Copyright 2013 Freescale Semiconductor, Inc.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/mmu.h>
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#include <asm/immap_85xx.h>
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#include <asm/processor.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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#include <asm/io.h>
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#include <asm/fsl_law.h>
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#ifdef CONFIG_SYS_DDR_RAW_TIMING
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#if defined(CONFIG_UCP1020) || defined(CONFIG_UCP1020T1)
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/*
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* Micron MT41J128M16HA-15E
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* */
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dimm_params_t ddr_raw_timing = {
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.n_ranks = 1,
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.rank_density = 536870912u,
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.capacity = 536870912u,
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.primary_sdram_width = 32,
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.ec_sdram_width = 8,
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.registered_dimm = 0,
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.mirrored_dimm = 0,
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.n_row_addr = 14,
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.n_col_addr = 10,
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.n_banks_per_sdram_device = 8,
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.edc_config = 2,
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.burst_lengths_bitmask = 0x0c,
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.tckmin_x_ps = 1650,
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.caslat_x = 0x7e << 4, /* 5,6,7,8,9,10 */
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.taa_ps = 14050,
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.twr_ps = 15000,
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.trcd_ps = 13500,
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.trrd_ps = 75000,
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.trp_ps = 13500,
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.tras_ps = 40000,
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.trc_ps = 49500,
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.trfc_ps = 160000,
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.twtr_ps = 75000,
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.trtp_ps = 75000,
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.refresh_rate_ps = 7800000,
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.tfaw_ps = 30000,
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};
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#else
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#error Missing raw timing data for this board
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#endif
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int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
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unsigned int controller_number,
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unsigned int dimm_number)
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{
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const char dimm_model[] = "Fixed DDR on board";
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if ((controller_number == 0) && (dimm_number == 0)) {
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memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
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memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
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memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
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}
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return 0;
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}
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#endif /* CONFIG_SYS_DDR_RAW_TIMING */
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#ifdef CONFIG_SYS_DDR_CS0_BNDS
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/* Fixed sdram init -- doesn't use serial presence detect. */
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phys_size_t fixed_sdram(void)
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{
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sys_info_t sysinfo;
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char buf[32];
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size_t ddr_size;
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fsl_ddr_cfg_regs_t ddr_cfg_regs = {
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.cs[0].bnds = CONFIG_SYS_DDR_CS0_BNDS,
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.cs[0].config = CONFIG_SYS_DDR_CS0_CONFIG,
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.cs[0].config_2 = CONFIG_SYS_DDR_CS0_CONFIG_2,
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#if CONFIG_CHIP_SELECTS_PER_CTRL > 1
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.cs[1].bnds = CONFIG_SYS_DDR_CS1_BNDS,
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.cs[1].config = CONFIG_SYS_DDR_CS1_CONFIG,
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.cs[1].config_2 = CONFIG_SYS_DDR_CS1_CONFIG_2,
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#endif
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.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3,
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.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0,
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.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1,
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.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2,
|
||||
.ddr_sdram_cfg = CONFIG_SYS_DDR_CONTROL,
|
||||
.ddr_sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL_2,
|
||||
.ddr_sdram_mode = CONFIG_SYS_DDR_MODE_1,
|
||||
.ddr_sdram_mode_2 = CONFIG_SYS_DDR_MODE_2,
|
||||
.ddr_sdram_md_cntl = CONFIG_SYS_DDR_MODE_CONTROL,
|
||||
.ddr_sdram_interval = CONFIG_SYS_DDR_INTERVAL,
|
||||
.ddr_data_init = CONFIG_SYS_DDR_DATA_INIT,
|
||||
.ddr_sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL,
|
||||
.ddr_init_addr = CONFIG_SYS_DDR_INIT_ADDR,
|
||||
.ddr_init_ext_addr = CONFIG_SYS_DDR_INIT_EXT_ADDR,
|
||||
.timing_cfg_4 = CONFIG_SYS_DDR_TIMING_4,
|
||||
.timing_cfg_5 = CONFIG_SYS_DDR_TIMING_5,
|
||||
.ddr_zq_cntl = CONFIG_SYS_DDR_ZQ_CONTROL,
|
||||
.ddr_wrlvl_cntl = CONFIG_SYS_DDR_WRLVL_CONTROL,
|
||||
.ddr_sr_cntr = CONFIG_SYS_DDR_SR_CNTR,
|
||||
.ddr_sdram_rcw_1 = CONFIG_SYS_DDR_RCW_1,
|
||||
.ddr_sdram_rcw_2 = CONFIG_SYS_DDR_RCW_2
|
||||
};
|
||||
|
||||
get_sys_info(&sysinfo);
|
||||
printf("Configuring DDR for %s MT/s data rate\n",
|
||||
strmhz(buf, sysinfo.freq_ddrbus));
|
||||
|
||||
ddr_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
|
||||
|
||||
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0, 0);
|
||||
|
||||
if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE,
|
||||
ddr_size, LAW_TRGT_IF_DDR_1) < 0) {
|
||||
printf("ERROR setting Local Access Windows for DDR\n");
|
||||
return 0;
|
||||
};
|
||||
|
||||
return ddr_size;
|
||||
}
|
||||
#endif
|
||||
|
||||
void fsl_ddr_board_options(memctl_options_t *popts,
|
||||
dimm_params_t *pdimm,
|
||||
unsigned int ctrl_num)
|
||||
{
|
||||
int i;
|
||||
|
||||
popts->clk_adjust = 6;
|
||||
popts->cpo_override = 0x1f;
|
||||
popts->write_data_delay = 2;
|
||||
popts->half_strength_driver_enable = 1;
|
||||
/* Write leveling override */
|
||||
popts->wrlvl_en = 1;
|
||||
popts->wrlvl_override = 1;
|
||||
popts->wrlvl_sample = 0xf;
|
||||
popts->wrlvl_start = 0x8;
|
||||
popts->trwt_override = 1;
|
||||
popts->trwt = 0;
|
||||
|
||||
if (pdimm->primary_sdram_width == 64)
|
||||
popts->data_bus_width = 0;
|
||||
else if (pdimm->primary_sdram_width == 32)
|
||||
popts->data_bus_width = 1;
|
||||
else
|
||||
printf("Error in DDR bus width configuration!\n");
|
||||
|
||||
for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) {
|
||||
popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER;
|
||||
popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS;
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* Copyright 2013-2015 Arcturus Networks, Inc.
|
||||
* http://www.arcturusnetworks.com/products/ucp1020/
|
||||
* based on board/freescale/p1_p2_rdb_pc/spl.c
|
||||
* original copyright follows:
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
struct law_entry law_table[] = {
|
||||
#ifdef CONFIG_VSC7385_ENET
|
||||
SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
|
||||
#endif
|
||||
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
|
||||
#ifdef CONFIG_SYS_NAND_BASE_PHYS
|
||||
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
|
||||
#endif
|
||||
};
|
||||
|
||||
int num_law_entries = ARRAY_SIZE(law_table);
|
||||
|
|
@ -0,0 +1,126 @@
|
|||
/*
|
||||
* Copyright 2013-2015 Arcturus Networks, Inc.
|
||||
* http://www.arcturusnetworks.com/products/ucp1020/
|
||||
* based on board/freescale/p1_p2_rdb_pc/spl.c
|
||||
* original copyright follows:
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <ns16550.h>
|
||||
#include <malloc.h>
|
||||
#include <mmc.h>
|
||||
#include <nand.h>
|
||||
#include <i2c.h>
|
||||
#include <fsl_esdhc.h>
|
||||
#include <spi_flash.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
static const u32 sysclk_tbl[] = {
|
||||
66666000, 7499900, 83332500, 8999900,
|
||||
99999000, 11111000, 12499800, 13333200
|
||||
};
|
||||
|
||||
phys_size_t get_effective_memsize(void)
|
||||
{
|
||||
return CONFIG_SYS_L2_SIZE;
|
||||
}
|
||||
|
||||
void board_init_f(ulong bootflag)
|
||||
{
|
||||
u32 plat_ratio, bus_clk;
|
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
||||
|
||||
console_init_f();
|
||||
|
||||
/* Set pmuxcr to allow both i2c1 and i2c2 */
|
||||
setbits_be32(&gur->pmuxcr, in_be32(&gur->pmuxcr) | 0x1000);
|
||||
setbits_be32(&gur->pmuxcr,
|
||||
in_be32(&gur->pmuxcr) | MPC85xx_PMUXCR_SD_DATA);
|
||||
|
||||
/* Read back the register to synchronize the write. */
|
||||
in_be32(&gur->pmuxcr);
|
||||
|
||||
#ifdef CONFIG_SPL_SPI_BOOT
|
||||
clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SD_DATA);
|
||||
#endif
|
||||
|
||||
/* initialize selected port with appropriate baud rate */
|
||||
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
|
||||
plat_ratio >>= 1;
|
||||
bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
|
||||
gd->bus_clk = bus_clk;
|
||||
|
||||
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
|
||||
bus_clk / 16 / CONFIG_BAUDRATE);
|
||||
#ifdef CONFIG_SPL_MMC_BOOT
|
||||
puts("\nSD boot...\n");
|
||||
#elif defined(CONFIG_SPL_SPI_BOOT)
|
||||
puts("\nSPI Flash boot...\n");
|
||||
#endif
|
||||
|
||||
/* copy code to RAM and jump to it - this should not return */
|
||||
/* NOTE - code has to be copied out of NAND buffer before
|
||||
* other blocks can be read.
|
||||
*/
|
||||
relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
|
||||
}
|
||||
|
||||
void board_init_r(gd_t *gd, ulong dest_addr)
|
||||
{
|
||||
/* Pointer is writable since we allocated a register for it */
|
||||
gd = (gd_t *)CONFIG_SPL_GD_ADDR;
|
||||
bd_t *bd;
|
||||
|
||||
memset(gd, 0, sizeof(gd_t));
|
||||
bd = (bd_t *)(CONFIG_SPL_GD_ADDR + sizeof(gd_t));
|
||||
memset(bd, 0, sizeof(bd_t));
|
||||
gd->bd = bd;
|
||||
bd->bi_memstart = CONFIG_SYS_INIT_L2_ADDR;
|
||||
bd->bi_memsize = CONFIG_SYS_L2_SIZE;
|
||||
|
||||
probecpu();
|
||||
get_clocks();
|
||||
mem_malloc_init(CONFIG_SPL_RELOC_MALLOC_ADDR,
|
||||
CONFIG_SPL_RELOC_MALLOC_SIZE);
|
||||
|
||||
#ifndef CONFIG_SPL_NAND_BOOT
|
||||
env_init();
|
||||
#endif
|
||||
#ifdef CONFIG_SPL_MMC_BOOT
|
||||
mmc_initialize(bd);
|
||||
#endif
|
||||
/* relocate environment function pointers etc. */
|
||||
#ifdef CONFIG_SPL_NAND_BOOT
|
||||
nand_spl_load_image(CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE,
|
||||
(uchar *)CONFIG_ENV_ADDR);
|
||||
gd->env_addr = (ulong)(CONFIG_ENV_ADDR);
|
||||
gd->env_valid = 1;
|
||||
#else
|
||||
env_relocate();
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SYS_I2C
|
||||
i2c_init_all();
|
||||
#else
|
||||
i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
|
||||
#endif
|
||||
|
||||
gd->ram_size = initdram(0);
|
||||
#ifdef CONFIG_SPL_NAND_BOOT
|
||||
puts("Tertiary program loader running in sram...");
|
||||
#else
|
||||
puts("Second program loader running in sram...\n");
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPL_MMC_BOOT
|
||||
mmc_boot();
|
||||
#elif defined(CONFIG_SPL_SPI_BOOT)
|
||||
spi_boot();
|
||||
#elif defined(CONFIG_SPL_NAND_BOOT)
|
||||
nand_boot();
|
||||
#endif
|
||||
}
|
||||
|
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
* Copyright 2013-2015 Arcturus Networks, Inc.
|
||||
* http://www.arcturusnetworks.com/products/ucp1020/
|
||||
* based on board/freescale/p1_p2_rdb_pc/spl_minimal.c
|
||||
* original copyright follows:
|
||||
* Copyright 2011 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <ns16550.h>
|
||||
#include <asm/io.h>
|
||||
#include <nand.h>
|
||||
#include <linux/compiler.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include <fsl_ddr_sdram.h>
|
||||
#include <asm/global_data.h>
|
||||
|
||||
DECLARE_GLOBAL_DATA_PTR;
|
||||
|
||||
void board_init_f(ulong bootflag)
|
||||
{
|
||||
u32 plat_ratio;
|
||||
ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
|
||||
|
||||
#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM)
|
||||
set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
|
||||
set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
|
||||
#endif
|
||||
|
||||
/* initialize selected port with appropriate baud rate */
|
||||
plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO;
|
||||
plat_ratio >>= 1;
|
||||
gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio;
|
||||
|
||||
NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1,
|
||||
gd->bus_clk / 16 / CONFIG_BAUDRATE);
|
||||
|
||||
puts("\nNAND boot... ");
|
||||
|
||||
/* copy code to RAM and jump to it - this should not return */
|
||||
/* NOTE - code has to be copied out of NAND buffer before
|
||||
* other blocks can be read.
|
||||
*/
|
||||
relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE);
|
||||
}
|
||||
|
||||
void board_init_r(gd_t *gd, ulong dest_addr)
|
||||
{
|
||||
puts("\nSecond program loader running in sram...");
|
||||
nand_boot();
|
||||
}
|
||||
|
||||
void putc(char c)
|
||||
{
|
||||
if (c == '\n')
|
||||
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r');
|
||||
|
||||
NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c);
|
||||
}
|
||||
|
||||
void puts(const char *str)
|
||||
{
|
||||
while (*str)
|
||||
putc(*str++);
|
||||
}
|
||||
|
|
@ -0,0 +1,101 @@
|
|||
/*
|
||||
* Copyright 2013-2015 Arcturus Networks, Inc
|
||||
* http://www.arcturusnetworks.com/products/ucp1020/
|
||||
* based on board/freescale/p1_p2_rdb_pc/tlb.c
|
||||
* original copyright follows:
|
||||
* Copyright 2010-2011 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = {
|
||||
/* TLB 0 - for temp stack in cache */
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS,
|
||||
MAS3_SX | MAS3_SW | MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
|
||||
MAS3_SX | MAS3_SW | MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
|
||||
MAS3_SX | MAS3_SW | MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
||||
CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
|
||||
MAS3_SX | MAS3_SW | MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
|
||||
/* TLB 1 */
|
||||
/* *I*** - Covers boot page */
|
||||
SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
|
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I,
|
||||
0, 0, BOOKE_PAGESZ_4K, 1),
|
||||
|
||||
/* *I*G* - CCSRBAR */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
|
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
|
||||
0, 1, BOOKE_PAGESZ_1M, 1),
|
||||
|
||||
#ifndef CONFIG_SPL_BUILD
|
||||
/* W**G* - Flash/promjet, localbus */
|
||||
/* This will be changed to *I*G* after relocation to RAM. */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
|
||||
MAS3_SX | MAS3_SR, MAS2_W | MAS2_G,
|
||||
0, 2, BOOKE_PAGESZ_64M, 1),
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
/* *I*G* - PCI memory 1.5G */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
|
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
|
||||
0, 3, BOOKE_PAGESZ_1G, 1),
|
||||
|
||||
/* *I*G* - PCI I/O effective: 192K */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
|
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
|
||||
0, 4, BOOKE_PAGESZ_256K, 1),
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_VSC7385_ENET
|
||||
/* *I*G - VSC7385 Switch */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
|
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
|
||||
0, 5, BOOKE_PAGESZ_1M, 1),
|
||||
#endif
|
||||
#endif /* not SPL */
|
||||
|
||||
#ifdef CONFIG_SYS_NAND_BASE
|
||||
/* *I*G - NAND */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
|
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
|
||||
0, 7, BOOKE_PAGESZ_1M, 1),
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SYS_RAMBOOT) || \
|
||||
(defined(CONFIG_SPL) && !defined(CONFIG_SPL_COMMON_INIT_DDR))
|
||||
/* *I*G - eSDHC/eSPI/NAND boot */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
|
||||
MAS3_SX | MAS3_SW | MAS3_SR, 0,
|
||||
0, 8, BOOKE_PAGESZ_1G, 1),
|
||||
|
||||
#endif /* RAMBOOT/SPL */
|
||||
|
||||
#ifdef CONFIG_SYS_INIT_L2_ADDR
|
||||
/* *I*G - L2SRAM */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
|
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_G,
|
||||
0, 11, BOOKE_PAGESZ_256K, 1),
|
||||
#if CONFIG_SYS_L2_SIZE >= (256 << 10)
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
|
||||
CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
|
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
|
||||
0, 12, BOOKE_PAGESZ_256K, 1)
|
||||
#endif
|
||||
#endif
|
||||
};
|
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table);
|
||||
|
|
@ -0,0 +1,363 @@
|
|||
/*
|
||||
* Copyright 2013-2015 Arcturus Networks, Inc.
|
||||
* http://www.arcturusnetworks.com/products/ucp1020/
|
||||
* by Oleksandr G Zhadan et al.
|
||||
* based on board/freescale/p1_p2_rdb_pc/spl.c
|
||||
* original copyright follows:
|
||||
* Copyright 2013 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <command.h>
|
||||
#include <hwconfig.h>
|
||||
#include <pci.h>
|
||||
#include <i2c.h>
|
||||
#include <miiphy.h>
|
||||
#include <libfdt.h>
|
||||
#include <fdt_support.h>
|
||||
#include <fsl_mdio.h>
|
||||
#include <tsec.h>
|
||||
#include <ioports.h>
|
||||
#include <netdev.h>
|
||||
#include <micrel.h>
|
||||
#include <spi_flash.h>
|
||||
#include <mmc.h>
|
||||
#include <linux/ctype.h>
|
||||
#include <asm/fsl_serdes.h>
|
||||
#include <asm/gpio.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/mmu.h>
|
||||
#include <asm/cache.h>
|
||||
#include <asm/immap_85xx.h>
|
||||
#include <asm/fsl_pci.h>
|
||||
#include <fsl_ddr_sdram.h>
|
||||
#include <asm/io.h>
|
||||
#include <asm/fsl_law.h>
|
||||
#include <asm/fsl_lbc.h>
|
||||
#include <asm/mp.h>
|
||||
#include "ucp1020.h"
|
||||
|
||||
void spi_set_speed(struct spi_slave *slave, uint hz)
|
||||
{
|
||||
/* TO DO: It's actially have to be in spi/ */
|
||||
}
|
||||
|
||||
/*
|
||||
* To be compatible with cmd_gpio
|
||||
*/
|
||||
int name_to_gpio(const char *name)
|
||||
{
|
||||
int gpio = 31 - simple_strtoul(name, NULL, 10);
|
||||
|
||||
if (gpio < 16)
|
||||
gpio = -1;
|
||||
|
||||
return gpio;
|
||||
}
|
||||
|
||||
void board_gpio_init(void)
|
||||
{
|
||||
int i;
|
||||
char envname[8], *val;
|
||||
|
||||
for (i = 0; i < GPIO_MAX_NUM; i++) {
|
||||
sprintf(envname, "GPIO%d", i);
|
||||
val = getenv(envname);
|
||||
if (val) {
|
||||
char direction = toupper(val[0]);
|
||||
char level = toupper(val[1]);
|
||||
|
||||
if (direction == 'I') {
|
||||
gpio_direction_input(i);
|
||||
} else {
|
||||
if (direction == 'O') {
|
||||
if (level == '1')
|
||||
gpio_direction_output(i, 1);
|
||||
else
|
||||
gpio_direction_output(i, 0);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
val = getenv("PCIE_OFF");
|
||||
if (val) {
|
||||
gpio_direction_input(GPIO_PCIE1_EN);
|
||||
gpio_direction_input(GPIO_PCIE2_EN);
|
||||
} else {
|
||||
gpio_direction_output(GPIO_PCIE1_EN, 1);
|
||||
gpio_direction_output(GPIO_PCIE2_EN, 1);
|
||||
}
|
||||
|
||||
val = getenv("SDHC_CDWP_OFF");
|
||||
if (!val) {
|
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
|
||||
setbits_be32(&gur->pmuxcr,
|
||||
(MPC85xx_PMUXCR_SDHC_CD | MPC85xx_PMUXCR_SDHC_WP));
|
||||
}
|
||||
}
|
||||
|
||||
int board_early_init_f(void)
|
||||
{
|
||||
return 0; /* Just in case. Could be disable in config file */
|
||||
}
|
||||
|
||||
int checkboard(void)
|
||||
{
|
||||
printf("Board: %s\n", CONFIG_BOARDNAME_LOCAL);
|
||||
board_gpio_init();
|
||||
printf("SD/MMC: 4-bit Mode\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_PCI
|
||||
void pci_init_board(void)
|
||||
{
|
||||
fsl_pcie_init_board(0);
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_early_init_r(void)
|
||||
{
|
||||
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
|
||||
const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
|
||||
|
||||
/*
|
||||
* Remap Boot flash region to caching-inhibited
|
||||
* so that flash can be erased properly.
|
||||
*/
|
||||
|
||||
/* Flush d-cache and invalidate i-cache of any FLASH data */
|
||||
flush_dcache();
|
||||
invalidate_icache();
|
||||
|
||||
/* invalidate existing TLB entry for flash */
|
||||
disable_tlb(flash_esel);
|
||||
|
||||
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
|
||||
MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, /* perms, wimge */
|
||||
0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_phy_config(struct phy_device *phydev)
|
||||
{
|
||||
#if defined(CONFIG_PHY_MICREL_KSZ9021)
|
||||
int regval;
|
||||
static int cnt;
|
||||
|
||||
if (cnt++ == 0)
|
||||
printf("PHYs address [");
|
||||
|
||||
if (phydev->addr == TSEC1_PHY_ADDR || phydev->addr == TSEC3_PHY_ADDR) {
|
||||
regval =
|
||||
ksz9021_phy_extended_read(phydev,
|
||||
MII_KSZ9021_EXT_STRAP_STATUS);
|
||||
/*
|
||||
* min rx data delay
|
||||
*/
|
||||
ksz9021_phy_extended_write(phydev,
|
||||
MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW,
|
||||
0x6666);
|
||||
/*
|
||||
* max rx/tx clock delay, min rx/tx control
|
||||
*/
|
||||
ksz9021_phy_extended_write(phydev,
|
||||
MII_KSZ9021_EXT_RGMII_CLOCK_SKEW,
|
||||
0xf6f6);
|
||||
printf("0x%x", (regval & 0x1f));
|
||||
} else {
|
||||
printf("0x%x", (TSEC2_PHY_ADDR & 0x1f));
|
||||
}
|
||||
if (cnt == 3)
|
||||
printf("] ");
|
||||
else
|
||||
printf(",");
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PHY_MICREL_KSZ9031_DEBUG)
|
||||
regval = ksz9031_phy_extended_read(phydev, 2, 0x01, 0x4000);
|
||||
if (regval >= 0)
|
||||
printf(" (ADDR 0x%x) ", regval & 0x1f);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int last_stage_init(void)
|
||||
{
|
||||
static char newkernelargs[256];
|
||||
static u8 id1[16];
|
||||
static u8 id2;
|
||||
struct mmc *mmc;
|
||||
char *sval, *kval;
|
||||
|
||||
if (i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 7, 1, &id1[0], 2) < 0) {
|
||||
printf("Error reading i2c IDT6V49205B information!\n");
|
||||
} else {
|
||||
printf("IDT6V49205B(0x%02x): ready\n", id1[1]);
|
||||
i2c_read(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2);
|
||||
if (!(id1[1] & 0x02)) {
|
||||
id1[1] |= 0x02;
|
||||
i2c_write(CONFIG_SYS_I2C_IDT6V49205B, 4, 1, &id1[0], 2);
|
||||
asm("nop; nop");
|
||||
}
|
||||
}
|
||||
|
||||
if (i2c_read(CONFIG_SYS_I2C_NCT72_ADDR, 0xFE, 1, &id2, 1) < 0)
|
||||
printf("Error reading i2c NCT72 information!\n");
|
||||
else
|
||||
printf("NCT72(0x%x): ready\n", id2);
|
||||
|
||||
kval = getenv("kernelargs");
|
||||
|
||||
mmc = find_mmc_device(0);
|
||||
if (mmc)
|
||||
if (!mmc_init(mmc)) {
|
||||
printf("MMC/SD card detected\n");
|
||||
if (kval) {
|
||||
int n = strlen(defkargs);
|
||||
char *tmp = strstr(kval, defkargs);
|
||||
|
||||
*tmp = 0;
|
||||
strcpy(newkernelargs, kval);
|
||||
strcat(newkernelargs, " ");
|
||||
strcat(newkernelargs, mmckargs);
|
||||
strcat(newkernelargs, " ");
|
||||
strcat(newkernelargs, &tmp[n]);
|
||||
setenv("kernelargs", newkernelargs);
|
||||
} else {
|
||||
setenv("kernelargs", mmckargs);
|
||||
}
|
||||
}
|
||||
get_arc_info();
|
||||
|
||||
if (kval) {
|
||||
sval = getenv("SERIAL");
|
||||
if (sval) {
|
||||
strcpy(newkernelargs, "SN=");
|
||||
strcat(newkernelargs, sval);
|
||||
strcat(newkernelargs, " ");
|
||||
strcat(newkernelargs, kval);
|
||||
setenv("kernelargs", newkernelargs);
|
||||
}
|
||||
} else {
|
||||
printf("Error reading kernelargs env variable!\n");
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
struct fsl_pq_mdio_info mdio_info;
|
||||
struct tsec_info_struct tsec_info[4];
|
||||
#ifdef CONFIG_TSEC2
|
||||
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
|
||||
#endif
|
||||
int num = 0;
|
||||
|
||||
#ifdef CONFIG_TSEC1
|
||||
SET_STD_TSEC_INFO(tsec_info[num], 1);
|
||||
num++;
|
||||
#endif
|
||||
#ifdef CONFIG_TSEC2
|
||||
SET_STD_TSEC_INFO(tsec_info[num], 2);
|
||||
if (is_serdes_configured(SGMII_TSEC2)) {
|
||||
if (!(in_be32(&gur->pordevsr) & MPC85xx_PORDEVSR_SGMII2_DIS)) {
|
||||
puts("eTSEC2 is in sgmii mode.\n");
|
||||
tsec_info[num].flags |= TSEC_SGMII;
|
||||
tsec_info[num].phyaddr = TSEC2_PHY_ADDR_SGMII;
|
||||
}
|
||||
}
|
||||
num++;
|
||||
#endif
|
||||
#ifdef CONFIG_TSEC3
|
||||
SET_STD_TSEC_INFO(tsec_info[num], 3);
|
||||
num++;
|
||||
#endif
|
||||
|
||||
if (!num) {
|
||||
printf("No TSECs initialized\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
|
||||
mdio_info.name = DEFAULT_MII_NAME;
|
||||
|
||||
fsl_pq_mdio_init(bis, &mdio_info);
|
||||
|
||||
tsec_eth_init(bis, tsec_info, num);
|
||||
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF_BOARD_SETUP
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
phys_addr_t base;
|
||||
phys_size_t size;
|
||||
const char *soc_usb_compat = "fsl-usb2-dr";
|
||||
int err, usb1_off, usb2_off;
|
||||
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
base = getenv_bootm_low();
|
||||
size = getenv_bootm_size();
|
||||
|
||||
fdt_fixup_memory(blob, (u64)base, (u64)size);
|
||||
|
||||
FT_FSL_PCI_SETUP;
|
||||
|
||||
#if defined(CONFIG_HAS_FSL_DR_USB)
|
||||
fdt_fixup_dr_usb(blob, bd);
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
|
||||
/* Delete eLBC node as it is muxed with USB2 controller */
|
||||
if (hwconfig("usb2")) {
|
||||
const char *soc_elbc_compat = "fsl,p1020-elbc";
|
||||
int off = fdt_node_offset_by_compatible(blob, -1,
|
||||
soc_elbc_compat);
|
||||
if (off < 0) {
|
||||
printf
|
||||
("WARNING: could not find compatible node %s: %s\n",
|
||||
soc_elbc_compat, fdt_strerror(off));
|
||||
return off;
|
||||
}
|
||||
err = fdt_del_node(blob, off);
|
||||
if (err < 0) {
|
||||
printf("WARNING: could not remove %s: %s\n",
|
||||
soc_elbc_compat, fdt_strerror(err));
|
||||
}
|
||||
return err;
|
||||
}
|
||||
#endif
|
||||
|
||||
/* Delete USB2 node as it is muxed with eLBC */
|
||||
usb1_off = fdt_node_offset_by_compatible(blob, -1, soc_usb_compat);
|
||||
if (usb1_off < 0) {
|
||||
printf("WARNING: could not find compatible node %s: %s.\n",
|
||||
soc_usb_compat, fdt_strerror(usb1_off));
|
||||
return usb1_off;
|
||||
}
|
||||
usb2_off =
|
||||
fdt_node_offset_by_compatible(blob, usb1_off, soc_usb_compat);
|
||||
if (usb2_off < 0) {
|
||||
printf("WARNING: could not find compatible node %s: %s.\n",
|
||||
soc_usb_compat, fdt_strerror(usb2_off));
|
||||
return usb2_off;
|
||||
}
|
||||
err = fdt_del_node(blob, usb2_off);
|
||||
if (err < 0) {
|
||||
printf("WARNING: could not remove %s: %s.\n",
|
||||
soc_usb_compat, fdt_strerror(err));
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -0,0 +1,44 @@
|
|||
/*
|
||||
* Copyright 2013-2015 Arcturus Networks, Inc.
|
||||
* http://www.arcturusnetworks.com/products/ucp1020/
|
||||
* by Oleksandr G Zhadan et al.
|
||||
*
|
||||
* SPDX-License-Identifier: GPL-2.0+
|
||||
*/
|
||||
|
||||
#ifndef __UCP1020_H__
|
||||
#define __UCP1020_H__
|
||||
|
||||
#define GPIO0 31
|
||||
#define GPIO1 30
|
||||
#define GPIO2 29
|
||||
#define GPIO3 28
|
||||
#define GPIO4 27
|
||||
#define GPIO5 26
|
||||
#define GPIO6 25
|
||||
#define GPIO7 24
|
||||
#define GPIO8 23
|
||||
#define GPIO9 22
|
||||
#define GPIO10 21
|
||||
#define GPIO11 20
|
||||
#define GPIO12 19
|
||||
#define GPIO13 18
|
||||
#define GPIO14 17
|
||||
#define GPIO15 16
|
||||
#define GPIO_MAX_NUM 16
|
||||
|
||||
#define GPIO_SDHC_CD GPIO8
|
||||
#define GPIO_SDHC_WP GPIO9
|
||||
#define GPIO_USB_PCTL0 GPIO10
|
||||
#define GPIO_PCIE1_EN GPIO11
|
||||
#define GPIO_PCIE2_EN GPIO10
|
||||
#define GPIO_USB_PCTL1 GPIO11
|
||||
|
||||
#define GPIO_WD GPIO15
|
||||
|
||||
static char *defkargs = "root=/dev/mtdblock1 rootfstype=cramfs ro";
|
||||
static char *mmckargs = "root=/dev/mmcblk0p1 rootwait rw";
|
||||
|
||||
int get_arc_info(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
CONFIG_PPC=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_UCP1020=y
|
||||
CONFIG_TARGET_UCP1020_SPIFLASH=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_UCP1020=y
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
CONFIG_PPC=y
|
||||
CONFIG_MPC85xx=y
|
||||
CONFIG_TARGET_UCP1020=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_UCP1020=y
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue