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ppc4xx: Only define DDR2 registers for the correct PowerPC variants

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Make sure that some SDRAM/DDR2 registers are only defined for the PPC
variants really implementing those registers.

Signed-off-by: Stefan Roese <sr@denx.de>
This commit is contained in:
Stefan Roese 2010-07-21 11:08:16 +02:00
parent eab9800182
commit 897d6abc50
1 changed files with 4 additions and 4 deletions
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8
arch/powerpc/include/asm/ppc4xx-sdram.h
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@ -363,6 +363,7 @@
/*
* Memory controller registers
*/
#ifdef CONFIG_405EX
#define SDRAM_BESR 0x00 /* PLB bus error status (read/clear) */
#define SDRAM_BESRT 0x01 /* PLB bus error status (test/set) */
#define SDRAM_BEARL 0x02 /* PLB bus error address low */
@ -371,11 +372,10 @@
#define SDRAM_WMIRQT 0x07 /* PLB write master interrupt (test/set) */
#define SDRAM_PLBOPT 0x08 /* PLB slave options */
#define SDRAM_PUABA 0x09 /* PLB upper address base */
#ifndef CONFIG_405EX
#define SDRAM_MCSTAT 0x14 /* memory controller status */
#else
#define SDRAM_MCSTAT 0x1F /* memory controller status */
#endif
#else /* CONFIG_405EX */
#define SDRAM_MCSTAT 0x14 /* memory controller status */
#endif /* CONFIG_405EX */
#define SDRAM_MCOPT1 0x20 /* memory controller options 1 */
#define SDRAM_MCOPT2 0x21 /* memory controller options 2 */
#define SDRAM_MODT0 0x22 /* on die termination for bank 0 */