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https://github.com/brain-hackers/u-boot-brain
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imx: Move some i.MX common functions into the imx-common directory
This patch moves the following functions into the imx-common directory: - mxs_wait_mask_set() - mxs_wait_mask_clr() - mxs_reset_block() These are currently used by i.MX28. But the upcoming GPMI NAND port for i.MX6 will also use these functions. So lets move them to a common location to re-use them. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
This commit is contained in:
Stefan Roese
Stefano Babic
parent
0499218dbc
commit
8870e45996
2
Makefile
2
Makefile
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@ -331,7 +331,7 @@ ifneq ($(CONFIG_AM33XX)$(CONFIG_OMAP34XX)$(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX)$(C
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LIBS-y += $(CPUDIR)/omap-common/libomap-common.o
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endif
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ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35))
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ifneq (,$(filter $(SOC), mx25 mx27 mx5 mx6 mx31 mx35 mxs))
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LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
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endif
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@ -39,12 +39,6 @@
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DECLARE_GLOBAL_DATA_PTR;
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/* 1 second delay should be plenty of time for block reset. */
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#define RESET_MAX_TIMEOUT 1000000
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#define MXS_BLOCK_SFTRST (1 << 31)
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#define MXS_BLOCK_CLKGATE (1 << 30)
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/* Lowlevel init isn't used on i.MX28, so just have a dummy here */
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inline void lowlevel_init(void) {}
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@ -82,63 +76,6 @@ void enable_caches(void)
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#endif
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}
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int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
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int timeout)
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{
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while (--timeout) {
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if ((readl(®->reg) & mask) == mask)
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break;
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udelay(1);
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}
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return !timeout;
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}
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int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
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int timeout)
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{
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while (--timeout) {
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if ((readl(®->reg) & mask) == 0)
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break;
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udelay(1);
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}
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return !timeout;
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}
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int mxs_reset_block(struct mxs_register_32 *reg)
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{
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/* Clear SFTRST */
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writel(MXS_BLOCK_SFTRST, ®->reg_clr);
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if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
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return 1;
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/* Clear CLKGATE */
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writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
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/* Set SFTRST */
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writel(MXS_BLOCK_SFTRST, ®->reg_set);
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/* Wait for CLKGATE being set */
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if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
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return 1;
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/* Clear SFTRST */
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writel(MXS_BLOCK_SFTRST, ®->reg_clr);
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if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
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return 1;
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/* Clear CLKGATE */
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writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
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if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
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return 1;
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return 0;
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}
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void mx28_fixup_vt(uint32_t start_addr)
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{
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uint32_t *vt = (uint32_t *)0x20;
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@ -31,6 +31,9 @@ ifeq ($(SOC),$(filter $(SOC),mx5 mx6))
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COBJS-y = iomux-v3.o timer.o cpu.o speed.o
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COBJS-$(CONFIG_I2C_MXC) += i2c-mxv7.o
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endif
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ifeq ($(SOC),$(filter $(SOC),mx6 mxs))
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COBJS-y += misc.o
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endif
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COBJS-$(CONFIG_CMD_BMODE) += cmd_bmode.o
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COBJS-$(CONFIG_CMD_HDMIDETECT) += cmd_hdmidet.o
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COBJS := $(sort $(COBJS-y))
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84
arch/arm/imx-common/misc.c
Normal file
84
arch/arm/imx-common/misc.c
Normal file
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@ -0,0 +1,84 @@
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/*
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* Copyright 2013 Stefan Roese <sr@denx.de>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <common.h>
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#include <asm/errno.h>
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#include <asm/io.h>
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#include <asm/imx-common/regs-common.h>
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/* 1 second delay should be plenty of time for block reset. */
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#define RESET_MAX_TIMEOUT 1000000
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#define MXS_BLOCK_SFTRST (1 << 31)
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#define MXS_BLOCK_CLKGATE (1 << 30)
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int mxs_wait_mask_set(struct mxs_register_32 *reg, uint32_t mask, unsigned
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int timeout)
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{
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while (--timeout) {
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if ((readl(®->reg) & mask) == mask)
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break;
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udelay(1);
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}
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return !timeout;
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}
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int mxs_wait_mask_clr(struct mxs_register_32 *reg, uint32_t mask, unsigned
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int timeout)
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{
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while (--timeout) {
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if ((readl(®->reg) & mask) == 0)
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break;
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udelay(1);
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}
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return !timeout;
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}
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int mxs_reset_block(struct mxs_register_32 *reg)
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{
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/* Clear SFTRST */
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writel(MXS_BLOCK_SFTRST, ®->reg_clr);
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if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
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return 1;
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/* Clear CLKGATE */
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writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
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/* Set SFTRST */
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writel(MXS_BLOCK_SFTRST, ®->reg_set);
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/* Wait for CLKGATE being set */
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if (mxs_wait_mask_set(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
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return 1;
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/* Clear SFTRST */
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writel(MXS_BLOCK_SFTRST, ®->reg_clr);
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if (mxs_wait_mask_clr(reg, MXS_BLOCK_SFTRST, RESET_MAX_TIMEOUT))
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return 1;
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/* Clear CLKGATE */
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writel(MXS_BLOCK_CLKGATE, ®->reg_clr);
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if (mxs_wait_mask_clr(reg, MXS_BLOCK_CLKGATE, RESET_MAX_TIMEOUT))
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return 1;
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return 0;
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}
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@ -24,6 +24,8 @@
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#ifndef _SYS_PROTO_H_
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#define _SYS_PROTO_H_
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#include <asm/imx-common/regs-common.h>
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#define MXC_CPU_MX51 0x51
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#define MXC_CPU_MX53 0x53
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#define MXC_CPU_MX6SL 0x60
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@ -46,4 +48,12 @@ void set_vddsoc(u32 mv);
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int fecmxc_initialize(bd_t *bis);
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u32 get_ahb_clk(void);
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u32 get_periph_clk(void);
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int mxs_reset_block(struct mxs_register_32 *reg);
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int mxs_wait_mask_set(struct mxs_register_32 *reg,
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uint32_t mask,
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unsigned int timeout);
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int mxs_wait_mask_clr(struct mxs_register_32 *reg,
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uint32_t mask,
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unsigned int timeout);
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#endif
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@ -94,6 +94,10 @@ LIBS-y += arch/$(ARCH)/cpu/tegra-common/libcputegra-common.o
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LIBS-y += $(CPUDIR)/tegra-common/libtegra-common.o
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endif
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ifneq ($(CONFIG_MX23),)
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LIBS-y += arch/$(ARCH)/imx-common/libimx-common.o
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endif
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# Add GCC lib
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ifeq ("$(USE_PRIVATE_LIBGCC)", "yes")
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PLATFORM_LIBGCC = $(SPLTREE)/arch/$(ARCH)/lib/libgcc.o
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