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sunxi: Add support for A33 PLL11 (second DRAM pll)
Add support for the new second DRAM PLL found on the A33 SoC. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
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5e6bacdb84
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@ -170,6 +170,24 @@ void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
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udelay(5500);
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udelay(5500);
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}
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}
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#ifdef CONFIG_MACH_SUN8I_A33
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void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
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{
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struct sunxi_ccm_reg * const ccm =
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(struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
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if (sigma_delta_enable)
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writel(CCM_PLL11_PATTERN, &ccm->pll5_pattern_cfg);
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writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD |
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(sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) |
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CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg);
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while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD)
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;
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}
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#endif
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unsigned int clock_get_pll6(void)
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unsigned int clock_get_pll6(void)
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{
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{
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struct sunxi_ccm_reg *const ccm =
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struct sunxi_ccm_reg *const ccm =
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@ -31,7 +31,7 @@ struct sunxi_ccm_reg {
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u32 mipi_pll_cfg; /* 0x40 MIPI pll control */
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u32 mipi_pll_cfg; /* 0x40 MIPI pll control */
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u32 pll9_cfg; /* 0x44 pll9 control */
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u32 pll9_cfg; /* 0x44 pll9 control */
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u32 pll10_cfg; /* 0x48 pll10 control */
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u32 pll10_cfg; /* 0x48 pll10 control */
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u32 reserved8;
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u32 pll11_cfg; /* 0x4c pll11 (ddr1) control (A33 only) */
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u32 cpu_axi_cfg; /* 0x50 CPU/AXI divide ratio */
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u32 cpu_axi_cfg; /* 0x50 CPU/AXI divide ratio */
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u32 ahb1_apb1_div; /* 0x54 AHB1/APB1 divide ratio */
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u32 ahb1_apb1_div; /* 0x54 AHB1/APB1 divide ratio */
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u32 apb2_div; /* 0x58 APB2 divide ratio */
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u32 apb2_div; /* 0x58 APB2 divide ratio */
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@ -63,7 +63,8 @@ struct sunxi_ccm_reg {
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u32 reserved12[7];
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u32 reserved12[7];
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u32 mdfs_clk_cfg; /* 0xf0 MDFS clock control */
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u32 mdfs_clk_cfg; /* 0xf0 MDFS clock control */
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u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */
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u32 dram_clk_cfg; /* 0xf4 DRAM configuration clock control */
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u32 reserved13[2];
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u32 dram_pll_cfg; /* 0xf8 PLL_DDR cfg register, A33 only */
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u32 mbus_reset; /* 0xfc MBUS reset control, A33 only */
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u32 dram_clk_gate; /* 0x100 DRAM module gating */
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u32 dram_clk_gate; /* 0x100 DRAM module gating */
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u32 be0_clk_cfg; /* 0x104 BE0 module clock */
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u32 be0_clk_cfg; /* 0x104 BE0 module clock */
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u32 be1_clk_cfg; /* 0x108 BE1 module clock */
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u32 be1_clk_cfg; /* 0x108 BE1 module clock */
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@ -126,7 +127,9 @@ struct sunxi_ccm_reg {
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u32 mipi_pattern_cfg; /* 0x2a0 MIPI Pattern config */
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u32 mipi_pattern_cfg; /* 0x2a0 MIPI Pattern config */
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u32 pll9_pattern_cfg; /* 0x2a4 PLL9 Pattern config */
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u32 pll9_pattern_cfg; /* 0x2a4 PLL9 Pattern config */
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u32 pll10_pattern_cfg; /* 0x2a8 PLL10 Pattern config */
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u32 pll10_pattern_cfg; /* 0x2a8 PLL10 Pattern config */
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u32 reserved22[5];
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u32 pll11_pattern_cfg0; /* 0x2ac PLL11 Pattern config0, A33 only */
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u32 pll11_pattern_cfg1; /* 0x2b0 PLL11 Pattern config0, A33 only */
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u32 reserved22[3];
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u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */
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u32 ahb_reset0_cfg; /* 0x2c0 AHB1 Reset 0 config */
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u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */
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u32 ahb_reset1_cfg; /* 0x2c4 AHB1 Reset 1 config */
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u32 ahb_reset2_cfg; /* 0x2c8 AHB1 Reset 2 config */
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u32 ahb_reset2_cfg; /* 0x2c8 AHB1 Reset 2 config */
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@ -195,6 +198,11 @@ struct sunxi_ccm_reg {
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#define CCM_PLL6_CTRL_K_SHIFT 4
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#define CCM_PLL6_CTRL_K_SHIFT 4
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#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT)
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#define CCM_PLL6_CTRL_K_MASK (0x3 << CCM_PLL6_CTRL_K_SHIFT)
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#define CCM_PLL11_CTRL_N(n) ((((n) - 1) & 0x3f) << 8)
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#define CCM_PLL11_CTRL_SIGMA_DELTA_EN (0x1 << 24)
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#define CCM_PLL11_CTRL_UPD (0x1 << 30)
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#define CCM_PLL11_CTRL_EN (0x1 << 31)
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#define AHB1_ABP1_DIV_DEFAULT 0x00002020
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#define AHB1_ABP1_DIV_DEFAULT 0x00002020
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#define AXI_GATE_OFFSET_DRAM 0
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#define AXI_GATE_OFFSET_DRAM 0
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@ -216,6 +224,7 @@ struct sunxi_ccm_reg {
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/* ahb_gate1 offsets */
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/* ahb_gate1 offsets */
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#define AHB_GATE_OFFSET_DRC0 25
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#define AHB_GATE_OFFSET_DRC0 25
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#define AHB_GATE_OFFSET_DE_FE0 14
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#define AHB_GATE_OFFSET_DE_BE0 12
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#define AHB_GATE_OFFSET_DE_BE0 12
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#define AHB_GATE_OFFSET_HDMI 11
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#define AHB_GATE_OFFSET_HDMI 11
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#define AHB_GATE_OFFSET_LCD1 5
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#define AHB_GATE_OFFSET_LCD1 5
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@ -248,12 +257,23 @@ struct sunxi_ccm_reg {
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#define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */
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#define MDFS_CLK_DEFAULT 0x81000002 /* PLL6 / 3 */
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#define CCM_DRAMCLK_CFG_DIV(x) ((x - 1) << 0)
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#define CCM_DRAMCLK_CFG_DIV_MASK (0xf << 0)
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#define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8)
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#define CCM_DRAMCLK_CFG_DIV0(x) ((x - 1) << 8)
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#define CCM_DRAMCLK_CFG_DIV0_MASK (0xf << 8)
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#define CCM_DRAMCLK_CFG_DIV0_MASK (0xf << 8)
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#define CCM_DRAMCLK_CFG_UPD (0x1 << 16)
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#define CCM_DRAMCLK_CFG_UPD (0x1 << 16)
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#define CCM_DRAMCLK_CFG_RST (0x1 << 31)
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#define CCM_DRAMCLK_CFG_RST (0x1 << 31)
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#define CCM_DRAMPLL_CFG_SRC_PLL5 (0x0 << 16) /* Select PLL5 (DDR0) */
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#define CCM_DRAMPLL_CFG_SRC_PLL11 (0x1 << 16) /* Select PLL11 (DDR1) */
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#define CCM_DRAMPLL_CFG_SRC_MASK (0x1 << 16)
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#define CCM_MBUS_RESET_RESET (0x1 << 31)
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#define CCM_DRAM_GATE_OFFSET_DE_FE0 24
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#define CCM_DRAM_GATE_OFFSET_DE_FE1 25
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#define CCM_DRAM_GATE_OFFSET_DE_BE0 26
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#define CCM_DRAM_GATE_OFFSET_DE_BE0 26
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#define CCM_DRAM_GATE_OFFSET_DE_BE1 27
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#define CCM_LCD_CH0_CTRL_PLL3 (0 << 24)
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#define CCM_LCD_CH0_CTRL_PLL3 (0 << 24)
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#define CCM_LCD_CH0_CTRL_PLL7 (1 << 24)
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#define CCM_LCD_CH0_CTRL_PLL7 (1 << 24)
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@ -285,8 +305,10 @@ struct sunxi_ccm_reg {
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#else
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#else
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#define MBUS_CLK_DEFAULT 0x81000003 /* PLL6 / 4 */
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#define MBUS_CLK_DEFAULT 0x81000003 /* PLL6 / 4 */
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#endif
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#endif
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#define MBUS_CLK_GATE (0x1 << 31)
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#define CCM_PLL5_PATTERN 0xd1303333
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#define CCM_PLL5_PATTERN 0xd1303333
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#define CCM_PLL11_PATTERN 0xf5860000
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/* ahb_reset0 offsets */
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/* ahb_reset0 offsets */
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#define AHB_RESET_OFFSET_GMAC 17
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#define AHB_RESET_OFFSET_GMAC 17
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@ -299,7 +321,9 @@ struct sunxi_ccm_reg {
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#define AHB_RESET_OFFSET_SS 5
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#define AHB_RESET_OFFSET_SS 5
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/* ahb_reset1 offsets */
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/* ahb_reset1 offsets */
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#define AHB_RESET_OFFSET_SAT 26
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#define AHB_RESET_OFFSET_DRC0 25
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#define AHB_RESET_OFFSET_DRC0 25
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#define AHB_RESET_OFFSET_DE_FE0 14
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#define AHB_RESET_OFFSET_DE_BE0 12
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#define AHB_RESET_OFFSET_DE_BE0 12
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#define AHB_RESET_OFFSET_HDMI 11
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#define AHB_RESET_OFFSET_HDMI 11
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#define AHB_RESET_OFFSET_LCD1 5
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#define AHB_RESET_OFFSET_LCD1 5
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@ -326,6 +350,7 @@ struct sunxi_ccm_reg {
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void clock_set_pll1(unsigned int hz);
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void clock_set_pll1(unsigned int hz);
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void clock_set_pll3(unsigned int hz);
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void clock_set_pll3(unsigned int hz);
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void clock_set_pll5(unsigned int clk, bool sigma_delta_enable);
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void clock_set_pll5(unsigned int clk, bool sigma_delta_enable);
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void clock_set_pll11(unsigned int clk, bool sigma_delta_enable);
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unsigned int clock_get_pll6(void);
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unsigned int clock_get_pll6(void);
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#endif
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#endif
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