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armv7: stronger barrier for cache-maintenance operations
set-way operations need a DSB after them to ensure the operation is complete. DMB may not be enough. Use DSB after all operations instead of DMB. Signed-off-by: Aneesh V <aneesh@ti.com>
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@ -81,8 +81,8 @@ static void v7_inval_dcache_level_setway(u32 level, u32 num_sets,
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: : "r" (setway));
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: : "r" (setway));
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}
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}
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}
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}
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/* DMB to make sure the operation is complete */
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/* DSB to make sure the operation is complete */
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CP15DMB;
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CP15DSB;
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}
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}
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static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
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static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
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@ -108,8 +108,8 @@ static void v7_clean_inval_dcache_level_setway(u32 level, u32 num_sets,
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: : "r" (setway));
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: : "r" (setway));
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}
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}
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}
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}
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/* DMB to make sure the operation is complete */
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/* DSB to make sure the operation is complete */
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CP15DMB;
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CP15DSB;
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}
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}
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static void v7_maint_dcache_level_setway(u32 level, u32 operation)
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static void v7_maint_dcache_level_setway(u32 level, u32 operation)
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@ -227,8 +227,8 @@ static void v7_dcache_maint_range(u32 start, u32 stop, u32 range_op)
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break;
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break;
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}
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}
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/* DMB to make sure the operation is complete */
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/* DSB to make sure the operation is complete */
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CP15DMB;
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CP15DSB;
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}
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}
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/* Invalidate TLB */
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/* Invalidate TLB */
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