ARC: Improve identification of ARC cores
1. Try to guess a ARC core template that was used
i.e. not just name a core family but something more
menaingful like "ARC HS38", "ARC EM11D" etc.
We do it checking availability of the key differentiation
features like:
- Caches (we actually only check for L1 I$ fpr simplicity)
- XY-memory
- DSP extensions etc.
2. Identify ARC subsystems
3. Print core clock frequency
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
This commit is contained in:
Alexey Brodkin
Alexey Brodkin
parent
ad74bb4fe3
commit
85e529fdfc
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@ -16,6 +16,20 @@
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* access: "lr"/"sr".
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*/
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/*
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* Typically 8 least significant bits of Build Configuration Register (BCR)
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* describe version of the HW block in question. Moreover if decoded version
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* is 0 this means given HW block is absent - this is especially useful because
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* we may safely read BRC regardless HW block existence while an attempt to
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* access any other AUX regs associated with this HW block lead to imediate
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* "instruction error" exception.
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*
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* I.e. before using any cofigurable HW block it's required to make sure it
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* exists at all, and for that we introduce a special macro below.
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*/
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#define ARC_BCR_VERSION_MASK GENMASK(7, 0)
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#define ARC_FEATURE_EXISTS(bcr) !!(__builtin_arc_lr(bcr) & ARC_BCR_VERSION_MASK)
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#define ARC_AUX_IDENTITY 0x04
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#define ARC_AUX_STATUS32 0x0a
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@ -73,7 +87,7 @@
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#define ARC_BCR_CLUSTER 0xcf
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/* MMU Management regs */
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#define ARC_AUX_MMU_BCR 0x06f
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#define ARC_AUX_MMU_BCR 0x6f
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/* IO coherency related auxiliary registers */
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#define ARC_AUX_IO_COH_ENABLE 0x500
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@ -81,6 +95,15 @@
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#define ARC_AUX_IO_COH_AP0_BASE 0x508
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#define ARC_AUX_IO_COH_AP0_SIZE 0x509
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/* XY-memory related */
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#define ARC_AUX_XY_BUILD 0x79
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/* DSP-extensions related auxiliary registers */
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#define ARC_AUX_DSP_BUILD 0x7A
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/* ARC Subsystems related auxiliary registers */
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#define ARC_AUX_SUBSYS_BUILD 0xF0
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#ifndef __ASSEMBLY__
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/* Accessors for auxiliary registers */
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#define read_aux_reg(reg) __builtin_arc_lr(reg)
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@ -4,6 +4,7 @@
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*/
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#include <common.h>
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#include <malloc.h>
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#include <asm/arcregs.h>
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#include <asm/cache.h>
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@ -35,34 +36,193 @@ int dram_init(void)
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}
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#ifdef CONFIG_DISPLAY_CPUINFO
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const char *decode_identity(void)
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const char *arc_700_version(int arcver, char *name, int name_len)
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{
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int arcver = read_aux_reg(ARC_AUX_IDENTITY) & 0xff;
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const char *arc_ver;
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switch (arcver) {
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/* ARCompact cores */
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case 0x32: return "ARC 700 v4.4-4.5";
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case 0x33: return "ARC 700 v4.6-v4.9";
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case 0x34: return "ARC 700 v4.10";
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case 0x35: return "ARC 700 v4.11";
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/* ARCv2 cores */
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case 0x41: return "ARC EM v1.1a";
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case 0x42: return "ARC EM v3.0";
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case 0x43: return "ARC EM v4.0";
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case 0x50: return "ARC HS v1.0";
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case 0x51: return "ARC EM v2.0";
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case 0x52: return "ARC EM v2.1";
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case 0x53: return "ARC HS v3.0";
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case 0x54: return "ARC HS v4.0";
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default: return "Unknown ARC core";
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case 0x32:
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arc_ver = "v4.4-4.5";
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break;
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case 0x33:
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arc_ver = "v4.6-v4.9";
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break;
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case 0x34:
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arc_ver = "v4.10";
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break;
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case 0x35:
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arc_ver = "v4.11";
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break;
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default:
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arc_ver = "unknown version";
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}
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snprintf(name, name_len, "ARC 700 %s", arc_ver);
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return name;
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}
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struct em_template_t {
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const bool cache;
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const bool dsp;
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const bool xymem;
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const char name[8];
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};
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static const struct em_template_t em_versions[] = {
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{false, false, false, "EM4"},
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{true, false, false, "EM6"},
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{false, true, false, "EM5D"},
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{true, true, false, "EM7D"},
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{false, true, true, "EM9D"},
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{true, true, true, "EM11D"},
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};
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const char *arc_em_version(int arcver, char *name, int name_len)
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{
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const char *arc_name = "EM";
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const char *arc_ver;
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bool cache = ARC_FEATURE_EXISTS(ARC_BCR_IC_BUILD);
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bool dsp = ARC_FEATURE_EXISTS(ARC_AUX_DSP_BUILD);
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bool xymem = ARC_FEATURE_EXISTS(ARC_AUX_XY_BUILD);
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int i;
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for (i = 0; i++ < sizeof(em_versions) / sizeof(struct em_template_t);) {
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if (em_versions[i].cache == cache &&
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em_versions[i].dsp == dsp &&
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em_versions[i].xymem == xymem) {
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arc_name = em_versions[i].name;
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break;
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}
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}
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switch (arcver) {
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case 0x41:
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arc_ver = "v1.1a";
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break;
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case 0x42:
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arc_ver = "v3.0";
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break;
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case 0x43:
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arc_ver = "v4.0";
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break;
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case 0x44:
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arc_ver = "v5.0";
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break;
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default:
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arc_ver = "unknown version";
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}
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snprintf(name, name_len, "ARC %s %s", arc_name, arc_ver);
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return name;
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}
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struct hs_template_t {
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const bool cache;
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const bool mmu;
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const bool dual_issue;
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const bool dsp;
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const char name[8];
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};
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static const struct hs_template_t hs_versions[] = {
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{false, false, false, false, "HS34"},
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{true, false, false, false, "HS36"},
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{true, true, false, false, "HS38"},
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{false, false, true, false, "HS44"},
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{true, false, true, false, "HS46"},
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{true, true, true, false, "HS48"},
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{false, false, true, true, "HS45D"},
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{true, false, true, true, "HS47D"},
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};
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const char *arc_hs_version(int arcver, char *name, int name_len)
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{
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const char *arc_name = "HS";
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const char *arc_ver;
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bool cache = ARC_FEATURE_EXISTS(ARC_BCR_IC_BUILD);
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bool dsp = ARC_FEATURE_EXISTS(ARC_AUX_DSP_BUILD);
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bool mmu = !!read_aux_reg(ARC_AUX_MMU_BCR);
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bool dual_issue = arcver == 0x54 ? true : false;
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int i;
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for (i = 0; i++ < sizeof(hs_versions) / sizeof(struct hs_template_t);) {
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if (hs_versions[i].cache == cache &&
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hs_versions[i].mmu == mmu &&
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hs_versions[i].dual_issue == dual_issue &&
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hs_versions[i].dsp == dsp) {
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arc_name = hs_versions[i].name;
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break;
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}
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}
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switch (arcver) {
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case 0x50:
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arc_ver = "v1.0";
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break;
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case 0x51:
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arc_ver = "v2.0";
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break;
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case 0x52:
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arc_ver = "v2.1c";
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break;
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case 0x53:
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arc_ver = "v3.0";
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break;
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case 0x54:
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arc_ver = "v4.0";
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break;
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default:
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arc_ver = "unknown version";
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}
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snprintf(name, name_len, "ARC %s %s", arc_name, arc_ver);
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return name;
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}
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const char *decode_identity(void)
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{
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#define MAX_CPU_NAME_LEN 64
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int arcver = read_aux_reg(ARC_AUX_IDENTITY) & 0xff;
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char *name = malloc(MAX_CPU_NAME_LEN);
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if (arcver >= 0x50)
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return arc_hs_version(arcver, name, MAX_CPU_NAME_LEN);
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else if (arcver >= 0x40)
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return arc_em_version(arcver, name, MAX_CPU_NAME_LEN);
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else if (arcver >= 0x30)
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return arc_700_version(arcver, name, MAX_CPU_NAME_LEN);
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else
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return "Unknown ARC core";
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}
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const char *decode_subsystem(void)
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{
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int subsys_type = read_aux_reg(ARC_AUX_SUBSYS_BUILD) & GENMASK(3, 0);
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switch (subsys_type) {
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case 0: return NULL;
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case 2: return "ARC Sensor & Control IP Subsystem";
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case 3: return "ARC Data Fusion IP Subsystem";
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case 4: return "ARC Secure Subsystem";
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default: return "Unknown subsystem";
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};
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}
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__weak int print_cpuinfo(void)
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{
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printf("CPU: %s\n", decode_identity());
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const char *subsys_name = decode_subsystem();
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char mhz[8];
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printf("CPU: %s at %s MHz\n", decode_identity(),
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strmhz(mhz, gd->cpu_clk));
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if (subsys_name)
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printf("Subsys:%s\n", subsys_name);
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return 0;
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}
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#endif /* CONFIG_DISPLAY_CPUINFO */
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