mirror of
https://github.com/brain-hackers/u-boot-brain
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Merge branch '2019-12-13-master-imports'
- Assorted minor fixes
This commit is contained in:
commit
85432c69da
2
.mailmap
2
.mailmap
@ -20,6 +20,8 @@ Allen Martin <amartin@nvidia.com>
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Andreas Bießmann <andreas.devel@googlemail.com>
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Andreas Bießmann <andreas@biessmann.org>
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Aneesh V <aneesh@ti.com>
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Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@bootlin.com>
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Boris Brezillon <bbrezillon@kernel.org> <boris.brezillon@free-electrons.com>
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Dirk Behme <dirk.behme@googlemail.com>
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Fabio Estevam <fabio.estevam@nxp.com>
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Jagan Teki <402jagan@gmail.com>
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1
Documentation/.gitignore
vendored
1
Documentation/.gitignore
vendored
@ -1 +0,0 @@
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*.pyc
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@ -1,66 +0,0 @@
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The following properties are common to the Ethernet controllers:
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NOTE: All 'phy*' properties documented below are Ethernet specific. For the
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generic PHY 'phys' property, see
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Documentation/devicetree/bindings/phy/phy-bindings.txt.
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- local-mac-address: array of 6 bytes, specifies the MAC address that was
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assigned to the network device;
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- mac-address: array of 6 bytes, specifies the MAC address that was last used by
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the boot program; should be used in cases where the MAC address assigned to
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the device by the boot program is different from the "local-mac-address"
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property;
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- nvmem-cells: phandle, reference to an nvmem node for the MAC address;
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- nvmem-cell-names: string, should be "mac-address" if nvmem is to be used;
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- max-speed: number, specifies maximum speed in Mbit/s supported by the device;
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- max-frame-size: number, maximum transfer unit (IEEE defined MTU), rather than
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the maximum frame size (there's contradiction in the Devicetree
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Specification).
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- phy-mode: string, operation mode of the PHY interface. This is now a de-facto
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standard property; supported values are:
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* "internal"
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* "mii"
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* "gmii"
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* "sgmii"
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* "qsgmii"
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* "tbi"
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* "rev-mii"
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* "rmii"
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* "rgmii" (RX and TX delays are added by the MAC when required)
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* "rgmii-id" (RGMII with internal RX and TX delays provided by the PHY, the
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MAC should not add the RX or TX delays in this case)
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* "rgmii-rxid" (RGMII with internal RX delay provided by the PHY, the MAC
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should not add an RX delay in this case)
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* "rgmii-txid" (RGMII with internal TX delay provided by the PHY, the MAC
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should not add an TX delay in this case)
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* "rtbi"
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* "smii"
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* "xgmii"
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* "trgmii"
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* "2000base-x",
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* "2500base-x",
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* "rxaui"
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* "xaui"
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* "10gbase-kr" (10GBASE-KR, XFI, SFI)
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- phy-connection-type: the same as "phy-mode" property but described in the
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Devicetree Specification;
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- phy-handle: phandle, specifies a reference to a node representing a PHY
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device; this property is described in the Devicetree Specification and so
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preferred;
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- phy: the same as "phy-handle" property, not recommended for new bindings.
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- phy-device: the same as "phy-handle" property, not recommended for new
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bindings.
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- rx-fifo-depth: the size of the controller's receive fifo in bytes. This
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is used for components that can have configurable receive fifo sizes,
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and is useful for determining certain configuration settings such as
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flow control thresholds.
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- tx-fifo-depth: the size of the controller's transmit fifo in bytes. This
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is used for components that can have configurable fifo sizes.
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- managed: string, specifies the PHY management type. Supported values are:
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"auto", "in-band-status". "auto" is the default, it usess MDIO for
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management if fixed-link is not specified.
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Child nodes of the Ethernet controller are typically the individual PHY devices
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connected via the MDIO bus (sometimes the MDIO bus controller is separate).
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They are described in the phy.txt file in this same directory.
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For non-MDIO PHY management see fixed-link.txt.
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@ -266,12 +266,14 @@
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};
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&cpsw_emac0 {
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phy_id = <&davinci_mdio>, <1>;
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phy-handle = <ðphy0>;
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phy-mode = "rmii";
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ti,ledcr = <0x0480>;
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};
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&cpsw_emac1 {
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phy_id = <&davinci_mdio>, <3>;
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phy-handle = <ðphy1>;
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phy-mode = "rmii";
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ti,ledcr = <0x0480>;
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@ -221,11 +221,13 @@
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};
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&cpsw_emac0 {
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phy_id = <&davinci_mdio>, <1>;
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phy-handle = <ðphy0>;
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phy-mode = "mii";
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};
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&cpsw_emac1 {
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phy_id = <&davinci_mdio>, <2>;
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phy-handle = <ðphy1>;
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phy-mode = "mii";
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};
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@ -34,6 +34,7 @@ CONFIG_CMD_SPL=y
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_NAND=y
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_BOOTP_DNS2=y
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CONFIG_CMD_MTDPARTS=y
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CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
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CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),2m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
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@ -85,6 +86,7 @@ CONFIG_DM_SPI_FLASH=y
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CONFIG_SF_DEFAULT_MODE=0
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CONFIG_SF_DEFAULT_SPEED=76800000
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_PHY_TI=y
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CONFIG_DM_ETH=y
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CONFIG_PHY_GIGE=y
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CONFIG_MII=y
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@ -37,6 +37,7 @@ CONFIG_SPL_USB_GADGET=y
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CONFIG_SPL_DFU=y
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# CONFIG_CMD_FLASH is not set
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CONFIG_CMD_NAND=y
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CONFIG_BOOTP_DNS2=y
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CONFIG_CMD_MTDPARTS=y
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CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
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CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),2m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
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@ -88,6 +89,7 @@ CONFIG_DM_SPI_FLASH=y
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CONFIG_SF_DEFAULT_MODE=0
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CONFIG_SF_DEFAULT_SPEED=76800000
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_PHY_TI=y
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CONFIG_DM_ETH=y
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CONFIG_PHY_GIGE=y
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CONFIG_MII=y
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@ -40,6 +40,7 @@ CONFIG_SPL_DFU=y
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CONFIG_SPL_YMODEM_SUPPORT=y
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# CONFIG_CMD_FLASH is not set
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# CONFIG_CMD_SETEXPR is not set
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CONFIG_BOOTP_DNS2=y
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CONFIG_OF_CONTROL=y
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CONFIG_SPL_OF_CONTROL=y
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CONFIG_DEFAULT_DEVICE_TREE="dra7-evm"
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@ -86,6 +87,7 @@ CONFIG_SF_DEFAULT_MODE=0
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CONFIG_SF_DEFAULT_SPEED=76800000
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CONFIG_SPI_FLASH_BAR=y
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CONFIG_SPI_FLASH_SPANSION=y
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CONFIG_PHY_TI=y
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CONFIG_DM_ETH=y
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CONFIG_PHY_GIGE=y
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CONFIG_MII=y
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@ -186,7 +186,7 @@ CONFIG_DM_RESET=y
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CONFIG_DM_SERIAL=y
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CONFIG_SYS_NS16550=y
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CONFIG_SYSRESET=y
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CONFIG_SYSRESET_MCP83XX=y
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CONFIG_SYSRESET_MPC83XX=y
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CONFIG_TIMER=y
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CONFIG_MPC83XX_TIMER=y
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CONFIG_TPM_ATMEL_TWI=y
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@ -1,25 +1,66 @@
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The following properties are common to the Ethernet controllers:
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NOTE: All 'phy*' properties documented below are Ethernet specific. For the
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generic PHY 'phys' property, see
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Documentation/devicetree/bindings/phy/phy-bindings.txt.
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- local-mac-address: array of 6 bytes, specifies the MAC address that was
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assigned to the network device;
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- mac-address: array of 6 bytes, specifies the MAC address that was last used by
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the boot program; should be used in cases where the MAC address assigned to
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the device by the boot program is different from the "local-mac-address"
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property;
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- nvmem-cells: phandle, reference to an nvmem node for the MAC address;
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- nvmem-cell-names: string, should be "mac-address" if nvmem is to be used;
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- max-speed: number, specifies maximum speed in Mbit/s supported by the device;
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- max-frame-size: number, maximum transfer unit (IEEE defined MTU), rather than
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the maximum frame size (there's contradiction in ePAPR).
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- phy-mode: string, operation mode of the PHY interface; supported values are
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"mii", "gmii", "sgmii", "qsgmii", "tbi", "rev-mii", "rmii", "rgmii", "rgmii-id",
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"rgmii-rxid", "rgmii-txid", "rtbi", "smii", "xgmii"; this is now a de-facto
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standard property;
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- phy-connection-type: the same as "phy-mode" property but described in ePAPR;
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the maximum frame size (there's contradiction in the Devicetree
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Specification).
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- phy-mode: string, operation mode of the PHY interface. This is now a de-facto
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standard property; supported values are:
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* "internal"
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* "mii"
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* "gmii"
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* "sgmii"
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* "qsgmii"
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* "tbi"
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* "rev-mii"
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* "rmii"
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* "rgmii" (RX and TX delays are added by the MAC when required)
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* "rgmii-id" (RGMII with internal RX and TX delays provided by the PHY, the
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MAC should not add the RX or TX delays in this case)
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* "rgmii-rxid" (RGMII with internal RX delay provided by the PHY, the MAC
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should not add an RX delay in this case)
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* "rgmii-txid" (RGMII with internal TX delay provided by the PHY, the MAC
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should not add an TX delay in this case)
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* "rtbi"
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* "smii"
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* "xgmii"
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* "trgmii"
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* "2000base-x",
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* "2500base-x",
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* "rxaui"
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* "xaui"
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* "10gbase-kr" (10GBASE-KR, XFI, SFI)
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- phy-connection-type: the same as "phy-mode" property but described in the
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Devicetree Specification;
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- phy-handle: phandle, specifies a reference to a node representing a PHY
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device; this property is described in ePAPR and so preferred;
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device; this property is described in the Devicetree Specification and so
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preferred;
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- phy: the same as "phy-handle" property, not recommended for new bindings.
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- phy-device: the same as "phy-handle" property, not recommended for new
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bindings.
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- rx-fifo-depth: the size of the controller's receive fifo in bytes. This
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is used for components that can have configurable receive fifo sizes,
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and is useful for determining certain configuration settings such as
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flow control thresholds.
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- tx-fifo-depth: the size of the controller's transmit fifo in bytes. This
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is used for components that can have configurable fifo sizes.
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- managed: string, specifies the PHY management type. Supported values are:
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"auto", "in-band-status". "auto" is the default, it usess MDIO for
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management if fixed-link is not specified.
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Child nodes of the Ethernet controller are typically the individual PHY devices
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connected via the MDIO bus (sometimes the MDIO bus controller is separate).
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They are described in the phy.txt file in this same directory.
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For non-MDIO PHY management see fixed-link.txt.
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@ -167,6 +167,68 @@ For RSA the following are mandatory:
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- rsa,r-squared: (2^num-bits)^2 as a big-endian multi-word integer
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- rsa,n0-inverse: -1 / modulus[0] mod 2^32
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These parameters can be added to a binary device tree using parameter -K of the
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mkimage command::
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tools/mkimage -f fit.its -K control.dtb -k keys -r image.fit
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Here is an example of a generated device tree node::
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signature {
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key-dev {
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required = "conf";
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algo = "sha256,rsa2048";
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rsa,r-squared = <0xb76d1acf 0xa1763ca5 0xeb2f126
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0x742edc80 0xd3f42177 0x9741d9d9
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0x35bb476e 0xff41c718 0xd3801430
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0xf22537cb 0xa7e79960 0xae32a043
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0x7da1427a 0x341d6492 0x3c2762f5
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0xaac04726 0x5b262d96 0xf984e86d
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0xb99443c7 0x17080c33 0x940f6892
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0xd57a95d1 0x6ea7b691 0xc5038fa8
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0x6bb48a6e 0x73f1b1ea 0x37160841
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0xe05715ce 0xa7c45bbd 0x690d82d5
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0x99c2454c 0x6ff117b3 0xd830683b
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0x3f81c9cf 0x1ca38a91 0x0c3392e4
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0xd817c625 0x7b8e9a24 0x175b89ea
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0xad79f3dc 0x4d50d7b4 0x9d4e90f8
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0xad9e2939 0xc165d6a4 0x0ada7e1b
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0xfb1bf495 0xfc3131c2 0xb8c6e604
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0xc2761124 0xf63de4a6 0x0e9565f9
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0xc8e53761 0x7e7a37a5 0xe99dcdae
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0x9aff7e1e 0xbd44b13d 0x6b0e6aa4
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0x038907e4 0x8e0d6850 0xef51bc20
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0xf73c94af 0x88bea7b1 0xcbbb1b30
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0xd024b7f3>;
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rsa,modulus = <0xc0711d6cb 0x9e86db7f 0x45986dbe
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0x023f1e8c9 0xe1a4c4d0 0x8a0dfdc9
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||||
0x023ba0c48 0x06815f6a 0x5caa0654
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||||
0x07078c4b7 0x3d154853 0x40729023
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||||
0x0b007c8fe 0x5a3647e5 0x23b41e20
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||||
0x024720591 0x66915305 0x0e0b29b0
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||||
0x0de2ad30d 0x8589430f 0xb1590325
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||||
0x0fb9f5d5e 0x9eba752a 0xd88e6de9
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||||
0x056b3dcc6 0x9a6b8e61 0x6784f61f
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||||
0x000f39c21 0x5eec6b33 0xd78e4f78
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||||
0x0921a305f 0xaa2cc27e 0x1ca917af
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||||
0x06e1134f4 0xd48cac77 0x4e914d07
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||||
0x0f707aa5a 0x0d141f41 0x84677f1d
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||||
0x0ad47a049 0x028aedb6 0xd5536fcf
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||||
0x03fef1e4f 0x133a03d2 0xfd7a750a
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||||
0x0f9159732 0xd207812e 0x6a807375
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||||
0x06434230d 0xc8e22dad 0x9f29b3d6
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||||
0x07c44ac2b 0xfa2aad88 0xe2429504
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||||
0x041febd41 0x85d0d142 0x7b194d65
|
||||
0x06e5d55ea 0x41116961 0xf3181dde
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||||
0x068bf5fbc 0x3dd82047 0x00ee647e
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||||
0x0d7a44ab3>;
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rsa,exponent = <0x00 0x10001>;
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rsa,n0-inverse = <0xb3928b85>;
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||||
rsa,num-bits = <0x800>;
|
||||
key-name-hint = "dev";
|
||||
};
|
||||
};
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||||
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||||
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||||
Signed Configurations
|
||||
---------------------
|
||||
|
@ -119,7 +119,7 @@ config SYSRESET_TPL_X86
|
||||
help
|
||||
Reboot support for generic x86 processor reset in TPL.
|
||||
|
||||
config SYSRESET_MCP83XX
|
||||
config SYSRESET_MPC83XX
|
||||
bool "Enable support MPC83xx SoC family reboot driver"
|
||||
help
|
||||
Reboot support for NXP MPC83xx SoCs.
|
||||
|
@ -8,7 +8,7 @@ obj-$(CONFIG_ARCH_ROCKCHIP) += sysreset_rockchip.o
|
||||
obj-$(CONFIG_ARCH_STI) += sysreset_sti.o
|
||||
obj-$(CONFIG_SANDBOX) += sysreset_sandbox.o
|
||||
obj-$(CONFIG_SYSRESET_GPIO) += sysreset_gpio.o
|
||||
obj-$(CONFIG_SYSRESET_MCP83XX) += sysreset_mpc83xx.o
|
||||
obj-$(CONFIG_SYSRESET_MPC83XX) += sysreset_mpc83xx.o
|
||||
obj-$(CONFIG_SYSRESET_MICROBLAZE) += sysreset_microblaze.o
|
||||
obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
|
||||
obj-$(CONFIG_SYSRESET_SOCFPGA) += sysreset_socfpga.o
|
||||
|
@ -15,7 +15,6 @@
|
||||
|
||||
#ifndef __ASSEMBLY__ /* put C only stuff in this section */
|
||||
|
||||
typedef unsigned char uchar;
|
||||
typedef volatile unsigned long vu_long;
|
||||
typedef volatile unsigned short vu_short;
|
||||
typedef volatile unsigned char vu_char;
|
||||
|
@ -63,10 +63,8 @@
|
||||
#define CONFIG_HSMMC2_8BIT
|
||||
|
||||
/* CPSW Ethernet */
|
||||
#define CONFIG_BOOTP_DNS2
|
||||
#define CONFIG_BOOTP_SEND_HOSTNAME
|
||||
#define CONFIG_NET_RETRY_COUNT 10
|
||||
#define CONFIG_PHY_TI
|
||||
|
||||
/*
|
||||
* Default to using SPI for environment, etc.
|
||||
|
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