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https://github.com/brain-hackers/u-boot-brain
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usb: ehci-mx6: Split usb_power_config()
Split usb_power_config() per SoC and pass in USB PHY, USBNC and ANATOP
addresses instead of ad-hoc sequence numbers. This is only applicable
on legacy systems which do not implement proper PHY support. Once PHY
support is available, parts of this can be removed altogether and moved
to the PHY driver, similar to Linux phy-mxs-usb.c .
Fixes: 4de51cc25b ("usb: ehci-mx6: Drop assignment of sequence number")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Ye Li <ye.li@nxp.com>
Cc: uboot-imx <uboot-imx@nxp.com>
This commit is contained in:
Marek Vasut
parent
eb64f598dc
commit
849763b963
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@ -86,43 +86,18 @@ struct usbnc_regs {
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u32 adp_status;
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};
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#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
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static const unsigned phy_bases[] = {
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USB_PHY0_BASE_ADDR,
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#if defined(USB_PHY1_BASE_ADDR)
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USB_PHY1_BASE_ADDR,
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#endif
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};
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static void usb_internal_phy_clock_gate(void __iomem *phy_reg, int on)
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#if defined(CONFIG_MX6) && !defined(CONFIG_PHY)
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static void usb_power_config_mx6(struct anatop_regs __iomem *anatop,
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int anatop_bits_index)
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{
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phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
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writel(USBPHY_CTRL_CLKGATE, phy_reg);
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}
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static void usb_power_config(int index)
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{
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#if defined(CONFIG_MX7ULP)
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struct usbphy_regs __iomem *usbphy =
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(struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR;
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if (index > 0)
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return;
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writel(ANADIG_USB2_CHRG_DETECT_EN_B |
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ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
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&usbphy->usb1_chrg_detect);
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scg_enable_usb_pll(true);
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#else
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struct anatop_regs __iomem *anatop =
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(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
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void __iomem *chrg_detect;
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void __iomem *pll_480_ctrl_clr;
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void __iomem *pll_480_ctrl_set;
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switch (index) {
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if (!is_mx6())
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return;
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switch (anatop_bits_index) {
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case 0:
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chrg_detect = &anatop->usb1_chrg_detect;
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pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
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@ -155,8 +130,61 @@ static void usb_power_config(int index)
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ANADIG_USB2_PLL_480_CTRL_POWER |
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ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
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pll_480_ctrl_set);
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}
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#else
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static void __maybe_unused
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usb_power_config_mx6(void *anatop, int anatop_bits_index) { }
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#endif
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#if defined(CONFIG_MX7) && !defined(CONFIG_PHY)
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static void usb_power_config_mx7(struct usbnc_regs *usbnc)
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{
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void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
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if (!is_mx7())
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return;
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/*
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* Clear the ACAENB to enable usb_otg_id detection,
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* otherwise it is the ACA detection enabled.
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*/
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clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
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}
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#else
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static void __maybe_unused
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usb_power_config_mx7(void *usbnc) { }
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#endif
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#if defined(CONFIG_MX7ULP) && !defined(CONFIG_PHY)
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static void usb_power_config_mx7ulp(struct usbphy_regs __iomem *usbphy)
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{
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if (!is_mx7ulp())
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return;
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writel(ANADIG_USB2_CHRG_DETECT_EN_B |
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ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
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&usbphy->usb1_chrg_detect);
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scg_enable_usb_pll(true);
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}
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#else
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static void __maybe_unused
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usb_power_config_mx7ulp(void *usbphy) { }
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#endif
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#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
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static const unsigned phy_bases[] = {
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USB_PHY0_BASE_ADDR,
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#if defined(USB_PHY1_BASE_ADDR)
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USB_PHY1_BASE_ADDR,
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#endif
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};
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#if !defined(CONFIG_PHY)
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static void usb_internal_phy_clock_gate(void __iomem *phy_reg, int on)
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{
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phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
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writel(USBPHY_CTRL_CLKGATE, phy_reg);
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}
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/* Return 0 : host node, <>0 : device mode */
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@ -196,6 +224,7 @@ static int usb_phy_enable(struct usb_ehci *ehci, void __iomem *phy_reg)
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return 0;
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}
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#endif
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int usb_phy_mode(int port)
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{
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@ -215,19 +244,6 @@ int usb_phy_mode(int port)
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}
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#elif defined(CONFIG_MX7)
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static void usb_power_config(int index)
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{
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struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
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(0x10000 * index) + USBNC_OFFSET);
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void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
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/*
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* Clear the ACAENB to enable usb_otg_id detection,
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* otherwise it is the ACA detection enabled.
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*/
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clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
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}
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int usb_phy_mode(int port)
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{
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struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
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@ -325,8 +341,16 @@ int ehci_hcd_init(int index, enum usb_init_type init,
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enum usb_init_type type;
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#if defined(CONFIG_MX6)
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u32 controller_spacing = 0x200;
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#elif defined(CONFIG_MX7) || defined(CONFIG_MX7ULP)
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struct anatop_regs __iomem *anatop =
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(struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
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#elif defined(CONFIG_MX7)
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u32 controller_spacing = 0x10000;
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struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
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(0x10000 * index) + USBNC_OFFSET);
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#elif defined(CONFIG_MX7ULP)
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u32 controller_spacing = 0x10000;
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struct usbphy_regs __iomem *usbphy =
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(struct usbphy_regs __iomem *)USB_PHY0_BASE_ADDR;
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#endif
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struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
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(controller_spacing * index));
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@ -353,7 +377,14 @@ int ehci_hcd_init(int index, enum usb_init_type init,
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return ret;
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}
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usb_power_config(index);
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#if defined(CONFIG_MX6)
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usb_power_config_mx6(anatop, index);
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#elif defined (CONFIG_MX7)
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usb_power_config_mx7(usbnc);
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#elif defined (CONFIG_MX7ULP)
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usb_power_config_mx7ulp(usbphy);
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#endif
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usb_oc_config(index);
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#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
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@ -410,10 +441,15 @@ static int mx6_init_after_reset(struct ehci_ctrl *dev)
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enum usb_init_type type = priv->init_type;
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struct usb_ehci *ehci = priv->ehci;
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usb_power_config(priv->portnr);
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#if !defined(CONFIG_PHY)
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usb_power_config_mx6(priv->anatop_addr, priv->portnr);
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usb_power_config_mx7(priv->misc_addr);
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usb_power_config_mx7ulp(priv->phy_addr);
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#endif
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usb_oc_config(priv->portnr);
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#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
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#if !defined(CONFIG_PHY) && (defined(CONFIG_MX6) || defined(CONFIG_MX7ULP))
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usb_internal_phy_clock_gate(priv->phy_addr, 1);
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usb_phy_enable(ehci, priv->phy_addr);
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#endif
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@ -655,10 +691,15 @@ static int ehci_usb_probe(struct udevice *dev)
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debug("%s: No vbus supply\n", dev->name);
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#endif
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usb_power_config(priv->portnr);
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#if !defined(CONFIG_PHY)
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usb_power_config_mx6(priv->anatop_addr, priv->portnr);
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usb_power_config_mx7(priv->misc_addr);
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usb_power_config_mx7ulp(priv->phy_addr);
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#endif
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usb_oc_config(priv->portnr);
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#if defined(CONFIG_MX6) || defined(CONFIG_MX7ULP)
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#if !defined(CONFIG_PHY) && (defined(CONFIG_MX6) || defined(CONFIG_MX7ULP))
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usb_internal_phy_clock_gate(priv->phy_addr, 1);
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usb_phy_enable(ehci, priv->phy_addr);
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#endif
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