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Merge branch '2021-04-20-assorted-improvements'

Browse Source 
- ARM64 GIC fix, CONFIG_IRQ now moved to Kconfig
- IDE, lz4 fixes
- octeontx cleanups / enhancements
- highbank DM migration
- psci updates
- Enable use of -fstack-protector
This commit is contained in:
Tom Rini 2021-04-20 07:32:04 -04:00
commit 842d049be2
52 changed files with 890 additions and 264 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
MAINTAINERS
View File

@ -1062,6 +1062,13 @@ F: include/sqfs.h
F: cmd/sqfs.c
F: test/py/tests/test_fs/test_squashfs/
STACKPROTECTOR
M: Joel Peshkin <joel.peshkin@broadcom.com>
S: Maintained
F: common/stackprot.c
F: cmd/stackprot_test.c
F: test/py/tests/test_stackprotector.py
TARGET_BCMNS3
M: Bharat Gooty <bharat.gooty@broadcom.com>
M: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com>

5
Makefile
View File

@ -676,7 +676,12 @@ else
KBUILD_CFLAGS += -O2
endif
ifeq ($(CONFIG_STACKPROTECTOR),y)
KBUILD_CFLAGS += $(call cc-option,-fstack-protector-strong)
CFLAGS_EFI += $(call cc-option,-fno-stack-protector)
else
KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector)
endif
KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks)
# disable stringop warnings in gcc 8+

3
arch/Kconfig
View File

@ -120,6 +120,7 @@ config SANDBOX
select SPI
select SUPPORT_OF_CONTROL
select SYSRESET_CMD_POWEROFF
select IRQ
imply BITREVERSE
select BLOBLIST
imply CMD_DM
@ -185,6 +186,7 @@ config X86
select TIMER
select USE_PRIVATE_LIBGCC
select X86_TSC_TIMER
select IRQ
imply HAS_ROM if X86_RESET_VECTOR
imply BLK
imply CMD_DM
@ -215,7 +217,6 @@ config X86
imply USB_HOST_ETHER
imply PCH
imply RTC_MC146818
imply IRQ
imply ACPIGEN if !QEMU
imply SYSINFO if GENERATE_SMBIOS_TABLE
imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE

12
arch/arm/Kconfig
View File

@ -67,6 +67,7 @@ config GIC_V3_ITS
bool "ARM GICV3 ITS"
select REGMAP
select SYSCON
select IRQ
help
ARM GICV3 Interrupt translation service (ITS).
Basic support for programming locality specific peripheral
@ -710,7 +711,16 @@ config ARCH_S5PC1XX
config ARCH_HIGHBANK
bool "Calxeda Highbank"
select CPU_V7A
select PL011_SERIAL
select PL01X_SERIAL
select DM
select DM_SERIAL
select OF_CONTROL
select OF_BOARD
select CLK
select CLK_CCF
select AHCI
select DM_ETH
select PHYS_64BIT
config ARCH_INTEGRATOR
bool "ARM Ltd. Integrator family"

3
arch/arm/config.mk
View File

@ -11,7 +11,8 @@ CONFIG_STANDALONE_LOAD_ADDR = 0xc100000
endif
endif
CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections
CFLAGS_NON_EFI := -fno-pic -ffixed-r9 -ffunction-sections -fdata-sections \
-fstack-protector-strong
CFLAGS_EFI := -fpic -fshort-wchar
LDFLAGS_FINAL += --gc-sections

12
arch/arm/lib/gic-v3-its.c
View File

@ -3,6 +3,7 @@
* Copyright 2019 Broadcom.
*/
#include <common.h>
#include <cpu_func.h>
#include <dm.h>
#include <regmap.h>
#include <syscon.h>
@ -108,6 +109,8 @@ int gic_lpi_tables_init(void)
int i;
u64 redist_lpi_base;
u64 pend_base;
ulong pend_tab_total_sz;
void *pend_tab_va;
if (gic_v3_its_get_gic_addr(&priv))
return -EINVAL;
@ -161,6 +164,12 @@ int gic_lpi_tables_init(void)
}
redist_lpi_base = priv.lpi_base + LPI_PROPBASE_SZ;
pend_tab_total_sz = priv.num_redist * LPI_PENDBASE_SZ;
pend_tab_va = map_physmem(redist_lpi_base, pend_tab_total_sz,
MAP_NOCACHE);
memset(pend_tab_va, 0, pend_tab_total_sz);
flush_cache((ulong)pend_tab_va, pend_tab_total_sz);
unmap_physmem(pend_tab_va, MAP_NOCACHE);
pend_base = priv.gicr_base + GICR_PENDBASER;
for (i = 0; i < priv.num_redist; i++) {
@ -168,7 +177,8 @@ int gic_lpi_tables_init(void)
val = ((redist_lpi_base + (i * LPI_PENDBASE_SZ)) |
GICR_PENDBASER_INNERSHAREABLE |
GICR_PENDBASER_RAWAWB);
GICR_PENDBASER_RAWAWB |
GICR_PENDBASER_PTZ);
writeq(val, (uintptr_t)(pend_base + offset));
tmp = readq((uintptr_t)(pend_base + offset));

1
arch/riscv/lib/Makefile
View File

@ -27,6 +27,7 @@ obj-$(CONFIG_SPL_BUILD) += spl.o
obj-y += fdt_fixup.o
# For building EFI apps
CFLAGS_NON_EFI := -fstack-protector-strong
CFLAGS_$(EFI_CRT0) := $(CFLAGS_EFI)
CFLAGS_REMOVE_$(EFI_CRT0) := $(CFLAGS_NON_EFI)

10
arch/x86/config.mk
View File

@ -39,10 +39,10 @@ LDFLAGS_EFI_PAYLOAD := -Bsymbolic -Bsymbolic-functions -shared --no-undefined -s
OBJCOPYFLAGS_EFI := -j .text -j .sdata -j .data -j .dynamic -j .dynsym \
-j .rel -j .rela -j .reloc
ifeq ($(IS_32BIT),y)
CFLAGS_NON_EFI := -mregparm=3
endif
# Compiler flags to be added when building UEFI applications
CFLAGS_EFI := -fpic -fshort-wchar
# Compiler flags to be removed when building UEFI applications
CFLAGS_NON_EFI := -mregparm=3 -fstack-protector-strong
ifeq ($(CONFIG_EFI_STUB_64BIT),)
CFLAGS_EFI += $(call cc-option, -mno-red-zone)
@ -70,7 +70,9 @@ LDSCRIPT := $(LDSCRIPT_EFI)
else
PLATFORM_CPPFLAGS += $(CFLAGS_NON_EFI)
ifeq ($(IS_32BIT),y)
PLATFORM_CPPFLAGS += -mregparm=3
endif
KBUILD_LDFLAGS += --emit-relocs
LDFLAGS_FINAL += --gc-sections $(if $(CONFIG_SPL_BUILD),,-pie)

2
board/highbank/MAINTAINERS
View File

@ -1,5 +1,5 @@
HIGHBANK BOARD
M: Rob Herring <robh@kernel.org>
M: Andre Przywara <andre.przywara@arm.com>
S: Maintained
F: board/highbank/
F: include/configs/highbank.h

32
board/highbank/highbank.c
View File

@ -8,9 +8,9 @@
#include <cpu_func.h>
#include <env.h>
#include <fdt_support.h>
#include <fdtdec.h>
#include <init.h>
#include <net.h>
#include <netdev.h>
#include <scsi.h>
#include <asm/global_data.h>
@ -52,18 +52,6 @@ int board_init(void)
return 0;
}
/* We know all the init functions have been run now */
int board_eth_init(struct bd_info *bis)
{
int rc = 0;
#ifdef CONFIG_CALXEDA_XGMAC
rc += calxedaxgmac_initialize(0, 0xfff50000);
rc += calxedaxgmac_initialize(1, 0xfff51000);
#endif
return rc;
}
#ifdef CONFIG_SCSI_AHCI_PLAT
void scsi_init(void)
{
@ -97,8 +85,12 @@ int misc_init_r(void)
int dram_init(void)
{
gd->ram_size = SZ_512M;
return 0;
return fdtdec_setup_mem_size_base();
}
int dram_init_banksize(void)
{
return fdtdec_setup_memory_banksize();
}
#if defined(CONFIG_OF_BOARD_SETUP)
@ -119,6 +111,16 @@ int ft_board_setup(void *fdt, struct bd_info *bd)
}
#endif
void *board_fdt_blob_setup(void)
{
/*
* The ECME management processor loads the DTB from NOR flash
* into DRAM (at 4KB), where it gets patched to contain the
* detected memory size.
*/
return (void *)0x1000;
}
static int is_highbank(void)
{
uint32_t midr;

4
board/toradex/common/tdx-cfg-block.c
View File

@ -556,6 +556,8 @@ static int get_cfgblock_interactive(void)
static int get_cfgblock_barcode(char *barcode, struct toradex_hw *tag,
u32 *serial)
{
char revision[3] = {barcode[6], barcode[7], '\0'};
if (strlen(barcode) < 16) {
printf("Argument too short, barcode is 16 chars long\n");
return -1;
@ -564,7 +566,7 @@ static int get_cfgblock_barcode(char *barcode, struct toradex_hw *tag,
/* Get hardware information from the first 8 digits */
tag->ver_major = barcode[4] - '0';
tag->ver_minor = barcode[5] - '0';
tag->ver_assembly = barcode[7] - '0';
tag->ver_assembly = simple_strtoul(revision, NULL, 10);
barcode[4] = '\0';
tag->prodid = simple_strtoul(barcode, NULL, 10);

10
cmd/Kconfig
View File

@ -1067,6 +1067,7 @@ config CMD_MISC
config CMD_MMC
bool "mmc"
depends on MMC
help
MMC memory mapped support.
@ -2324,6 +2325,15 @@ config CMD_AVB
avb read_part_hex - read data from partition and output to stdout
avb write_part - write data to partition
avb verify - run full verification chain
config CMD_STACKPROTECTOR_TEST
bool "Test command for stack protector"
depends on STACKPROTECTOR
help
Enable stackprot_test command
The stackprot_test command will force a stack overrun to test
the stack smashing detection mechanisms.
endmenu
config CMD_UBI

1
cmd/Makefile
View File

@ -144,6 +144,7 @@ obj-$(CONFIG_CMD_SPI) += spi.o
obj-$(CONFIG_CMD_STRINGS) += strings.o
obj-$(CONFIG_CMD_SMC) += smccc.o
obj-$(CONFIG_CMD_SYSBOOT) += sysboot.o pxe_utils.o
obj-$(CONFIG_CMD_STACKPROTECTOR_TEST) += stackprot_test.o
obj-$(CONFIG_CMD_TERMINAL) += terminal.o
obj-$(CONFIG_CMD_TIME) += time.o
obj-$(CONFIG_CMD_TIMER) += timer.o

2
cmd/boot.c
View File

@ -56,7 +56,7 @@ U_BOOT_CMD(
#endif
U_BOOT_CMD(
reset, 1, 0, do_reset,
reset, 2, 0, do_reset,
"Perform RESET of the CPU",
""
);

19
cmd/stackprot_test.c Normal file
View File

@ -0,0 +1,19 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Broadcom
*/
#include <common.h>
#include <command.h>
static int do_test_stackprot_fail(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
char a[128];
memset(a, 0xa5, 512);
return 0;
}
U_BOOT_CMD(stackprot_test, 1, 1, do_test_stackprot_fail,
"test stack protector fail", "");

17
common/Kconfig
View File

@ -618,6 +618,23 @@ config TPL_HASH
and the algorithms it supports are defined in common/hash.c. See
also CMD_HASH for command-line access.
config STACKPROTECTOR
bool "Stack Protector buffer overflow detection"
default n
help
Enable stack smash detection through compiler's stack-protector
canary logic
config SPL_STACKPROTECTOR
bool "Stack Protector buffer overflow detection for SPL"
depends on STACKPROTECTOR && SPL
default n
config TPL_STACKPROTECTOR
bool "Stack Protector buffer overflow detection for TPL"
depends on STACKPROTECTOR && TPL
default n
endmenu
menu "Update support"

1
common/Makefile
View File

@ -137,6 +137,7 @@ obj-$(CONFIG_CMD_LOADB) += xyzModem.o
obj-$(CONFIG_$(SPL_TPL_)YMODEM_SUPPORT) += xyzModem.o
obj-$(CONFIG_AVB_VERIFY) += avb_verify.o
obj-$(CONFIG_$(SPL_TPL_)STACKPROTECTOR) += stackprot.o
obj-$(CONFIG_SCP03) += scp03.o
obj-$(CONFIG_QFW) += qfw.o

20
common/stackprot.c Normal file
View File

@ -0,0 +1,20 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright 2021 Broadcom
*/
#include <common.h>
#include <asm/global_data.h>
DECLARE_GLOBAL_DATA_PTR;
unsigned long __stack_chk_guard = (unsigned long)(0xfeedf00ddeadbeef & ~0UL);
void __stack_chk_fail(void)
{
void *ra;
ra = __builtin_extract_return_addr(__builtin_return_address(0));
panic("Stack smashing detected in function:\n%p relocated from %p",
ra, ra - gd->reloc_off);
}

4
configs/highbank_defconfig
View File

@ -3,7 +3,7 @@ CONFIG_SYS_DCACHE_OFF=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_HIGHBANK=y
CONFIG_SYS_TEXT_BASE=0x00008000
CONFIG_NR_DRAM_BANKS=0
CONFIG_NR_DRAM_BANKS=2
CONFIG_ENV_SIZE=0x2000
CONFIG_SYS_BOOTCOUNT_ADDR=0xfff3cf0c
CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y
@ -26,3 +26,5 @@ CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_SCSI=y
CONFIG_CONS_INDEX=0
CONFIG_OF_LIBFDT=y
CONFIG_OF_BOARD=y
CONFIG_CALXEDA_XGMAC=y

2
configs/octeontx_81xx_defconfig
View File

@ -17,6 +17,7 @@ CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y
@ -131,4 +132,5 @@ CONFIG_USB_ETHER_ASIX=y
CONFIG_USB_ETHER_ASIX88179=y
CONFIG_USB_ETHER_RTL8152=y
CONFIG_WDT=y
CONFIG_WDT_SBSA=y
CONFIG_ERRNO_STR=y

1
configs/octeontx_83xx_defconfig
View File

@ -15,6 +15,7 @@ CONFIG_DEBUG_UART=y
CONFIG_AHCI=y
CONFIG_FIT=y
CONFIG_FIT_SIGNATURE=y
CONFIG_SUPPORT_RAW_INITRD=y
CONFIG_OF_BOARD_SETUP=y
CONFIG_BOOTDELAY=5
CONFIG_USE_BOOTARGS=y

1
configs/sandbox64_defconfig
View File

@ -137,7 +137,6 @@ CONFIG_CROS_EC_I2C=y
CONFIG_CROS_EC_LPC=y
CONFIG_CROS_EC_SANDBOX=y
CONFIG_CROS_EC_SPI=y
CONFIG_IRQ=y
CONFIG_P2SB=y
CONFIG_PWRSEQ=y
CONFIG_SPL_PWRSEQ=y

3
configs/sandbox_defconfig
View File

@ -25,6 +25,7 @@ CONFIG_LOG_SYSLOG=y
CONFIG_LOG_ERROR_RETURN=y
CONFIG_DISPLAY_BOARDINFO_LATE=y
CONFIG_MISC_INIT_F=y
CONFIG_STACKPROTECTOR=y
CONFIG_ANDROID_AB=y
CONFIG_CMD_CPU=y
CONFIG_CMD_LICENSE=y
@ -97,6 +98,7 @@ CONFIG_CMD_CRAMFS=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_SQUASHFS=y
CONFIG_CMD_MTDPARTS=y
CONFIG_CMD_STACKPROTECTOR_TEST=y
CONFIG_MAC_PARTITION=y
CONFIG_AMIGA_PARTITION=y
CONFIG_OF_CONTROL=y
@ -166,7 +168,6 @@ CONFIG_CROS_EC_I2C=y
CONFIG_CROS_EC_LPC=y
CONFIG_CROS_EC_SANDBOX=y
CONFIG_CROS_EC_SPI=y
CONFIG_IRQ=y
CONFIG_P2SB=y
CONFIG_PWRSEQ=y
CONFIG_SPL_PWRSEQ=y

1
configs/sandbox_flattree_defconfig
View File

@ -115,7 +115,6 @@ CONFIG_CROS_EC_I2C=y
CONFIG_CROS_EC_LPC=y
CONFIG_CROS_EC_SANDBOX=y
CONFIG_CROS_EC_SPI=y
CONFIG_IRQ=y
CONFIG_P2SB=y
CONFIG_PWRSEQ=y
CONFIG_SPL_PWRSEQ=y

1
configs/sandbox_spl_defconfig
View File

@ -139,7 +139,6 @@ CONFIG_CROS_EC_I2C=y
CONFIG_CROS_EC_LPC=y
CONFIG_CROS_EC_SANDBOX=y
CONFIG_CROS_EC_SPI=y
CONFIG_IRQ=y
CONFIG_P2SB=y
CONFIG_PWRSEQ=y
CONFIG_SPL_PWRSEQ=y

45
doc/device-tree-bindings/regulator/fsl,anatop-regulator.txt Normal file
View File

@ -0,0 +1,45 @@
ANATOP REGULATOR
Anatop is an integrated regulator inside i.MX6 SoC.
Required properties:
- compatible: Must be "fsl,anatop-regulator".
- regulator-name: Name of the regulator
- anatop-reg-offset: u32 value representing the anatop MFD register offset.
- anatop-vol-bit-shift: u32 value representing the bit shift for the register.
- anatop-vol-bit-width: u32 value representing the number of bits used in the
register.
- anatop-min-bit-val: u32 value representing the minimum value of this
register.
- anatop-min-voltage: u32 value representing the minimum voltage of this
regulator.
- anatop-max-voltage: u32 value representing the maximum voltage of this
regulator.
Optional properties:
- anatop-delay-reg-offset: u32 value representing the anatop MFD step time
register offset.
- anatop-delay-bit-shift: u32 value representing the bit shift for the step
time register.
- anatop-delay-bit-width: u32 value representing the number of bits used in
the step time register.
- anatop-enable-bit: u32 value representing regulator enable bit offset.
- vin-supply: input supply phandle.
Example:
regulator-vddpu {
compatible = "fsl,anatop-regulator";
regulator-name = "vddpu";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1300000>;
regulator-always-on;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <9>;
anatop-vol-bit-width = <5>;
anatop-delay-reg-offset = <0x170>;
anatop-delay-bit-shift = <24>;
anatop-delay-bit-width = <2>;
anatop-min-bit-val = <1>;
anatop-min-voltage = <725000>;
anatop-max-voltage = <1300000>;
};

1
doc/usage/index.rst
View File

@ -40,3 +40,4 @@ Shell commands
sbi
true
scp03
reset

26
doc/usage/reset.rst Normal file
View File

@ -0,0 +1,26 @@
.. SPDX-License-Identifier: GPL-2.0+
reset command
=============
Synopsis
--------
::
reset [-w]
Description
-----------
Perform reset of the CPU. By default does COLD reset, which resets CPU,
DDR and peripherals, on some boards also resets external PMIC.
-w
Do warm WARM, reset CPU but keep peripheral/DDR/PMIC active.
Return value
------------
The return value $? is always set to 0 (true).

3
drivers/ata/ahci.c
View File

@ -1190,6 +1190,9 @@ int ahci_probe_scsi(struct udevice *ahci_dev, ulong base)
*/
uc_plat->max_id = max_t(unsigned long, uc_priv->n_ports,
uc_plat->max_id);
/* If port count is less than max_id, update max_id */
if (uc_priv->n_ports < uc_plat->max_id)
uc_plat->max_id = uc_priv->n_ports;
return 0;
}

160
drivers/block/ide.c
View File

@ -130,56 +130,38 @@ OUT:
* ATAPI Support
*/
#if defined(CONFIG_IDE_SWAP_IO)
/* since ATAPI may use commands with not 4 bytes alligned length
* we have our own transfer functions, 2 bytes alligned */
__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
{
uintptr_t paddr = (ATA_CURR_BASE(dev) + ATA_DATA_REG);
ushort *dbuf;
volatile ushort *pbuf;
pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
dbuf = (ushort *)sect_buf;
debug("in output data shorts base for read is %lx\n",
(unsigned long) pbuf);
debug("in output data shorts base for read is %p\n", (void *)paddr);
while (shorts--) {
EIEIO;
*pbuf = *dbuf++;
outw(cpu_to_le16(*dbuf++), paddr);
}
}
__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
{
uintptr_t paddr = (ATA_CURR_BASE(dev) + ATA_DATA_REG);
ushort *dbuf;
volatile ushort *pbuf;
pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
dbuf = (ushort *)sect_buf;
debug("in input data shorts base for read is %lx\n",
(unsigned long) pbuf);
debug("in input data shorts base for read is %p\n", (void *)paddr);
while (shorts--) {
EIEIO;
*dbuf++ = *pbuf;
*dbuf++ = le16_to_cpu(inw(paddr));
}
}
#else /* ! CONFIG_IDE_SWAP_IO */
__weak void ide_output_data_shorts(int dev, ushort *sect_buf, int shorts)
{
outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
}
__weak void ide_input_data_shorts(int dev, ushort *sect_buf, int shorts)
{
insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, shorts);
}
#endif /* CONFIG_IDE_SWAP_IO */
/*
* Wait until (Status & mask) == res, or timeout (in ms)
* Return last status
@ -636,19 +618,6 @@ static void ide_ident(struct blk_desc *dev_desc)
sizeof(dev_desc->vendor));
ident_cpy((unsigned char *)dev_desc->product, iop.serial_no,
sizeof(dev_desc->product));
#ifdef __LITTLE_ENDIAN
/*
* firmware revision, model, and serial number have Big Endian Byte
* order in Word. Convert all three to little endian.
*
* See CF+ and CompactFlash Specification Revision 2.0:
* 6.2.1.6: Identify Drive, Table 39 for more details
*/
strswab(dev_desc->revision);
strswab(dev_desc->vendor);
strswab(dev_desc->product);
#endif /* __LITTLE_ENDIAN */
if ((iop.config & 0x0080) == 0x0080)
dev_desc->removable = 1;
@ -662,26 +631,22 @@ static void ide_ident(struct blk_desc *dev_desc)
}
#endif /* CONFIG_ATAPI */
#ifdef __BIG_ENDIAN
/* swap shorts */
dev_desc->lba = (iop.lba_capacity << 16) | (iop.lba_capacity >> 16);
#else /* ! __BIG_ENDIAN */
/*
* do not swap shorts on little endian
*
* See CF+ and CompactFlash Specification Revision 2.0:
* 6.2.1.6: Identfy Drive, Table 39, Word Address 57-58 for details.
*/
dev_desc->lba = iop.lba_capacity;
#endif /* __BIG_ENDIAN */
iop.lba_capacity[0] = be16_to_cpu(iop.lba_capacity[0]);
iop.lba_capacity[1] = be16_to_cpu(iop.lba_capacity[1]);
dev_desc->lba =
((unsigned long)iop.lba_capacity[0]) |
((unsigned long)iop.lba_capacity[1] << 16);
#ifdef CONFIG_LBA48
if (iop.command_set_2 & 0x0400) { /* LBA 48 support */
dev_desc->lba48 = 1;
dev_desc->lba = (unsigned long long) iop.lba48_capacity[0] |
((unsigned long long) iop.lba48_capacity[1] << 16) |
((unsigned long long) iop.lba48_capacity[2] << 32) |
((unsigned long long) iop.lba48_capacity[3] << 48);
for (int i = 0; i < 4; i++)
iop.lba48_capacity[i] = be16_to_cpu(iop.lba48_capacity[i]);
dev_desc->lba =
((unsigned long long)iop.lba48_capacity[0] |
((unsigned long long)iop.lba48_capacity[1] << 16) |
((unsigned long long)iop.lba48_capacity[2] << 32) |
((unsigned long long)iop.lba48_capacity[3] << 48));
} else {
dev_desc->lba48 = 0;
}
@ -846,90 +811,59 @@ void ide_init(void)
#endif
}
/* We only need to swap data if we are running on a big endian cpu. */
#if defined(__LITTLE_ENDIAN)
__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
{
ide_input_data(dev, sect_buf, words);
}
#else
__weak void ide_input_swap_data(int dev, ulong *sect_buf, int words)
{
volatile ushort *pbuf =
(ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
uintptr_t paddr = (ATA_CURR_BASE(dev) + ATA_DATA_REG);
ushort *dbuf = (ushort *)sect_buf;
debug("in input swap data base for read is %lx\n",
(unsigned long) pbuf);
debug("in input swap data base for read is %p\n", (void *)paddr);
while (words--) {
#ifdef __MIPS__
*dbuf++ = swab16p((u16 *)pbuf);
*dbuf++ = swab16p((u16 *)pbuf);
#else
*dbuf++ = ld_le16(pbuf);
*dbuf++ = ld_le16(pbuf);
#endif /* !MIPS */
EIEIO;
*dbuf++ = be16_to_cpu(inw(paddr));
EIEIO;
*dbuf++ = be16_to_cpu(inw(paddr));
}
}
#endif /* __LITTLE_ENDIAN */
#if defined(CONFIG_IDE_SWAP_IO)
__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
{
ushort *dbuf;
volatile ushort *pbuf;
pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
dbuf = (ushort *)sect_buf;
while (words--) {
EIEIO;
*pbuf = *dbuf++;
EIEIO;
*pbuf = *dbuf++;
}
}
#else /* ! CONFIG_IDE_SWAP_IO */
__weak void ide_output_data(int dev, const ulong *sect_buf, int words)
{
#if defined(CONFIG_IDE_AHB)
ide_write_data(dev, sect_buf, words);
#else
outsw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1);
#endif
}
#endif /* CONFIG_IDE_SWAP_IO */
#if defined(CONFIG_IDE_SWAP_IO)
__weak void ide_input_data(int dev, ulong *sect_buf, int words)
{
uintptr_t paddr = (ATA_CURR_BASE(dev) + ATA_DATA_REG);
ushort *dbuf;
volatile ushort *pbuf;
pbuf = (ushort *)(ATA_CURR_BASE(dev) + ATA_DATA_REG);
dbuf = (ushort *)sect_buf;
debug("in input data base for read is %lx\n", (unsigned long) pbuf);
while (words--) {
EIEIO;
*dbuf++ = *pbuf;
outw(cpu_to_le16(*dbuf++), paddr);
EIEIO;
*dbuf++ = *pbuf;
outw(cpu_to_le16(*dbuf++), paddr);
}
#endif /* CONFIG_IDE_AHB */
}
#else /* ! CONFIG_IDE_SWAP_IO */
__weak void ide_input_data(int dev, ulong *sect_buf, int words)
{
#if defined(CONFIG_IDE_AHB)
ide_read_data(dev, sect_buf, words);
#else
insw(ATA_CURR_BASE(dev) + ATA_DATA_REG, sect_buf, words << 1);
#endif
}
uintptr_t paddr = (ATA_CURR_BASE(dev) + ATA_DATA_REG);
ushort *dbuf;
#endif /* CONFIG_IDE_SWAP_IO */
dbuf = (ushort *)sect_buf;
debug("in input data base for read is %p\n", (void *)paddr);
while (words--) {
EIEIO;
*dbuf++ = le16_to_cpu(inw(paddr));
EIEIO;
*dbuf++ = le16_to_cpu(inw(paddr));
}
#endif /* CONFIG_IDE_AHB */
}
#ifdef CONFIG_BLK
ulong ide_read(struct udevice *dev, lbaint_t blknr, lbaint_t blkcnt,
@ -1019,14 +953,14 @@ ulong ide_read(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
if (lba48) {
ide_outb(device, ATA_DEV_HD,
ATA_LBA | ATA_DEVICE(device));
ide_outb(device, ATA_COMMAND, ATA_CMD_READ_EXT);
ide_outb(device, ATA_COMMAND, ATA_CMD_PIO_READ_EXT);
} else
#endif
{
ide_outb(device, ATA_DEV_HD, ATA_LBA |
ATA_DEVICE(device) | ((blknr >> 24) & 0xF));
ide_outb(device, ATA_COMMAND, ATA_CMD_READ);
ide_outb(device, ATA_COMMAND, ATA_CMD_PIO_READ);
}
udelay(50);
@ -1116,14 +1050,14 @@ ulong ide_write(struct blk_desc *block_dev, lbaint_t blknr, lbaint_t blkcnt,
if (lba48) {
ide_outb(device, ATA_DEV_HD,
ATA_LBA | ATA_DEVICE(device));
ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE_EXT);
ide_outb(device, ATA_COMMAND, ATA_CMD_PIO_WRITE_EXT);
} else
#endif
{
ide_outb(device, ATA_DEV_HD, ATA_LBA |
ATA_DEVICE(device) | ((blknr >> 24) & 0xF));
ide_outb(device, ATA_COMMAND, ATA_CMD_WRITE);
ide_outb(device, ATA_COMMAND, ATA_CMD_PIO_WRITE);
}
udelay(50);

68
drivers/firmware/psci.c
View File

@ -13,6 +13,7 @@
#include <log.h>
#include <dm/lists.h>
#include <efi_loader.h>
#include <sysreset.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
#include <linux/arm-smccc.h>
@ -26,6 +27,18 @@
#define PSCI_METHOD_HVC 1
#define PSCI_METHOD_SMC 2
/*
* While a 64-bit OS can make calls with SMC32 calling conventions, for some
* calls it is necessary to use SMC64 to pass or return 64-bit values.
* For such calls PSCI_FN_NATIVE(version, name) will choose the appropriate
* (native-width) function ID.
*/
#if defined(CONFIG_ARM64)
#define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN64_##name
#else
#define PSCI_FN_NATIVE(version, name) PSCI_##version##_FN_##name
#endif
#if CONFIG_IS_ENABLED(EFI_LOADER)
int __efi_runtime_data psci_method;
#else
@ -53,6 +66,34 @@ unsigned long __efi_runtime invoke_psci_fn
return res.a0;
}
static int psci_features(u32 psci_func_id)
{
return invoke_psci_fn(PSCI_1_0_FN_PSCI_FEATURES,
psci_func_id, 0, 0);
}
static u32 psci_0_2_get_version(void)
{
return invoke_psci_fn(PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0);
}
static bool psci_is_system_reset2_supported(void)
{
int ret;
u32 ver;
ver = psci_0_2_get_version();
if (PSCI_VERSION_MAJOR(ver) >= 1) {
ret = psci_features(PSCI_FN_NATIVE(1_1, SYSTEM_RESET2));
if (ret != PSCI_RET_NOT_SUPPORTED)
return true;
}
return false;
}
static int psci_bind(struct udevice *dev)
{
/* No SYSTEM_RESET support for PSCI 0.1 */
@ -141,6 +182,33 @@ void reset_misc(void)
}
#endif /* CONFIG_PSCI_RESET */
void psci_sys_reset(u32 type)
{
bool reset2_supported;
do_psci_probe();
reset2_supported = psci_is_system_reset2_supported();
if (type == SYSRESET_WARM && reset2_supported) {
/*
* reset_type[31] = 0 (architectural)
* reset_type[30:0] = 0 (SYSTEM_WARM_RESET)
* cookie = 0 (ignored by the implementation)
*/
invoke_psci_fn(PSCI_FN_NATIVE(1_1, SYSTEM_RESET2), 0, 0, 0);
} else {
invoke_psci_fn(PSCI_0_2_FN_SYSTEM_RESET, 0, 0, 0);
}
}
void psci_sys_poweroff(void)
{
do_psci_probe();
invoke_psci_fn(PSCI_0_2_FN_SYSTEM_OFF, 0, 0, 0);
}
#ifdef CONFIG_CMD_POWEROFF
int do_poweroff(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{

5
drivers/misc/Kconfig
View File

@ -211,10 +211,9 @@ config FSL_SEC_MON
like software violations or hardware security violations.
config IRQ
bool "Intel Interrupt controller"
depends on X86 || SANDBOX
bool "Interrupt controller"
help
This enables support for Intel interrupt controllers, including ITSS.
This enables support for interrupt controllers, including ITSS.
Some devices have extra features, such as Apollo Lake. The
device has its own uclass since there are several operations
involved.

7
drivers/net/Kconfig
View File

@ -180,6 +180,13 @@ config CORTINA_NI_ENET
This driver supports the Cortina-Access Ethernet MAC for
all supported CAxxxx SoCs.
config CALXEDA_XGMAC
bool "Calxeda XGMAC support"
depends on DM_ETH
help
This driver supports the XGMAC in Calxeda Highbank and Midway
machines.
config DWC_ETH_QOS
bool "Synopsys DWC Ethernet QOS device support"
depends on DM_ETH

208
drivers/net/calxedaxgmac.c
View File

@ -10,6 +10,8 @@
#include <linux/delay.h>
#include <linux/err.h>
#include <asm/io.h>
#include <dm.h>
#include <dm/device-internal.h> /* for dev_set_priv() */
#define TX_NUM_DESC 1
#define RX_NUM_DESC 32
@ -212,6 +214,18 @@ struct xgmac_dma_desc {
__le32 res[3];
};
static struct xgmac_regs *xgmac_get_regs(struct eth_pdata *pdata)
{
/*
* We use PHYS_64BIT on Highbank, so phys_addr_t is bigger than
* a pointer. U-Boot doesn't use LPAE (not even the MMU on highbank),
* so we can't access anything above 4GB.
* We have a check in the probe function below the ensure this,
* so casting to a 32-bit pointer type is fine here.
*/
return (struct xgmac_regs *)(uintptr_t)pdata->iobase;
}
/* XGMAC Descriptor Access Helpers */
static inline void desc_set_buf_len(struct xgmac_dma_desc *p, u32 buf_sz)
{
@ -304,8 +318,6 @@ struct calxeda_eth_dev {
u32 tx_currdesc;
u32 rx_currdesc;
struct eth_device *dev;
} __aligned(32);
/*
@ -313,10 +325,10 @@ struct calxeda_eth_dev {
* advanced descriptors.
*/
static void init_rx_desc(struct calxeda_eth_dev *priv)
static void init_rx_desc(struct eth_pdata *pdata, struct calxeda_eth_dev *priv)
{
struct xgmac_dma_desc *rxdesc = priv->rx_chain;
struct xgmac_regs *regs = (struct xgmac_regs *)priv->dev->iobase;
struct xgmac_regs *regs = xgmac_get_regs(pdata);
void *rxbuffer = priv->rxbuffer;
int i;
@ -330,17 +342,16 @@ static void init_rx_desc(struct calxeda_eth_dev *priv)
}
}
static void init_tx_desc(struct calxeda_eth_dev *priv)
static void init_tx_desc(struct eth_pdata *pdata, struct calxeda_eth_dev *priv)
{
struct xgmac_regs *regs = (struct xgmac_regs *)priv->dev->iobase;
struct xgmac_regs *regs = xgmac_get_regs(pdata);
desc_init_tx_desc(priv->tx_chain, TX_NUM_DESC);
writel((ulong)priv->tx_chain, &regs->txdesclist);
}
static int xgmac_reset(struct eth_device *dev)
static int xgmac_reset(struct xgmac_regs *regs)
{
struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
int timeout = MAC_TIMEOUT;
u32 value;
@ -356,27 +367,28 @@ static int xgmac_reset(struct eth_device *dev)
return timeout;
}
static void xgmac_hwmacaddr(struct eth_device *dev)
static void xgmac_hwmacaddr(struct eth_pdata *pdata)
{
struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
struct xgmac_regs *regs = xgmac_get_regs(pdata);
u32 macaddr[2];
memcpy(macaddr, dev->enetaddr, 6);
memcpy(macaddr, pdata->enetaddr, ARP_HLEN);
writel(macaddr[1], &regs->macaddr[0].hi);
writel(macaddr[0], &regs->macaddr[0].lo);
}
static int xgmac_init(struct eth_device *dev, struct bd_info * bis)
static int xgmac_eth_start(struct udevice *dev)
{
struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
struct calxeda_eth_dev *priv = dev->priv;
int value;
struct eth_pdata *pdata = dev_get_plat(dev);
struct xgmac_regs *regs = xgmac_get_regs(pdata);
struct calxeda_eth_dev *priv = dev_get_priv(dev);
u32 value;
if (xgmac_reset(dev) < 0)
return -1;
if (xgmac_reset(regs) < 0)
return -ETIMEDOUT;
/* set the hardware MAC address */
xgmac_hwmacaddr(dev);
xgmac_hwmacaddr(pdata);
/* set the AXI bus modes */
value = XGMAC_DMA_BUSMODE_ATDS |
@ -401,8 +413,8 @@ static int xgmac_init(struct eth_device *dev, struct bd_info * bis)
writel(value, &regs->flow_control);
/* Initialize the descriptor chains */
init_rx_desc(priv);
init_tx_desc(priv);
init_rx_desc(pdata, priv);
init_tx_desc(pdata, priv);
/* must set to 0, or when started up will cause issues */
priv->tx_currdesc = 0;
@ -425,10 +437,11 @@ static int xgmac_init(struct eth_device *dev, struct bd_info * bis)
return 0;
}
static int xgmac_tx(struct eth_device *dev, void *packet, int length)
static int xgmac_tx(struct udevice *dev, void *packet, int length)
{
struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
struct calxeda_eth_dev *priv = dev->priv;
struct calxeda_eth_dev *priv = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_plat(dev);
struct xgmac_regs *regs = xgmac_get_regs(pdata);
u32 currdesc = priv->tx_currdesc;
struct xgmac_dma_desc *txdesc = &priv->tx_chain[currdesc];
int timeout;
@ -453,35 +466,45 @@ static int xgmac_tx(struct eth_device *dev, void *packet, int length)
return 0;
}
static int xgmac_rx(struct eth_device *dev)
static int xgmac_rx(struct udevice *dev, int flags, uchar **packetp)
{
struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
struct calxeda_eth_dev *priv = dev->priv;
struct calxeda_eth_dev *priv = dev_get_priv(dev);
u32 currdesc = priv->rx_currdesc;
struct xgmac_dma_desc *rxdesc = &priv->rx_chain[currdesc];
int length = 0;
/* check if the host has the desc */
if (desc_get_owner(rxdesc))
return -1; /* something bad happened */
return -EAGAIN; /* the MAC is still chewing on it */
length = desc_get_rx_frame_len(rxdesc);
net_process_received_packet(desc_get_buf_addr(rxdesc), length);
/* set descriptor back to owned by XGMAC */
desc_set_rx_owner(rxdesc);
writel(1, &regs->rxpoll);
*packetp = desc_get_buf_addr(rxdesc);
priv->rx_currdesc = (currdesc + 1) & (RX_NUM_DESC - 1);
return length;
}
static void xgmac_halt(struct eth_device *dev)
static int xgmac_free_pkt(struct udevice *dev, uchar *packet, int length)
{
struct xgmac_regs *regs = (struct xgmac_regs *)dev->iobase;
struct calxeda_eth_dev *priv = dev->priv;
struct eth_pdata *pdata = dev_get_plat(dev);
struct xgmac_regs *regs = xgmac_get_regs(pdata);
struct calxeda_eth_dev *priv = dev_get_priv(dev);
u32 rxdesc = ((char *)packet - priv->rxbuffer) / ETH_BUF_SZ;
struct xgmac_dma_desc *p = &priv->rx_chain[rxdesc];
/* set descriptor back to owned by XGMAC */
desc_set_rx_owner(p);
writel(1, &regs->rxpoll);
return 0;
}
static void xgmac_eth_stop(struct udevice *dev)
{
struct calxeda_eth_dev *priv = dev_get_priv(dev);
struct eth_pdata *pdata = dev_get_plat(dev);
struct xgmac_regs *regs = xgmac_get_regs(pdata);
int value;
/* Disable TX/RX */
@ -499,47 +522,88 @@ static void xgmac_halt(struct eth_device *dev)
priv->rx_currdesc = 0;
}
int calxedaxgmac_initialize(u32 id, ulong base_addr)
/*
* Changing the MAC address is not a good idea, as the fabric would
* need to know about this as well (it does not learn MAC addresses).
*/
static int xgmac_eth_write_hwaddr(struct udevice *dev)
{
struct eth_device *dev;
struct calxeda_eth_dev *priv;
struct xgmac_regs *regs;
return -ENOSYS;
}
static int xgmac_eth_read_rom_hwaddr(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
struct xgmac_regs *regs = xgmac_get_regs(pdata);
u32 macaddr[2];
regs = (struct xgmac_regs *)base_addr;
/* check hardware version */
if (readl(&regs->version) != 0x1012)
return -1;
dev = malloc(sizeof(*dev));
if (!dev)
return 0;
memset(dev, 0, sizeof(*dev));
/* Structure must be aligned, because it contains the descriptors */
priv = memalign(32, sizeof(*priv));
if (!priv) {
free(dev);
return 0;
}
dev->iobase = (int)base_addr;
dev->priv = priv;
priv->dev = dev;
sprintf(dev->name, "xgmac%d", id);
/* The MAC address is already configured, so read it from registers. */
macaddr[1] = readl(&regs->macaddr[0].hi);
macaddr[0] = readl(&regs->macaddr[0].lo);
memcpy(dev->enetaddr, macaddr, 6);
memcpy(pdata->enetaddr, macaddr, ARP_HLEN);
dev->init = xgmac_init;
dev->send = xgmac_tx;
dev->recv = xgmac_rx;
dev->halt = xgmac_halt;
eth_register(dev);
return 1;
return 0;
}
static int xgmac_ofdata_to_platdata(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
struct calxeda_eth_dev *priv;
/* Structure must be aligned, because it contains the descriptors */
priv = memalign(32, sizeof(*priv));
if (!priv)
return -ENOMEM;
dev_set_priv(dev, priv);
pdata->iobase = devfdt_get_addr(dev);
if (pdata->iobase == FDT_ADDR_T_NONE) {
printf("%s: Cannot find XGMAC base address\n", __func__);
return -EINVAL;
}
if (pdata->iobase >= (1ULL << 32)) {
printf("%s: MMIO base address cannot be above 4GB\n", __func__);
return -EINVAL;
}
return 0;
}
static int xgmac_eth_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_plat(dev);
struct xgmac_regs *regs = xgmac_get_regs(pdata);
/* check hardware version */
if (readl(&regs->version) != 0x1012)
return -ENODEV;
xgmac_eth_read_rom_hwaddr(dev);
return 0;
}
static const struct eth_ops xgmac_eth_ops = {
.start = xgmac_eth_start,
.send = xgmac_tx,
.recv = xgmac_rx,
.free_pkt = xgmac_free_pkt,
.stop = xgmac_eth_stop,
.write_hwaddr = xgmac_eth_write_hwaddr,
.read_rom_hwaddr = xgmac_eth_read_rom_hwaddr,
};
static const struct udevice_id xgmac_eth_ids[] = {
{ .compatible = "calxeda,hb-xgmac" },
{ }
};
U_BOOT_DRIVER(eth_xgmac) = {
.name = "eth_xgmac",
.id = UCLASS_ETH,
.of_match = xgmac_eth_ids,
.of_to_plat = xgmac_ofdata_to_platdata,
.probe = xgmac_eth_probe,
.ops = &xgmac_eth_ops,
.plat_auto = sizeof(struct eth_pdata),
};

20
drivers/net/octeontx/bgx.c
View File

@ -36,7 +36,6 @@ struct lmac {
int dmac;
u8 mac[6];
bool link_up;
bool init_pend;
int lmacid; /* ID within BGX */
int phy_addr; /* ID on board */
struct udevice *dev;
@ -849,6 +848,7 @@ static int bgx_lmac_enable(struct bgx *bgx, int8_t lmacid)
u64 cfg;
lmac = &bgx->lmac[lmacid];
lmac->bgx = bgx;
debug("%s: lmac: %p, lmacid = %d\n", __func__, lmac, lmacid);
@ -895,16 +895,6 @@ int bgx_poll_for_link(int node, int bgx_idx, int lmacid)
debug("%s: %d, lmac: %d/%d/%d %p\n",
__FILE__, __LINE__,
node, bgx_idx, lmacid, lmac);
if (lmac->init_pend) {
ret = bgx_lmac_enable(lmac->bgx, lmacid);
if (ret < 0) {
printf("BGX%d LMAC%d lmac_enable failed\n", bgx_idx,
lmacid);
return ret;
}
lmac->init_pend = 0;
mdelay(100);
}
if (lmac->qlm_mode == QLM_MODE_SGMII ||
lmac->qlm_mode == QLM_MODE_RGMII ||
lmac->qlm_mode == QLM_MODE_QSGMII) {
@ -1461,6 +1451,7 @@ int octeontx_bgx_remove(struct udevice *dev)
int octeontx_bgx_probe(struct udevice *dev)
{
int err;
struct bgx *bgx = dev_get_priv(dev);
u8 lmac = 0;
int qlm[4] = {-1, -1, -1, -1};
@ -1540,8 +1531,11 @@ skip_qlm_config:
struct lmac *tlmac = &bgx->lmac[lmac];
tlmac->dev = dev;
tlmac->init_pend = 1;
tlmac->bgx = bgx;
err = bgx_lmac_enable(bgx, lmac);
if (err) {
printf("BGX%d failed to enable lmac%d\n",
bgx->bgx_id, lmac);
}
}
return 0;

2
drivers/net/octeontx/smi.c
View File

@ -325,6 +325,8 @@ int octeontx_smi_probe(struct udevice *dev)
return -1;
}
node = fdt_node_offset_by_compatible(gd->fdt_blob, -1,
"cavium,thunder-8890-mdio-nexus");
fdt_for_each_subnode(subnode, gd->fdt_blob, node) {
ret = fdt_node_check_compatible(gd->fdt_blob, subnode,
"cavium,thunder-8890-mdio");

10
drivers/power/regulator/Kconfig
View File

@ -312,6 +312,16 @@ config DM_REGULATOR_STPMIC1
by the PMIC device. This driver is controlled by a device tree node
which includes voltage limits.
config DM_REGULATOR_ANATOP
bool "Enable driver for ANATOP regulators"
depends on DM_REGULATOR
select REGMAP
select SYSCON
help
Enable support for the Freescale i.MX on-chip ANATOP LDO
regulators. It is recommended that this option be enabled on
i.MX6 platform.
config SPL_DM_REGULATOR_STPMIC1
bool "Enable driver for STPMIC1 regulators in SPL"
depends on SPL_DM_REGULATOR && PMIC_STPMIC1

1
drivers/power/regulator/Makefile
View File

@ -31,3 +31,4 @@ obj-$(CONFIG_DM_REGULATOR_TPS62360) += tps62360_regulator.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_STPMIC1) += stpmic1.o
obj-$(CONFIG_DM_REGULATOR_TPS65941) += tps65941_regulator.o
obj-$(CONFIG_DM_REGULATOR_SCMI) += scmi_regulator.o
obj-$(CONFIG_$(SPL_)DM_REGULATOR_ANATOP) += anatop_regulator.o

278
drivers/power/regulator/anatop_regulator.c Normal file
View File

@ -0,0 +1,278 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
* Copyright (C) 2021 Linaro
*/
#include <common.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
#include <regmap.h>
#include <syscon.h>
#include <dm/device-internal.h>
#include <dm/device_compat.h>
#include <linux/bitops.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/ioport.h>
#include <power/pmic.h>
#include <power/regulator.h>
#define LDO_RAMP_UP_UNIT_IN_CYCLES 64 /* 64 cycles per step */
#define LDO_RAMP_UP_FREQ_IN_MHZ 24 /* cycle based on 24M OSC */
#define LDO_POWER_GATE 0x00
#define LDO_FET_FULL_ON 0x1f
#define BIT_WIDTH_MAX 32
#define ANATOP_REGULATOR_STEP 25000
#define MIN_DROPOUT_UV 125000
struct anatop_regulator {
const char *name;
struct regmap *regmap;
struct udevice *supply;
u32 control_reg;
u32 vol_bit_shift;
u32 vol_bit_width;
u32 min_bit_val;
u32 min_voltage;
u32 max_voltage;
u32 delay_reg;
u32 delay_bit_shift;
u32 delay_bit_width;
};
static u32 anatop_get_bits(struct udevice *dev, u32 addr, int bit_shift,
int bit_width)
{
const struct anatop_regulator *anatop_reg = dev_get_plat(dev);
int err;
u32 val, mask;
if (bit_width == BIT_WIDTH_MAX)
mask = ~0;
else
mask = (1 << bit_width) - 1;
err = regmap_read(anatop_reg->regmap, addr, &val);
if (err) {
dev_dbg(dev, "cannot read reg (%d)\n", err);
return err;
}
val = (val >> bit_shift) & mask;
return val;
}
static int anatop_set_bits(struct udevice *dev, u32 addr, int bit_shift,
int bit_width, u32 data)
{
const struct anatop_regulator *anatop_reg = dev_get_plat(dev);
int err;
u32 val, mask;
if (bit_width == 32)
mask = ~0;
else
mask = (1 << bit_width) - 1;
err = regmap_read(anatop_reg->regmap, addr, &val);
if (err) {
dev_dbg(dev, "cannot read reg (%d)\n", err);
return err;
}
val = val & ~(mask << bit_shift);
err = regmap_write(anatop_reg->regmap,
addr, (data << bit_shift) | val);
if (err) {
dev_dbg(dev, "cannot write reg (%d)\n", err);
return err;
}
return 0;
}
static int anatop_get_voltage(struct udevice *dev)
{
const struct anatop_regulator *anatop_reg = dev_get_plat(dev);
u32 sel;
u32 val;
if (!anatop_reg->control_reg)
return -ENOSYS;
val = anatop_get_bits(dev,
anatop_reg->control_reg,
anatop_reg->vol_bit_shift,
anatop_reg->vol_bit_width);
sel = val - anatop_reg->min_bit_val;
return sel * ANATOP_REGULATOR_STEP + anatop_reg->min_voltage;
}
static int anatop_set_voltage(struct udevice *dev, int uV)
{
const struct anatop_regulator *anatop_reg = dev_get_plat(dev);
u32 val;
u32 sel;
int ret;
dev_dbg(dev, "uv %d, min %d, max %d\n", uV, anatop_reg->min_voltage,
anatop_reg->max_voltage);
if (uV < anatop_reg->min_voltage)
return -EINVAL;
if (!anatop_reg->control_reg)
return -ENOSYS;
sel = DIV_ROUND_UP(uV - anatop_reg->min_voltage,
ANATOP_REGULATOR_STEP);
if (sel * ANATOP_REGULATOR_STEP + anatop_reg->min_voltage >
anatop_reg->max_voltage)
return -EINVAL;
val = anatop_reg->min_bit_val + sel;
dev_dbg(dev, "calculated val %d\n", val);
if (anatop_reg->supply) {
ret = regulator_set_value(anatop_reg->supply,
uV + MIN_DROPOUT_UV);
if (ret)
return ret;
}
ret = anatop_set_bits(dev,
anatop_reg->control_reg,
anatop_reg->vol_bit_shift,
anatop_reg->vol_bit_width,
val);
return ret;
}
static const struct dm_regulator_ops anatop_regulator_ops = {
.set_value = anatop_set_voltage,
.get_value = anatop_get_voltage,
};
static int anatop_regulator_probe(struct udevice *dev)
{
struct anatop_regulator *anatop_reg;
struct dm_regulator_uclass_plat *uc_pdata;
struct udevice *syscon;
int ret = 0;
u32 val;
anatop_reg = dev_get_plat(dev);
uc_pdata = dev_get_uclass_plat(dev);
anatop_reg->name = ofnode_read_string(dev_ofnode(dev),
"regulator-name");
if (!anatop_reg->name)
return log_msg_ret("regulator-name", -EINVAL);
ret = device_get_supply_regulator(dev, "vin-supply",
&anatop_reg->supply);
if (ret != -ENODEV) {
if (ret)
return log_msg_ret("get vin-supply", ret);
ret = regulator_set_enable(anatop_reg->supply, true);
if (ret)
return ret;
}
ret = dev_read_u32(dev,
"anatop-reg-offset",
&anatop_reg->control_reg);
if (ret)
return log_msg_ret("anatop-reg-offset", ret);
ret = dev_read_u32(dev,
"anatop-vol-bit-width",
&anatop_reg->vol_bit_width);
if (ret)
return log_msg_ret("anatop-vol-bit-width", ret);
ret = dev_read_u32(dev,
"anatop-vol-bit-shift",
&anatop_reg->vol_bit_shift);
if (ret)
return log_msg_ret("anatop-vol-bit-shift", ret);
ret = dev_read_u32(dev,
"anatop-min-bit-val",
&anatop_reg->min_bit_val);
if (ret)
return log_msg_ret("anatop-min-bit-val", ret);
ret = dev_read_u32(dev,
"anatop-min-voltage",
&anatop_reg->min_voltage);
if (ret)
return log_msg_ret("anatop-min-voltage", ret);
ret = dev_read_u32(dev,
"anatop-max-voltage",
&anatop_reg->max_voltage);
if (ret)
return log_msg_ret("anatop-max-voltage", ret);
/* read LDO ramp up setting, only for core reg */
dev_read_u32(dev, "anatop-delay-reg-offset",
&anatop_reg->delay_reg);
dev_read_u32(dev, "anatop-delay-bit-width",
&anatop_reg->delay_bit_width);
dev_read_u32(dev, "anatop-delay-bit-shift",
&anatop_reg->delay_bit_shift);
syscon = dev_get_parent(dev);
if (!syscon) {
dev_dbg(dev, "unable to find syscon device\n");
return -ENOENT;
}
anatop_reg->regmap = syscon_get_regmap(syscon);
if (IS_ERR(anatop_reg->regmap)) {
dev_dbg(dev, "unable to find regmap (%ld)\n",
PTR_ERR(anatop_reg->regmap));
return -ENOENT;
}
/* check whether need to care about LDO ramp up speed */
if (anatop_reg->delay_bit_width) {
/*
* the delay for LDO ramp up time is
* based on the register setting, we need
* to calculate how many steps LDO need to
* ramp up, and how much delay needed. (us)
*/
val = anatop_get_bits(dev,
anatop_reg->delay_reg,
anatop_reg->delay_bit_shift,
anatop_reg->delay_bit_width);
uc_pdata->ramp_delay = (LDO_RAMP_UP_UNIT_IN_CYCLES << val)
/ LDO_RAMP_UP_FREQ_IN_MHZ + 1;
}
return 0;
}
static const struct udevice_id of_anatop_regulator_match_tbl[] = {
{ .compatible = "fsl,anatop-regulator", },
{ /* end */ }
};
U_BOOT_DRIVER(anatop_regulator) = {
.name = "anatop_regulator",
.id = UCLASS_REGULATOR,
.ops = &anatop_regulator_ops,
.of_match = of_anatop_regulator_match_tbl,
.plat_auto = sizeof(struct anatop_regulator),
.probe = anatop_regulator_probe,
};

11
drivers/sysreset/sysreset-uclass.c
View File

@ -122,10 +122,19 @@ void reset_cpu(void)
#if IS_ENABLED(CONFIG_SYSRESET_CMD_RESET)
int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
enum sysreset_t reset_type = SYSRESET_COLD;
if (argc > 2)
return CMD_RET_USAGE;
if (argc == 2 && argv[1][0] == '-' && argv[1][1] == 'w') {
reset_type = SYSRESET_WARM;
}
printf("resetting ...\n");
mdelay(100);
sysreset_walk_halt(SYSRESET_COLD);
sysreset_walk_halt(reset_type);
return 0;
}

8
drivers/sysreset/sysreset_psci.c
View File

@ -11,22 +11,18 @@
static int psci_sysreset_request(struct udevice *dev, enum sysreset_t type)
{
unsigned long function_id;
switch (type) {
case SYSRESET_WARM:
case SYSRESET_COLD:
function_id = PSCI_0_2_FN_SYSTEM_RESET;
psci_sys_reset(type);
break;
case SYSRESET_POWER_OFF:
function_id = PSCI_0_2_FN_SYSTEM_OFF;
psci_sys_poweroff();
break;
default:
return -ENOSYS;
}
invoke_psci_fn(function_id, 0, 0, 0);
return -EINPROGRESS;
}

2
include/ata.h
View File

@ -134,7 +134,7 @@ typedef struct hd_driveid {
unsigned short cur_capacity1; /* (2 words, misaligned int) */
unsigned char multsect; /* current multiple sector count */
unsigned char multsect_valid; /* when (bit0==1) multsect is ok */
unsigned int lba_capacity; /* total number of sectors */
unsigned short lba_capacity[2];/* two words containing total number of sectors */
unsigned short dma_1word; /* single-word dma info */
unsigned short dma_mword; /* multiple-word dma info */
unsigned short eide_pio_modes; /* bits 0:mode3 1:mode4 */

13
include/configs/highbank.h
View File

@ -18,7 +18,6 @@
#define CONFIG_SYS_MALLOC_LEN (512 * 1024)
#define CONFIG_PL011_CLOCK 150000000
#define CONFIG_PL01x_PORTS { (void *)(0xFFF36000) }
#define CONFIG_SYS_BOOTCOUNT_LE /* Use little-endian accessors */
@ -28,8 +27,6 @@
#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
CONFIG_SYS_SCSI_MAX_LUN)
#define CONFIG_CALXEDA_XGMAC
#define CONFIG_BOOT_RETRY_TIME -1
#define CONFIG_RESET_TO_RETRY
@ -42,12 +39,6 @@
#define CONFIG_SYS_LOAD_ADDR 0x800000
#define CONFIG_SYS_64BIT_LBA
/*-----------------------------------------------------------------------
* Physical Memory Map
* The DRAM is already setup, so do not touch the DT node later.
*/
#define PHYS_SDRAM_1_SIZE (4089 << 20)
/* Environment data setup
*/
#define CONFIG_SYS_NVRAM_BASE_ADDR 0xfff88000 /* NVRAM base address */
@ -57,4 +48,8 @@
#define CONFIG_SYS_INIT_SP_ADDR 0x01000000
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_EXTRA_ENV_SETTINGS \
"fdt_high=0x20000000\0" \
"initrd_high=0x20000000\0"
#endif

31
include/configs/octeontx_common.h
View File

@ -8,7 +8,31 @@
#ifndef __OCTEONTX_COMMON_H__
#define __OCTEONTX_COMMON_H__
#define CONFIG_SUPPORT_RAW_INITRD
#ifdef CONFIG_DISTRO_DEFAULTS
#define BOOT_TARGET_DEVICES(func) \
func(MMC, mmc, 0) \
func(MMC, mmc, 1) \
func(USB, usb, 0) \
func(SCSI, scsi, 0)
#include <config_distro_bootcmd.h>
/* Extra environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
"autoload=0\0" \
"loadaddr=0x20080000\0" \
"kernel_addr_r=0x02000000\0" \
"ramdisk_addr_r=0x03000000\0" \
"scriptaddr=0x04000000\0" \
BOOTENV
#else
/** Extra environment settings */
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=20080000\0" \
"autoload=0\0"
#endif /* ifdef CONFIG_DISTRO_DEFAULTS*/
/** Maximum size of image supported for bootm (and bootable FIT images) */
#define CONFIG_SYS_BOOTM_LEN (256 << 20)
@ -52,11 +76,6 @@
# define CONFIG_SF_DEFAULT_CS 0
#endif
/** Extra environment settings */
#define CONFIG_EXTRA_ENV_SETTINGS \
"loadaddr=20080000\0" \
"autoload=0\0"
/** Environment defines */
#if defined(CONFIG_ENV_IS_IN_MMC)
#define CONFIG_SYS_MMC_ENV_DEV 0

31
include/linux/psci.h
View File

@ -46,6 +46,14 @@
#define PSCI_0_2_FN64_MIGRATE PSCI_0_2_FN64(5)
#define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU PSCI_0_2_FN64(7)
#define PSCI_1_0_FN_PSCI_FEATURES PSCI_0_2_FN(10)
#define PSCI_1_0_FN_SYSTEM_SUSPEND PSCI_0_2_FN(14)
#define PSCI_1_0_FN_SET_SUSPEND_MODE PSCI_0_2_FN(15)
#define PSCI_1_1_FN_SYSTEM_RESET2 PSCI_0_2_FN(18)
#define PSCI_1_0_FN64_SYSTEM_SUSPEND PSCI_0_2_FN64(14)
#define PSCI_1_1_FN64_SYSTEM_RESET2 PSCI_0_2_FN64(18)
/* PSCI v0.2 power state encoding for CPU_SUSPEND function */
#define PSCI_0_2_POWER_STATE_ID_MASK 0xffff
#define PSCI_0_2_POWER_STATE_ID_SHIFT 0
@ -56,6 +64,13 @@
#define PSCI_0_2_POWER_STATE_AFFL_MASK \
(0x3 << PSCI_0_2_POWER_STATE_AFFL_SHIFT)
/* PSCI extended power state encoding for CPU_SUSPEND function */
#define PSCI_1_0_EXT_POWER_STATE_ID_MASK 0xfffffff
#define PSCI_1_0_EXT_POWER_STATE_ID_SHIFT 0
#define PSCI_1_0_EXT_POWER_STATE_TYPE_SHIFT 30
#define PSCI_1_0_EXT_POWER_STATE_TYPE_MASK \
(0x1 << PSCI_1_0_EXT_POWER_STATE_TYPE_SHIFT)
/* PSCI v0.2 affinity level state returned by AFFINITY_INFO */
#define PSCI_0_2_AFFINITY_LEVEL_ON 0
#define PSCI_0_2_AFFINITY_LEVEL_OFF 1
@ -75,6 +90,18 @@
(((ver) & PSCI_VERSION_MAJOR_MASK) >> PSCI_VERSION_MAJOR_SHIFT)
#define PSCI_VERSION_MINOR(ver) \
((ver) & PSCI_VERSION_MINOR_MASK)
#define PSCI_VERSION(maj, min) \
((((maj) << PSCI_VERSION_MAJOR_SHIFT) & PSCI_VERSION_MAJOR_MASK) | \
((min) & PSCI_VERSION_MINOR_MASK))
/* PSCI features decoding (>=1.0) */
#define PSCI_1_0_FEATURES_CPU_SUSPEND_PF_SHIFT 1
#define PSCI_1_0_FEATURES_CPU_SUSPEND_PF_MASK \
(0x1 << PSCI_1_0_FEATURES_CPU_SUSPEND_PF_SHIFT)
#define PSCI_1_0_OS_INITIATED BIT(0)
#define PSCI_1_0_SUSPEND_MODE_PC 0
#define PSCI_1_0_SUSPEND_MODE_OSI 1
/* PSCI return values (inclusive of all PSCI versions) */
#define PSCI_RET_SUCCESS 0
@ -86,10 +113,14 @@
#define PSCI_RET_INTERNAL_FAILURE -6
#define PSCI_RET_NOT_PRESENT -7
#define PSCI_RET_DISABLED -8
#define PSCI_RET_INVALID_ADDRESS -9
#ifdef CONFIG_ARM_PSCI_FW
unsigned long invoke_psci_fn(unsigned long a0, unsigned long a1,
unsigned long a2, unsigned long a3);
void psci_sys_reset(u32 type);
void psci_sys_poweroff(void);
#else
static inline unsigned long invoke_psci_fn(unsigned long a0, unsigned long a1,
unsigned long a2, unsigned long a3)

1
include/netdev.h
View File

@ -33,7 +33,6 @@ int at91emac_register(struct bd_info *bis, unsigned long iobase);
int ax88180_initialize(struct bd_info *bis);
int bcm_sf2_eth_register(struct bd_info *bis, u8 dev_num);
int bfin_EMAC_initialize(struct bd_info *bis);
int calxedaxgmac_initialize(u32 id, ulong base_addr);
int cs8900_initialize(u8 dev_num, int base_addr);
int dc21x4x_initialize(struct bd_info *bis);
int designware_initialize(ulong base_addr, u32 interface);

4
include/sysinfo.h
View File

@ -4,6 +4,9 @@
* Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc
*/
#ifndef __SYSINFO_H__
#define __SYSINFO_H__
struct udevice;
/*
@ -228,3 +231,4 @@ static inline int sysinfo_get_fit_loadable(struct udevice *dev, int index,
}
#endif
#endif

15
lib/lz4_wrapper.c
View File

@ -11,9 +11,18 @@
#include <linux/types.h>
#include <asm/unaligned.h>
static u16 LZ4_readLE16(const void *src) { return le16_to_cpu(*(u16 *)src); }
static void LZ4_copy4(void *dst, const void *src) { *(u32 *)dst = *(u32 *)src; }
static void LZ4_copy8(void *dst, const void *src) { *(u64 *)dst = *(u64 *)src; }
static u16 LZ4_readLE16(const void *src)
{
return get_unaligned_le16(src);
}
static void LZ4_copy4(void *dst, const void *src)
{
put_unaligned(get_unaligned((const u32 *)src), (u32 *)dst);
}
static void LZ4_copy8(void *dst, const void *src)
{
put_unaligned(get_unaligned((const u64 *)src), (u64 *)dst);
}
typedef uint8_t BYTE;
typedef uint16_t U16;

6
scripts/Makefile.spl
View File

@ -67,6 +67,12 @@ include $(srctree)/scripts/Makefile.lib
KBUILD_CFLAGS += -ffunction-sections -fdata-sections
LDFLAGS_FINAL += --gc-sections
ifeq ($(CONFIG_$(SPL_TPL_)STACKPROTECTOR),y)
KBUILD_CFLAGS += -fstack-protector-strong
else
KBUILD_CFLAGS += -fno-stack-protector
endif
# FIX ME
cpp_flags := $(KBUILD_CPPFLAGS) $(PLATFORM_CPPFLAGS) $(UBOOTINCLUDE) \
$(NOSTDINC_FLAGS)

1
scripts/config_whitelist.txt
View File

@ -149,7 +149,6 @@ CONFIG_BTB
CONFIG_BUFNO_AUTO_INCR_BIT
CONFIG_BUILD_ENVCRC
CONFIG_BUS_WIDTH
CONFIG_CALXEDA_XGMAC
CONFIG_CDP_APPLIANCE_VLAN_TYPE
CONFIG_CDP_CAPABILITIES
CONFIG_CDP_DEVICE_ID

9
test/dm/regmap.c
View File

@ -286,7 +286,8 @@ U_BOOT_DRIVER(regmap_test) = {
static int dm_test_devm_regmap(struct unit_test_state *uts)
{
int i = 0;
u32 val;
u16 val;
void *valp = &val;
u16 pattern[REGMAP_TEST_BUF_SZ];
u16 *buffer;
struct udevice *dev;
@ -311,7 +312,7 @@ static int dm_test_devm_regmap(struct unit_test_state *uts)
ut_assertok(regmap_write(priv->cfg_regmap, i, pattern[i]));
}
for (i = 0; i < REGMAP_TEST_BUF_SZ; i++) {
ut_assertok(regmap_read(priv->cfg_regmap, i, &val));
ut_assertok(regmap_read(priv->cfg_regmap, i, valp));
ut_asserteq(val, buffer[i]);
ut_asserteq(val, pattern[i]);
}
@ -319,9 +320,9 @@ static int dm_test_devm_regmap(struct unit_test_state *uts)
ut_asserteq(-ERANGE, regmap_write(priv->cfg_regmap, REGMAP_TEST_BUF_SZ,
val));
ut_asserteq(-ERANGE, regmap_read(priv->cfg_regmap, REGMAP_TEST_BUF_SZ,
&val));
valp));
ut_asserteq(-ERANGE, regmap_write(priv->cfg_regmap, -1, val));
ut_asserteq(-ERANGE, regmap_read(priv->cfg_regmap, -1, &val));
ut_asserteq(-ERANGE, regmap_read(priv->cfg_regmap, -1, valp));
return 0;
}

14
test/py/tests/test_stackprotector.py Normal file
View File

@ -0,0 +1,14 @@
# SPDX-License-Identifier: GPL-2.0
# Copyright (c) 2021 Broadcom
import pytest
import signal
@pytest.mark.buildconfigspec('cmd_stackprotector_test')
def test_stackprotector(u_boot_console):
"""Test that the stackprotector function works."""
u_boot_console.run_command('stackprot_test',wait_for_prompt=False)
expected_response = 'Stack smashing detected'
u_boot_console.wait_for(expected_response)
u_boot_console.restart_uboot()