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https://github.com/brain-hackers/u-boot-brain
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powerpc: Remove configs/MPC8536DS_36BIT_defconfig board
DM_SPI and other driver model migration deadlines are expired for this board. Remove it. Patch-cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Jagan Teki
parent
447ec175b2
commit
8429b95167
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@ -56,14 +56,6 @@ config TARGET_P5040DS
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imply CMD_SATA
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imply PANIC_HANG
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config TARGET_MPC8536DS
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bool "Support MPC8536DS"
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select ARCH_MPC8536
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# Use DDR3 controller with DDR2 DIMMs on this board
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select SYS_FSL_DDRC_GEN3
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imply CMD_SATA
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imply FSL_SATA
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config TARGET_MPC8541CDS
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bool "Support MPC8541CDS"
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select ARCH_MPC8541
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@ -1557,7 +1549,6 @@ config SYS_FSL_LBC_CLK_DIV
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eLBC controller).
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source "board/freescale/corenet_ds/Kconfig"
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source "board/freescale/mpc8536ds/Kconfig"
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source "board/freescale/mpc8541cds/Kconfig"
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source "board/freescale/mpc8544ds/Kconfig"
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source "board/freescale/mpc8548cds/Kconfig"
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@ -1,12 +0,0 @@
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if TARGET_MPC8536DS
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config SYS_BOARD
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default "mpc8536ds"
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config SYS_VENDOR
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default "freescale"
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config SYS_CONFIG_NAME
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default "MPC8536DS"
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endif
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@ -1,9 +0,0 @@
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MPC8536DS BOARD
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M: Priyanka Jain <priyanka.jain@nxp.com>
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S: Maintained
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F: board/freescale/mpc8536ds/
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F: include/configs/MPC8536DS.h
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F: configs/MPC8536DS_defconfig
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F: configs/MPC8536DS_36BIT_defconfig
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F: configs/MPC8536DS_SDCARD_defconfig
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F: configs/MPC8536DS_SPIFLASH_defconfig
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@ -1,10 +0,0 @@
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# SPDX-License-Identifier: GPL-2.0+
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#
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# Copyright 2008 Freescale Semiconductor.
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# (C) Copyright 2001-2006
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# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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obj-y += mpc8536ds.o
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obj-y += ddr.o
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obj-y += law.o
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obj-y += tlb.o
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@ -1,127 +0,0 @@
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Overview:
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=========
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The MPC8536E integrates a PowerPC processor core with system logic
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required for imaging, networking, and communications applications.
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Boot from NAND:
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===============
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The MPC8536E is capable of booting from NAND flash which uses the image
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u-boot-nand.bin. This image contains two parts: a first stage image(also
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call 4K NAND loader and a second stage image. The former is appended to
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the latter to produce u-boot-nand.bin.
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The bootup process can be divided into two stages: the first stage will
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configure the L2SRAM, then copy the second stage image to L2SRAM and jump
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to it. The second stage image is to configure all the hardware and boot up
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to U-Boot command line.
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The 4K NAND loader's code comes from the corresponding nand_spl directory,
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along with the code twisted by CONFIG_NAND_SPL. The macro CONFIG_NAND_SPL
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is mainly used to shrink the code size to the 4K size limitation.
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The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the
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second stage image. It's set in the board config file when boot from NAND
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is selected.
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Build and boot steps
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--------------------
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1. Building image
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make MPC8536DS_NAND_config
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make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
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2. Change dip-switch
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SW2[5-8] = 1011
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SW9[1-3] = 101
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Note: 1 stands for 'on', 0 stands for 'off'
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3. Flash image
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tftp 1000000 u-boot-nand.bin
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nand erase 0 a0000
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nand write 1000000 0 a0000
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Boot from On-chip ROM:
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======================
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The MPC8536E is capable of booting from the on-chip ROM - boot from eSDHC
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and boot from eSPI. When power on, the porcessor excutes the ROM code to
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initialize the eSPI/eSDHC controller, and loads the mian U-Boot image from
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the memory device that interfaced to the controller, such as the SDCard or
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SPI EEPROM, to the target memory, e.g. SDRAM or L2SRAM, then boot from it.
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The memory device should contain a specific data structure with control word
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and config word at the fixed address. The config word direct the process how
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to config the memory device, and the control word direct the processor where
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to find the image on the memory device, or where copy the main image to. The
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user can use any method to store the data structure to the memory device, only
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if store it on the assigned address.
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Build and boot steps
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--------------------
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For boot from eSDHC:
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1. Build image
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make MPC8536DS_SDCARD_config
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make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
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2. Change dip-switch
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SW2[5-8] = 0111
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SW3[1] = 0
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SW8[7] = 0 - The on-board SD/MMC slot is active
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SW8[7] = 1 - The externel SD/MMC slot is active
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3. Put image to SDCard
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Put the follwing info at the assigned address on the SDCard:
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Offset | Data | Description
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--------------------------------------------------------
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| 0x40-0x43 | 0x424F4F54 | BOOT signature |
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--------------------------------------------------------
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| 0x48-0x4B | 0x00080000 | u-boot.bin's size |
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--------------------------------------------------------
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| 0x50-0x53 | 0x???????? | u-boot.bin's Addr on SDCard |
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--------------------------------------------------------
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| 0x58-0x5B | 0xF8F80000 | Target Address |
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-------------------------------------------------------
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| 0x60-0x63 | 0xF8FFF000 | Execution Starting Address |
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--------------------------------------------------------
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| 0x68-0x6B | 0x6 | Number of Config Addr/Data |
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--------------------------------------------------------
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| 0x80-0x83 | 0xFF720100 | Config Addr 1 |
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| 0x84-0x87 | 0xF8F80000 | Config Data 1 |
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--------------------------------------------------------
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| 0x88-0x8b | 0xFF720e44 | Config Addr 2 |
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| 0x8c-0x8f | 0x0000000C | Config Data 2 |
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--------------------------------------------------------
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| 0x90-0x93 | 0xFF720000 | Config Addr 3 |
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| 0x94-0x97 | 0x80010000 | Config Data 3 |
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--------------------------------------------------------
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| 0x98-0x9b | 0xFF72e40c | Config Addr 4 |
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| 0x9c-0x9f | 0x00000040 | Config Data 4 |
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--------------------------------------------------------
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| 0xa0-0xa3 | 0x40000001 | Config Addr 5 |
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| 0xa4-0xa7 | 0x00000100 | Config Data 5 |
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--------------------------------------------------------
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| 0xa8-0xab | 0x80000001 | Config Addr 6 |
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| 0xac-0xaf | 0x80000001 | Config Data 6 |
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--------------------------------------------------------
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| ...... |
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--------------------------------------------------------
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| 0x???????? | u-boot.bin |
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--------------------------------------------------------
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then insert the SDCard to the active slot to boot up.
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For boot from eSPI:
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1. Build image
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make MPC8536DS_SPIFLASH_config
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make CROSS_COMPILE=powerpc-none-linux-gnuspe- all
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2. Change dip-switch
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SW2[5-8] = 0110
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3. Put image to SPI flash
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Put the info in the above table onto the SPI flash, then
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boot up.
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@ -1,59 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <fsl_ddr_sdram.h>
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#include <fsl_ddr_dimm_params.h>
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void fsl_ddr_board_options(memctl_options_t *popts,
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dimm_params_t *pdimm,
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unsigned int ctrl_num)
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{
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/*
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* Factors to consider for clock adjust:
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* - number of chips on bus
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* - position of slot
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* - DDR1 vs. DDR2?
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* - ???
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*
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* This needs to be determined on a board-by-board basis.
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* 0110 3/4 cycle late
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* 0111 7/8 cycle late
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*/
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popts->clk_adjust = 7;
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/*
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* Factors to consider for CPO:
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* - frequency
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* - ddr1 vs. ddr2
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*/
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popts->cpo_override = 10;
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/*
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* Factors to consider for write data delay:
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* - number of DIMMs
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*
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* 1 = 1/4 clock delay
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* 2 = 1/2 clock delay
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* 3 = 3/4 clock delay
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* 4 = 1 clock delay
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* 5 = 5/4 clock delay
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* 6 = 3/2 clock delay
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*/
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popts->write_data_delay = 3;
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/*
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* Factors to consider for half-strength driver enable:
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* - number of DIMMs installed
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*/
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popts->half_strength_driver_enable = 0;
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/*
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* For wake up arp feature, we need enable auto self refresh
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*/
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popts->auto_self_refresh_en = 1;
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popts->sr_it = 0x6;
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}
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@ -1,19 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2008 Freescale Semiconductor, Inc.
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*
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* (C) Copyright 2000
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* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
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*/
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#include <common.h>
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#include <asm/fsl_law.h>
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#include <asm/mmu.h>
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struct law_entry law_table[] = {
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SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
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SET_LAW(PIXIS_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
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SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
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};
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int num_law_entries = ARRAY_SIZE(law_table);
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@ -1,293 +0,0 @@
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// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2008-2012 Freescale Semiconductor, Inc.
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*/
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#include <common.h>
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#include <command.h>
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#include <init.h>
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#include <log.h>
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#include <net.h>
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#include <pci.h>
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#include <asm/processor.h>
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#include <asm/mmu.h>
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#include <asm/cache.h>
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#include <asm/immap_85xx.h>
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#include <asm/fsl_pci.h>
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#include <fsl_ddr_sdram.h>
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#include <asm/io.h>
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#include <asm/fsl_serdes.h>
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#include <spd.h>
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#include <miiphy.h>
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#include <linux/delay.h>
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#include <linux/libfdt.h>
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#include <spd_sdram.h>
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#include <fdt_support.h>
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#include <fsl_mdio.h>
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#include <tsec.h>
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#include <netdev.h>
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#include <sata.h>
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#include "../common/sgmii_riser.h"
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int board_early_init_f (void)
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{
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#ifdef CONFIG_MMC
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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setbits_be32(&gur->pmuxcr,
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(MPC85xx_PMUXCR_SDHC_CD |
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MPC85xx_PMUXCR_SDHC_WP));
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/* The MPC8536DS board insert the SDHC_WP pin for erratum NMG_eSDHC118,
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* however, this erratum only applies to MPC8536 Rev1.0.
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* So set SDHC_WP to active-low when use MPC8536 Rev1.1 and greater.*/
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if ((((SVR_MAJ(get_svr()) & 0x7) == 0x1) &&
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(SVR_MIN(get_svr()) >= 0x1))
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|| (SVR_MAJ(get_svr() & 0x7) > 0x1))
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setbits_be32(&gur->gencfgr, MPC85xx_GENCFGR_SDHC_WP_INV);
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#endif
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return 0;
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}
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int checkboard (void)
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{
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u8 vboot;
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u8 *pixis_base = (u8 *)PIXIS_BASE;
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printf("Board: MPC8536DS Sys ID: 0x%02x, "
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"Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
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in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
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in_8(pixis_base + PIXIS_PVER));
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vboot = in_8(pixis_base + PIXIS_VBOOT);
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switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
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case PIXIS_VBOOT_LBMAP_NOR0:
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puts ("vBank: 0\n");
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break;
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case PIXIS_VBOOT_LBMAP_NOR1:
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puts ("vBank: 1\n");
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break;
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case PIXIS_VBOOT_LBMAP_NOR2:
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puts ("vBank: 2\n");
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break;
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case PIXIS_VBOOT_LBMAP_NOR3:
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puts ("vBank: 3\n");
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break;
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case PIXIS_VBOOT_LBMAP_PJET:
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puts ("Promjet\n");
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break;
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case PIXIS_VBOOT_LBMAP_NAND:
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puts ("NAND\n");
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break;
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}
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return 0;
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}
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#if !defined(CONFIG_SPD_EEPROM)
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/*
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* Fixed sdram init -- doesn't use serial presence detect.
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*/
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phys_size_t fixed_sdram (void)
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{
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volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
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struct ccsr_ddr __iomem *ddr = &immap->im_ddr;
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uint d_init;
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ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
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ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
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ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
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ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
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ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
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ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
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ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
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ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
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ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
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ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
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ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
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ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
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#if defined (CONFIG_DDR_ECC)
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ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
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ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
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ddr->err_sbe = CONFIG_SYS_DDR_SBE;
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#endif
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asm("sync;isync");
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udelay(500);
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ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
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#if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
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d_init = 1;
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debug("DDR - 1st controller: memory initializing\n");
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/*
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* Poll until memory is initialized.
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* 512 Meg at 400 might hit this 200 times or so.
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*/
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while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
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udelay(1000);
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}
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debug("DDR: memory initialized\n\n");
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asm("sync; isync");
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udelay(500);
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#endif
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return 512 * 1024 * 1024;
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}
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#endif
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#ifdef CONFIG_PCI1
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static struct pci_controller pci1_hose;
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#endif
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#ifdef CONFIG_PCI
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void pci_init_board(void)
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{
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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struct fsl_pci_info pci_info;
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u32 devdisr, pordevsr;
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u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
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int first_free_busno;
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first_free_busno = fsl_pcie_init_board(0);
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#ifdef CONFIG_PCI1
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devdisr = in_be32(&gur->devdisr);
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pordevsr = in_be32(&gur->pordevsr);
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porpllsr = in_be32(&gur->porpllsr);
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pci_speed = 66666000;
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pci_32 = 1;
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pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
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pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
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if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
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SET_STD_PCI_INFO(pci_info, 1);
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set_next_law(pci_info.mem_phys,
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law_size_bits(pci_info.mem_size), pci_info.law);
|
||||
set_next_law(pci_info.io_phys,
|
||||
law_size_bits(pci_info.io_size), pci_info.law);
|
||||
|
||||
pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
|
||||
printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
|
||||
(pci_32) ? 32 : 64,
|
||||
(pci_speed == 33333000) ? "33" :
|
||||
(pci_speed == 66666000) ? "66" : "unknown",
|
||||
pci_clk_sel ? "sync" : "async",
|
||||
pci_agent ? "agent" : "host",
|
||||
pci_arb ? "arbiter" : "external-arbiter",
|
||||
pci_info.regs);
|
||||
|
||||
first_free_busno = fsl_pci_init_port(&pci_info,
|
||||
&pci1_hose, first_free_busno);
|
||||
} else {
|
||||
printf("PCI: disabled\n");
|
||||
}
|
||||
|
||||
puts("\n");
|
||||
#else
|
||||
setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
int board_early_init_r(void)
|
||||
{
|
||||
const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
|
||||
int flash_esel = find_tlb_idx((void *)flashbase, 1);
|
||||
|
||||
/*
|
||||
* Remap Boot flash + PROMJET region to caching-inhibited
|
||||
* so that flash can be erased properly.
|
||||
*/
|
||||
|
||||
/* Flush d-cache and invalidate i-cache of any FLASH data */
|
||||
flush_dcache();
|
||||
invalidate_icache();
|
||||
|
||||
if (flash_esel == -1) {
|
||||
/* very unlikely unless something is messed up */
|
||||
puts("Error: Could not find TLB for FLASH BASE\n");
|
||||
flash_esel = 1; /* give our best effort to continue */
|
||||
} else {
|
||||
/* invalidate existing TLB entry for flash + promjet */
|
||||
disable_tlb(flash_esel);
|
||||
}
|
||||
|
||||
set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
|
||||
0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int board_eth_init(bd_t *bis)
|
||||
{
|
||||
#ifdef CONFIG_TSEC_ENET
|
||||
struct fsl_pq_mdio_info mdio_info;
|
||||
struct tsec_info_struct tsec_info[2];
|
||||
int num = 0;
|
||||
|
||||
#ifdef CONFIG_TSEC1
|
||||
SET_STD_TSEC_INFO(tsec_info[num], 1);
|
||||
if (is_serdes_configured(SGMII_TSEC1)) {
|
||||
puts("eTSEC1 is in sgmii mode.\n");
|
||||
tsec_info[num].phyaddr = 0;
|
||||
tsec_info[num].flags |= TSEC_SGMII;
|
||||
}
|
||||
num++;
|
||||
#endif
|
||||
#ifdef CONFIG_TSEC3
|
||||
SET_STD_TSEC_INFO(tsec_info[num], 3);
|
||||
if (is_serdes_configured(SGMII_TSEC3)) {
|
||||
puts("eTSEC3 is in sgmii mode.\n");
|
||||
tsec_info[num].phyaddr = 1;
|
||||
tsec_info[num].flags |= TSEC_SGMII;
|
||||
}
|
||||
num++;
|
||||
#endif
|
||||
|
||||
if (!num) {
|
||||
printf("No TSECs initialized\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_FSL_SGMII_RISER
|
||||
if (is_serdes_configured(SGMII_TSEC1) ||
|
||||
is_serdes_configured(SGMII_TSEC3)) {
|
||||
fsl_sgmii_riser_init(tsec_info, num);
|
||||
}
|
||||
#endif
|
||||
|
||||
mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
|
||||
mdio_info.name = DEFAULT_MII_NAME;
|
||||
fsl_pq_mdio_init(bis, &mdio_info);
|
||||
|
||||
tsec_eth_init(bis, tsec_info, num);
|
||||
#endif
|
||||
return pci_eth_init(bis);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF_BOARD_SETUP)
|
||||
int ft_board_setup(void *blob, bd_t *bd)
|
||||
{
|
||||
ft_cpu_setup(blob, bd);
|
||||
|
||||
FT_FSL_PCI_SETUP;
|
||||
|
||||
#ifdef CONFIG_FSL_SGMII_RISER
|
||||
fsl_sgmii_riser_fdt_fixup(blob);
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HAS_FSL_MPH_USB
|
||||
fsl_fdt_fixup_dr_usb(blob, bd);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
|
@ -1,70 +0,0 @@
|
|||
// SPDX-License-Identifier: GPL-2.0+
|
||||
/*
|
||||
* Copyright 2008 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* (C) Copyright 2000
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*/
|
||||
|
||||
#include <common.h>
|
||||
#include <asm/mmu.h>
|
||||
|
||||
struct fsl_e_tlb_entry tlb_table[] = {
|
||||
/* TLB 0 - for temp stack in cache */
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, 0,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
|
||||
SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 0, BOOKE_PAGESZ_4K, 0),
|
||||
|
||||
/* TLB 1 */
|
||||
/* *I*G* - CCSRBAR */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 0, BOOKE_PAGESZ_1M, 1),
|
||||
|
||||
/* W**G* - Flash/promjet, localbus */
|
||||
/* This will be changed to *I*G* after relocation to RAM. */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
|
||||
0, 1, BOOKE_PAGESZ_256M, 1),
|
||||
|
||||
/* *I*G* - PCI */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 2, BOOKE_PAGESZ_1G, 1),
|
||||
|
||||
/* *I*G* - PCI I/O */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 3, BOOKE_PAGESZ_256K, 1),
|
||||
|
||||
/* *I*G - NAND */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 4, BOOKE_PAGESZ_1M, 1),
|
||||
|
||||
#if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
|
||||
/* *I*G - L2SRAM */
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 5, BOOKE_PAGESZ_256K, 1),
|
||||
SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
|
||||
CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
|
||||
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
|
||||
0, 6, BOOKE_PAGESZ_256K, 1),
|
||||
#endif
|
||||
};
|
||||
|
||||
int num_tlb_entries = ARRAY_SIZE(tlb_table);
|
||||
|
|
@ -1,61 +0,0 @@
|
|||
CONFIG_PPC=y
|
||||
CONFIG_SYS_TEXT_BASE=0xEFF40000
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_SECT_SIZE=0x20000
|
||||
CONFIG_MPC85xx=y
|
||||
# CONFIG_CMD_ERRATA is not set
|
||||
CONFIG_TARGET_MPC8536DS=y
|
||||
CONFIG_PHYS_64BIT=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
# CONFIG_MISC_INIT_R is not set
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_IMLS=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
# CONFIG_CMD_HASH is not set
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_ENV_ADDR=0xEFF20000
|
||||
CONFIG_SYS_FSL_DDR2=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_PHY_BROADCOM=y
|
||||
CONFIG_PHY_DAVICOM=y
|
||||
CONFIG_PHY_LXT=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_TSEC_ENET=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_FSL_ESPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_VIDEO=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
@ -1,60 +0,0 @@
|
|||
CONFIG_PPC=y
|
||||
CONFIG_SYS_TEXT_BASE=0xf8f40000
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_OFFSET=0x0
|
||||
CONFIG_MPC85xx=y
|
||||
# CONFIG_CMD_ERRATA is not set
|
||||
CONFIG_TARGET_MPC8536DS=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SDCARD"
|
||||
CONFIG_BOOTDELAY=10
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
# CONFIG_MISC_INIT_R is not set
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_IMLS=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
# CONFIG_CMD_HASH is not set
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_ENV_IS_IN_MMC=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_SYS_FSL_DDR2=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_PHY_BROADCOM=y
|
||||
CONFIG_PHY_DAVICOM=y
|
||||
CONFIG_PHY_LXT=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_TSEC_ENET=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_FSL_ESPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_VIDEO=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
@ -1,61 +0,0 @@
|
|||
CONFIG_PPC=y
|
||||
CONFIG_SYS_TEXT_BASE=0xf8f40000
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_OFFSET=0xF0000
|
||||
CONFIG_ENV_SECT_SIZE=0x10000
|
||||
CONFIG_MPC85xx=y
|
||||
# CONFIG_CMD_ERRATA is not set
|
||||
CONFIG_TARGET_MPC8536DS=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_SYS_EXTRA_OPTIONS="SPIFLASH"
|
||||
CONFIG_BOOTDELAY=10
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
# CONFIG_MISC_INIT_R is not set
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_IMLS=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
# CONFIG_CMD_HASH is not set
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_ENV_IS_IN_SPI_FLASH=y
|
||||
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
|
||||
CONFIG_SYS_FSL_DDR2=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_PHY_BROADCOM=y
|
||||
CONFIG_PHY_DAVICOM=y
|
||||
CONFIG_PHY_LXT=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_TSEC_ENET=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_FSL_ESPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_VIDEO=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
@ -1,60 +0,0 @@
|
|||
CONFIG_PPC=y
|
||||
CONFIG_SYS_TEXT_BASE=0xEFF40000
|
||||
CONFIG_ENV_SIZE=0x2000
|
||||
CONFIG_ENV_SECT_SIZE=0x20000
|
||||
CONFIG_MPC85xx=y
|
||||
# CONFIG_CMD_ERRATA is not set
|
||||
CONFIG_TARGET_MPC8536DS=y
|
||||
CONFIG_OF_BOARD_SETUP=y
|
||||
CONFIG_OF_STDOUT_VIA_ALIAS=y
|
||||
CONFIG_BOOTDELAY=10
|
||||
# CONFIG_CONSOLE_MUX is not set
|
||||
# CONFIG_MISC_INIT_R is not set
|
||||
CONFIG_BOARD_EARLY_INIT_F=y
|
||||
CONFIG_BOARD_EARLY_INIT_R=y
|
||||
CONFIG_HUSH_PARSER=y
|
||||
CONFIG_CMD_IMLS=y
|
||||
CONFIG_CMD_I2C=y
|
||||
CONFIG_CMD_MMC=y
|
||||
CONFIG_CMD_PCI=y
|
||||
CONFIG_CMD_SF=y
|
||||
CONFIG_CMD_USB=y
|
||||
CONFIG_CMD_DHCP=y
|
||||
CONFIG_CMD_MII=y
|
||||
CONFIG_CMD_PING=y
|
||||
# CONFIG_CMD_HASH is not set
|
||||
CONFIG_CMD_EXT2=y
|
||||
CONFIG_CMD_FAT=y
|
||||
CONFIG_ENV_IS_IN_FLASH=y
|
||||
CONFIG_ENV_ADDR=0xEFF20000
|
||||
CONFIG_SYS_FSL_DDR2=y
|
||||
CONFIG_FSL_ESDHC=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_NOR_FLASH=y
|
||||
CONFIG_FLASH_CFI_DRIVER=y
|
||||
CONFIG_SYS_FLASH_CFI=y
|
||||
CONFIG_MTD_RAW_NAND=y
|
||||
CONFIG_SPI_FLASH=y
|
||||
CONFIG_SF_DEFAULT_MODE=0
|
||||
CONFIG_SF_DEFAULT_SPEED=10000000
|
||||
CONFIG_SPI_FLASH_SPANSION=y
|
||||
CONFIG_PHY_ATHEROS=y
|
||||
CONFIG_PHY_BROADCOM=y
|
||||
CONFIG_PHY_DAVICOM=y
|
||||
CONFIG_PHY_LXT=y
|
||||
CONFIG_PHY_MARVELL=y
|
||||
CONFIG_PHY_NATSEMI=y
|
||||
CONFIG_PHY_REALTEK=y
|
||||
CONFIG_PHY_SMSC=y
|
||||
CONFIG_PHY_VITESSE=y
|
||||
CONFIG_PHY_GIGE=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_MII=y
|
||||
CONFIG_TSEC_ENET=y
|
||||
CONFIG_SYS_NS16550=y
|
||||
CONFIG_SPI=y
|
||||
CONFIG_FSL_ESPI=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_VIDEO=y
|
||||
CONFIG_OF_LIBFDT=y
|
||||
|
|
@ -1,642 +0,0 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0+ */
|
||||
/*
|
||||
* Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc.
|
||||
*/
|
||||
|
||||
/*
|
||||
* mpc8536ds board configuration file
|
||||
*
|
||||
*/
|
||||
#ifndef __CONFIG_H
|
||||
#define __CONFIG_H
|
||||
|
||||
#include <linux/stringify.h>
|
||||
|
||||
#include "../board/freescale/common/ics307_clk.h"
|
||||
|
||||
#ifdef CONFIG_SDCARD
|
||||
#define CONFIG_RAMBOOT_SDCARD 1
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_SPIFLASH
|
||||
#define CONFIG_RAMBOOT_SPIFLASH 1
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_RESET_VECTOR_ADDRESS
|
||||
#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
|
||||
#endif
|
||||
|
||||
#ifndef CONFIG_SYS_MONITOR_BASE
|
||||
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
|
||||
#endif
|
||||
|
||||
#define CONFIG_PCI1 1 /* Enable PCI controller 1 */
|
||||
#define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */
|
||||
#define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */
|
||||
#define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */
|
||||
#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
|
||||
#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
|
||||
#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
|
||||
|
||||
|
||||
#define CONFIG_ENV_OVERWRITE
|
||||
|
||||
#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
|
||||
#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
|
||||
#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
|
||||
|
||||
/*
|
||||
* These can be toggled for performance analysis, otherwise use default.
|
||||
*/
|
||||
#define CONFIG_L2_CACHE /* toggle L2 cache */
|
||||
#define CONFIG_BTB /* toggle branch predition */
|
||||
|
||||
#define CONFIG_ENABLE_36BIT_PHYS 1
|
||||
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_ADDR_MAP 1
|
||||
#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Config the L2 Cache as L2 SRAM
|
||||
*/
|
||||
#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull
|
||||
#else
|
||||
#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
|
||||
#endif
|
||||
#define CONFIG_SYS_L2_SIZE (512 << 10)
|
||||
#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
|
||||
|
||||
#define CONFIG_SYS_CCSRBAR 0xffe00000
|
||||
#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
|
||||
|
||||
#if defined(CONFIG_NAND_SPL)
|
||||
#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
|
||||
#endif
|
||||
|
||||
/* DDR Setup */
|
||||
#define CONFIG_VERY_BIG_RAM
|
||||
#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
|
||||
#define CONFIG_DDR_SPD
|
||||
|
||||
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
|
||||
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
|
||||
|
||||
#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
|
||||
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
|
||||
|
||||
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
|
||||
#define CONFIG_CHIP_SELECTS_PER_CTRL 2
|
||||
|
||||
/* I2C addresses of SPD EEPROMs */
|
||||
#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
|
||||
#define CONFIG_SYS_SPD_BUS_NUM 1
|
||||
|
||||
/* These are used when DDR doesn't use SPD. */
|
||||
#define CONFIG_SYS_SDRAM_SIZE 256 /* DDR is 256MB */
|
||||
#define CONFIG_SYS_DDR_CS0_BNDS 0x0000001F
|
||||
#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010102 /* Enable, no interleaving */
|
||||
#define CONFIG_SYS_DDR_TIMING_3 0x00000000
|
||||
#define CONFIG_SYS_DDR_TIMING_0 0x00260802
|
||||
#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
|
||||
#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
|
||||
#define CONFIG_SYS_DDR_MODE_1 0x00480432
|
||||
#define CONFIG_SYS_DDR_MODE_2 0x00000000
|
||||
#define CONFIG_SYS_DDR_INTERVAL 0x06180100
|
||||
#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
|
||||
#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
|
||||
#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
|
||||
#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
|
||||
#define CONFIG_SYS_DDR_CONTROL 0xC3008000 /* Type = DDR2 */
|
||||
#define CONFIG_SYS_DDR_CONTROL2 0x04400010
|
||||
|
||||
#define CONFIG_SYS_DDR_ERR_INT_EN 0x0000000d
|
||||
#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
|
||||
#define CONFIG_SYS_DDR_SBE 0x00010000
|
||||
|
||||
/* Make sure required options are set */
|
||||
#ifndef CONFIG_SPD_EEPROM
|
||||
#error ("CONFIG_SPD_EEPROM is required")
|
||||
#endif
|
||||
|
||||
#undef CONFIG_CLOCKS_IN_MHZ
|
||||
|
||||
/*
|
||||
* Memory map -- xxx -this is wrong, needs updating
|
||||
*
|
||||
* 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
|
||||
* 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
|
||||
* 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
|
||||
* 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
|
||||
*
|
||||
* Localbus cacheable (TBD)
|
||||
* 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
|
||||
*
|
||||
* Localbus non-cacheable
|
||||
* 0xe000_0000 0xe7ff_ffff Promjet/free 128M non-cacheable
|
||||
* 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
|
||||
* 0xffa0_0000 0xffaf_ffff NAND 1M non-cacheable
|
||||
* 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
|
||||
* 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
|
||||
* 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
|
||||
*/
|
||||
|
||||
/*
|
||||
* Local Bus Definitions
|
||||
*/
|
||||
#define CONFIG_SYS_FLASH_BASE 0xe0000000 /* start of FLASH 128M */
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe0000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
|
||||
#endif
|
||||
|
||||
#define CONFIG_FLASH_BR_PRELIM \
|
||||
(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) | BR_PS_16 | BR_V)
|
||||
#define CONFIG_FLASH_OR_PRELIM 0xf8000ff7
|
||||
|
||||
#define CONFIG_SYS_BR1_PRELIM \
|
||||
(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
|
||||
| BR_PS_16 | BR_V)
|
||||
#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
|
||||
|
||||
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000, \
|
||||
CONFIG_SYS_FLASH_BASE_PHYS }
|
||||
#define CONFIG_SYS_FLASH_QUIET_TEST
|
||||
#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
|
||||
|
||||
#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
|
||||
#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
|
||||
#undef CONFIG_SYS_FLASH_CHECKSUM
|
||||
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
|
||||
#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
|
||||
|
||||
#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH)
|
||||
#define CONFIG_SYS_RAMBOOT
|
||||
#else
|
||||
#undef CONFIG_SYS_RAMBOOT
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_FLASH_EMPTY_INFO
|
||||
#define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
|
||||
|
||||
#define CONFIG_HWCONFIG /* enable hwconfig */
|
||||
#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */
|
||||
#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define PIXIS_BASE_PHYS 0xfffdf0000ull
|
||||
#else
|
||||
#define PIXIS_BASE_PHYS PIXIS_BASE
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
|
||||
#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
|
||||
|
||||
#define PIXIS_ID 0x0 /* Board ID at offset 0 */
|
||||
#define PIXIS_VER 0x1 /* Board version at offset 1 */
|
||||
#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */
|
||||
#define PIXIS_CSR 0x3 /* PIXIS General control/status register */
|
||||
#define PIXIS_RST 0x4 /* PIXIS Reset Control register */
|
||||
#define PIXIS_PWR 0x5 /* PIXIS Power status register */
|
||||
#define PIXIS_AUX 0x6 /* Auxiliary 1 register */
|
||||
#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */
|
||||
#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */
|
||||
#define PIXIS_VCTL 0x10 /* VELA Control Register */
|
||||
#define PIXIS_VSTAT 0x11 /* VELA Status Register */
|
||||
#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */
|
||||
#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */
|
||||
#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */
|
||||
#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */
|
||||
#define PIXIS_VBOOT_LBMAP 0xe0 /* VBOOT - CFG_LBMAP */
|
||||
#define PIXIS_VBOOT_LBMAP_NOR0 0x00 /* cfg_lbmap - boot from NOR 0 */
|
||||
#define PIXIS_VBOOT_LBMAP_NOR1 0x01 /* cfg_lbmap - boot from NOR 1 */
|
||||
#define PIXIS_VBOOT_LBMAP_NOR2 0x02 /* cfg_lbmap - boot from NOR 2 */
|
||||
#define PIXIS_VBOOT_LBMAP_NOR3 0x03 /* cfg_lbmap - boot from NOR 3 */
|
||||
#define PIXIS_VBOOT_LBMAP_PJET 0x04 /* cfg_lbmap - boot from projet */
|
||||
#define PIXIS_VBOOT_LBMAP_NAND 0x05 /* cfg_lbmap - boot from NAND */
|
||||
#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */
|
||||
#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */
|
||||
#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */
|
||||
#define PIXIS_VSYSCLK0 0x1A /* VELA SYSCLK0 Register */
|
||||
#define PIXIS_VSYSCLK1 0x1B /* VELA SYSCLK1 Register */
|
||||
#define PIXIS_VSYSCLK2 0x1C /* VELA SYSCLK2 Register */
|
||||
#define PIXIS_VDDRCLK0 0x1D /* VELA DDRCLK0 Register */
|
||||
#define PIXIS_VDDRCLK1 0x1E /* VELA DDRCLK1 Register */
|
||||
#define PIXIS_VDDRCLK2 0x1F /* VELA DDRCLK2 Register */
|
||||
#define PIXIS_VWATCH 0x24 /* Watchdog Register */
|
||||
#define PIXIS_LED 0x25 /* LED Register */
|
||||
|
||||
#define PIXIS_SPD_SYSCLK 0x7 /* SYSCLK option */
|
||||
|
||||
/* old pixis referenced names */
|
||||
#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */
|
||||
#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */
|
||||
#define CONFIG_SYS_PIXIS_VBOOT_MASK 0x4e
|
||||
|
||||
#define CONFIG_SYS_INIT_RAM_LOCK 1
|
||||
#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
|
||||
#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
|
||||
|
||||
#define CONFIG_SYS_GBL_DATA_OFFSET \
|
||||
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
|
||||
#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
|
||||
|
||||
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
|
||||
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
|
||||
|
||||
#ifndef CONFIG_NAND_SPL
|
||||
#define CONFIG_SYS_NAND_BASE 0xffa00000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS 0xfffa00000ull
|
||||
#else
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
|
||||
#endif
|
||||
#else
|
||||
#define CONFIG_SYS_NAND_BASE 0xfff00000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS 0xffff00000ull
|
||||
#else
|
||||
#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
|
||||
#endif
|
||||
#endif
|
||||
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE,\
|
||||
CONFIG_SYS_NAND_BASE + 0x40000, \
|
||||
CONFIG_SYS_NAND_BASE + 0x80000, \
|
||||
CONFIG_SYS_NAND_BASE + 0xC0000}
|
||||
#define CONFIG_SYS_MAX_NAND_DEVICE 4
|
||||
#define CONFIG_NAND_FSL_ELBC 1
|
||||
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
|
||||
|
||||
/* NAND boot: 4K NAND loader config */
|
||||
#define CONFIG_SYS_NAND_SPL_SIZE 0x1000
|
||||
#define CONFIG_SYS_NAND_U_BOOT_SIZE ((768 << 10) - 0x2000)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_DST (CONFIG_SYS_INIT_L2_ADDR)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_START \
|
||||
(CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_NAND_SPL_SIZE)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_OFFS (0)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_RELOC (CONFIG_SYS_INIT_L2_END - 0x2000)
|
||||
#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
|
||||
|
||||
/* NAND flash config */
|
||||
#define CONFIG_SYS_NAND_BR_PRELIM \
|
||||
(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
|
||||
| OR_FCM_PGS /* Large Page*/ \
|
||||
| OR_FCM_CSCT \
|
||||
| OR_FCM_CST \
|
||||
| OR_FCM_CHT \
|
||||
| OR_FCM_SCY_1 \
|
||||
| OR_FCM_TRLX \
|
||||
| OR_FCM_EHTR)
|
||||
|
||||
#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
|
||||
#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
|
||||
#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
|
||||
#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
|
||||
|
||||
#define CONFIG_SYS_BR4_PRELIM \
|
||||
(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x40000) \
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR4_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
|
||||
#define CONFIG_SYS_BR5_PRELIM \
|
||||
(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0x80000) \
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR5_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
|
||||
|
||||
#define CONFIG_SYS_BR6_PRELIM \
|
||||
(BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS + 0xc0000) \
|
||||
| (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
|
||||
| BR_PS_8 /* Port Size = 8 bit */ \
|
||||
| BR_MS_FCM /* MSEL = FCM */ \
|
||||
| BR_V) /* valid */
|
||||
#define CONFIG_SYS_OR6_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
|
||||
|
||||
/* Serial Port - controlled on board with jumper J8
|
||||
* open - index 2
|
||||
* shorted - index 1
|
||||
*/
|
||||
#define CONFIG_SYS_NS16550_SERIAL
|
||||
#define CONFIG_SYS_NS16550_REG_SIZE 1
|
||||
#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
|
||||
#ifdef CONFIG_NAND_SPL
|
||||
#define CONFIG_NS16550_MIN_FUNCTIONS
|
||||
#endif
|
||||
|
||||
#define CONFIG_SYS_BAUDRATE_TABLE \
|
||||
{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
|
||||
|
||||
#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
|
||||
#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
|
||||
|
||||
/*
|
||||
* I2C
|
||||
*/
|
||||
#define CONFIG_SYS_I2C
|
||||
#define CONFIG_SYS_I2C_FSL
|
||||
#define CONFIG_SYS_FSL_I2C_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
|
||||
#define CONFIG_SYS_FSL_I2C2_SPEED 400000
|
||||
#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
|
||||
#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
|
||||
#define CONFIG_SYS_I2C_NOPROBES { {0, 0x29} }
|
||||
|
||||
/*
|
||||
* I2C2 EEPROM
|
||||
*/
|
||||
#define CONFIG_ID_EEPROM
|
||||
#ifdef CONFIG_ID_EEPROM
|
||||
#define CONFIG_SYS_I2C_EEPROM_NXID
|
||||
#endif
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
|
||||
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
|
||||
#define CONFIG_SYS_EEPROM_BUS_NUM 1
|
||||
|
||||
/*
|
||||
* General PCI
|
||||
* Memory space is mapped 1-1, but I/O space must start from 0.
|
||||
*/
|
||||
|
||||
#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCI1_MEM_BUS 0xf0000000
|
||||
#define CONFIG_SYS_PCI1_MEM_PHYS 0xc00000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
|
||||
#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
|
||||
#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000
|
||||
#define CONFIG_SYS_PCI1_IO_BUS 0x00000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCI1_IO_PHYS 0xfffc00000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCI1_IO_PHYS 0xffc00000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64k */
|
||||
|
||||
/* controller 1, Slot 1, tgtid 1, Base address a000 */
|
||||
#define CONFIG_SYS_PCIE1_NAME "Slot 1"
|
||||
#define CONFIG_SYS_PCIE1_MEM_VIRT 0x90000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0xf8000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc10000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE1_MEM_BUS 0x90000000
|
||||
#define CONFIG_SYS_PCIE1_MEM_PHYS 0x90000000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE1_MEM_SIZE 0x08000000 /* 128M */
|
||||
#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc10000
|
||||
#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc10000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc10000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
|
||||
|
||||
/* controller 2, Slot 2, tgtid 2, Base address 9000 */
|
||||
#define CONFIG_SYS_PCIE2_NAME "Slot 2"
|
||||
#define CONFIG_SYS_PCIE2_MEM_VIRT 0x98000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE2_MEM_BUS 0xf8000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc18000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE2_MEM_BUS 0x98000000
|
||||
#define CONFIG_SYS_PCIE2_MEM_PHYS 0x98000000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE2_MEM_SIZE 0x08000000 /* 128M */
|
||||
#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc20000
|
||||
#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc20000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc20000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
|
||||
|
||||
/* controller 3, direct to uli, tgtid 3, Base address 8000 */
|
||||
#define CONFIG_SYS_PCIE3_NAME "Slot 3"
|
||||
#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
|
||||
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000
|
||||
#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
|
||||
#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc30000
|
||||
#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
|
||||
#ifdef CONFIG_PHYS_64BIT
|
||||
#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc30000ull
|
||||
#else
|
||||
#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc30000
|
||||
#endif
|
||||
#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
|
||||
|
||||
#if defined(CONFIG_PCI)
|
||||
/*PCIE video card used*/
|
||||
#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE3_IO_VIRT
|
||||
|
||||
/*PCI video card used*/
|
||||
/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/
|
||||
|
||||
/* video */
|
||||
|
||||
#if defined(CONFIG_VIDEO)
|
||||
#define CONFIG_BIOSEMU
|
||||
#define CONFIG_ATI_RADEON_FB
|
||||
#define CONFIG_VIDEO_LOGO
|
||||
#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE3_IO_VIRT
|
||||
#endif
|
||||
|
||||
#undef CONFIG_EEPRO100
|
||||
#undef CONFIG_TULIP
|
||||
|
||||
#ifndef CONFIG_PCI_PNP
|
||||
#define PCI_ENET0_IOADDR CONFIG_SYS_PCI1_IO_BUS
|
||||
#define PCI_ENET0_MEMADDR CONFIG_SYS_PCI1_IO_BUS
|
||||
#define PCI_IDSEL_NUMBER 0x11 /* IDSEL = AD11 */
|
||||
#endif
|
||||
|
||||
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
|
||||
|
||||
#endif /* CONFIG_PCI */
|
||||
|
||||
/* SATA */
|
||||
#define CONFIG_SYS_SATA_MAX_DEVICE 2
|
||||
#define CONFIG_SATA1
|
||||
#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
|
||||
#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
|
||||
#define CONFIG_SATA2
|
||||
#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
|
||||
#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
|
||||
|
||||
#ifdef CONFIG_FSL_SATA
|
||||
#define CONFIG_LBA48
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
|
||||
#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
|
||||
#define CONFIG_TSEC1 1
|
||||
#define CONFIG_TSEC1_NAME "eTSEC1"
|
||||
#define CONFIG_TSEC3 1
|
||||
#define CONFIG_TSEC3_NAME "eTSEC3"
|
||||
|
||||
#define CONFIG_FSL_SGMII_RISER 1
|
||||
#define SGMII_RISER_PHY_OFFSET 0x1c
|
||||
|
||||
#define TSEC1_PHY_ADDR 1 /* TSEC1 -> PHY1 */
|
||||
#define TSEC3_PHY_ADDR 0 /* TSEC3 -> PHY0 */
|
||||
|
||||
#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
|
||||
|
||||
#define TSEC1_PHYIDX 0
|
||||
#define TSEC3_PHYIDX 0
|
||||
|
||||
#define CONFIG_ETHPRIME "eTSEC1"
|
||||
|
||||
#endif /* CONFIG_TSEC_ENET */
|
||||
|
||||
/*
|
||||
* Environment
|
||||
*/
|
||||
|
||||
#if defined(CONFIG_SYS_RAMBOOT)
|
||||
#if defined(CONFIG_RAMBOOT_SPIFLASH)
|
||||
#elif defined(CONFIG_RAMBOOT_SDCARD)
|
||||
#define CONFIG_FSL_FIXED_MMC_LOCATION
|
||||
#define CONFIG_SYS_MMC_ENV_DEV 0
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
|
||||
#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
|
||||
|
||||
#undef CONFIG_WATCHDOG /* watchdog disabled */
|
||||
|
||||
#ifdef CONFIG_MMC
|
||||
#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
|
||||
#endif
|
||||
|
||||
/*
|
||||
* USB
|
||||
*/
|
||||
#define CONFIG_HAS_FSL_MPH_USB
|
||||
#ifdef CONFIG_HAS_FSL_MPH_USB
|
||||
#ifdef CONFIG_USB_EHCI_HCD
|
||||
#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
|
||||
#define CONFIG_USB_EHCI_FSL
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Miscellaneous configurable options
|
||||
*/
|
||||
#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
|
||||
|
||||
/*
|
||||
* For booting Linux, the board info and command line data
|
||||
* have to be in the first 64 MB of memory, since this is
|
||||
* the maximum mapped by the Linux kernel during initialization.
|
||||
*/
|
||||
#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */
|
||||
#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
|
||||
|
||||
#if defined(CONFIG_CMD_KGDB)
|
||||
#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Environment Configuration
|
||||
*/
|
||||
|
||||
/* The mac addresses for all ethernet interface */
|
||||
#if defined(CONFIG_TSEC_ENET)
|
||||
#define CONFIG_HAS_ETH0
|
||||
#define CONFIG_HAS_ETH1
|
||||
#define CONFIG_HAS_ETH2
|
||||
#define CONFIG_HAS_ETH3
|
||||
#endif
|
||||
|
||||
#define CONFIG_IPADDR 192.168.1.254
|
||||
|
||||
#define CONFIG_HOSTNAME "unknown"
|
||||
#define CONFIG_ROOTPATH "/opt/nfsroot"
|
||||
#define CONFIG_BOOTFILE "uImage"
|
||||
#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
|
||||
|
||||
#define CONFIG_SERVERIP 192.168.1.1
|
||||
#define CONFIG_GATEWAYIP 192.168.1.1
|
||||
#define CONFIG_NETMASK 255.255.255.0
|
||||
|
||||
/* default location for tftp and bootm */
|
||||
#define CONFIG_LOADADDR 1000000
|
||||
|
||||
#define CONFIG_EXTRA_ENV_SETTINGS \
|
||||
"netdev=eth0\0" \
|
||||
"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
|
||||
"tftpflash=tftpboot $loadaddr $uboot; " \
|
||||
"protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" +$filesize; " \
|
||||
"erase " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" +$filesize; " \
|
||||
"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" $filesize; " \
|
||||
"protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" +$filesize; " \
|
||||
"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
|
||||
" $filesize\0" \
|
||||
"consoledev=ttyS0\0" \
|
||||
"ramdiskaddr=2000000\0" \
|
||||
"ramdiskfile=8536ds/ramdisk.uboot\0" \
|
||||
"fdtaddr=1e00000\0" \
|
||||
"fdtfile=8536ds/mpc8536ds.dtb\0" \
|
||||
"bdev=sda3\0" \
|
||||
"hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
|
||||
|
||||
#define CONFIG_HDBOOT \
|
||||
"setenv bootargs root=/dev/$bdev rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_NFSBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/nfs rw " \
|
||||
"nfsroot=$serverip:$rootpath " \
|
||||
"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr - $fdtaddr"
|
||||
|
||||
#define CONFIG_RAMBOOTCOMMAND \
|
||||
"setenv bootargs root=/dev/ram rw " \
|
||||
"console=$consoledev,$baudrate $othbootargs;" \
|
||||
"tftp $ramdiskaddr $ramdiskfile;" \
|
||||
"tftp $loadaddr $bootfile;" \
|
||||
"tftp $fdtaddr $fdtfile;" \
|
||||
"bootm $loadaddr $ramdiskaddr $fdtaddr"
|
||||
|
||||
#define CONFIG_BOOTCOMMAND CONFIG_HDBOOT
|
||||
|
||||
#endif /* __CONFIG_H */
|
||||
Loading…
Reference in New Issue
Block a user