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powerpc: P1012: Drop configuration for P1012

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P1012 is a single-core version of P1021. There is no P1012 target
configured. Drop related macros. P1012 SoC is still supported.

Signed-off-by: York Sun <york.sun@nxp.com>
This commit is contained in:
York Sun 2016-11-16 15:57:52 -08:00
parent 1cdd96f325
commit 83b9bea116
6 changed files with 7 additions and 27 deletions
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1
arch/powerpc/cpu/mpc85xx/Makefile
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@ -74,7 +74,6 @@ obj-$(CONFIG_ARCH_MPC8569) += mpc8569_serdes.o
obj-$(CONFIG_ARCH_MPC8572) += mpc8572_serdes.o
obj-$(CONFIG_ARCH_P1010) += p1010_serdes.o
obj-$(CONFIG_ARCH_P1011) += p1021_serdes.o
obj-$(CONFIG_P1012) += p1021_serdes.o
obj-$(CONFIG_P1013) += p1022_serdes.o
obj-$(CONFIG_P1014) += p1010_serdes.o
obj-$(CONFIG_P1017) += p1023_serdes.o

2
arch/powerpc/cpu/mpc85xx/speed.c
View File

@ -596,7 +596,7 @@ void get_sys_info(sys_info_t *sys_info)
#endif
#ifdef CONFIG_QE
#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
#if defined(CONFIG_P1021) || defined(CONFIG_P1025)
sys_info->freq_qe = sys_info->freq_systembus;
#else
qe_ratio = ((gur->porpllsr) & MPC85xx_PORPLLSR_QE_RATIO)

18
arch/powerpc/include/asm/config_mpc85xx.h
View File

@ -183,24 +183,6 @@
#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
/* P1012 is single core version of P1021 */
#elif defined(CONFIG_P1012)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 12
#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
#define CONFIG_SYS_PPC_E500_DEBUG_TLB 2
#define CONFIG_TSECV2
#define CONFIG_FSL_PCIE_DISABLE_ASPM
#define CONFIG_SYS_FSL_SEC_COMPAT 2
#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
#define CONFIG_SYS_FSL_ERRATUM_ELBC_A001
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define QE_MURAM_SIZE 0x6000UL
#define MAX_QE_RISC 1
#define QE_NUM_OF_SNUM 28
#define CONFIG_SYS_FSL_ERRATUM_A004508
#define CONFIG_SYS_FSL_ERRATUM_A005125
/* P1013 is single core version of P1022 */
#elif defined(CONFIG_P1013)
#define CONFIG_MAX_CPUS 1

2
arch/powerpc/include/asm/immap_85xx.h
View File

@ -2488,7 +2488,7 @@ typedef struct ccsr_gur {
u8 res11a[76];
par_io_t qe_par_io[7];
u8 res11b[1600];
#elif defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
#elif defined(CONFIG_P1021) || defined(CONFIG_P1025)
u8 res11a[12];
u32 iovselsr;
u8 res11b[60];

1
doc/README.mpc85xx-sd-spi-boot
View File

@ -69,7 +69,6 @@ P1011RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
P1010RDB config_ddr3_1gb_p1010rdb_800M.dat
P1014RDB config_ddr3_1gb_p1014rdb_800M.dat
P1021RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
P1012RDB config_ddr3_1gb_p1_p2_rdb_pc_800M.dat
P1022DS config_ddr3_2gb_p1022ds.dat
P1013DS config_ddr3_2gb_p1022ds.dat
P1024RDB config_ddr3_1gb_p1_p2_rdb_pc_667M.dat

10
drivers/qe/uec.c
View File

@ -567,7 +567,7 @@ static void phy_change(struct eth_device *dev)
{
uec_private_t *uec = (uec_private_t *)dev->priv;
#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
#if defined(CONFIG_P1021) || defined(CONFIG_P1025)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
/* QE9 and QE12 need to be set for enabling QE MII managment signals */
@ -578,7 +578,7 @@ static void phy_change(struct eth_device *dev)
/* Update the link, speed, duplex */
uec->mii_info->phyinfo->read_status(uec->mii_info);
#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
#if defined(CONFIG_P1021) || defined(CONFIG_P1025)
/*
* QE12 is muxed with LBCTL, it needs to be released for enabling
* LBCTL signal for LBC usage.
@ -1193,14 +1193,14 @@ static int uec_init(struct eth_device* dev, bd_t *bd)
uec_private_t *uec;
int err, i;
struct phy_info *curphy;
#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
#if defined(CONFIG_P1021) || defined(CONFIG_P1025)
ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
#endif
uec = (uec_private_t *)dev->priv;
if (uec->the_first_run == 0) {
#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
#if defined(CONFIG_P1021) || defined(CONFIG_P1025)
/* QE9 and QE12 need to be set for enabling QE MII managment signals */
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9);
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
@ -1232,7 +1232,7 @@ static int uec_init(struct eth_device* dev, bd_t *bd)
udelay(100000);
} while (1);
#if defined(CONFIG_P1012) || defined(CONFIG_P1021) || defined(CONFIG_P1025)
#if defined(CONFIG_P1021) || defined(CONFIG_P1025)
/* QE12 needs to be released for enabling LBCTL signal*/
clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE12);
#endif