x86: Provide default SMBIOS manufacturer/product

Add a file containing defaults for these, using the existing CONFIG
options. This file must be included with #include since it needs to
be passed through the C preprocessor.

Enable the driver for all x86 boards that generate SMBIOS tables.
Disable it for coral since it has its own driver.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: reword the commit message a little bit]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>

arch/Kconfig

@@ -198,6 +198,8 @@ config X86
 	imply RTC_MC146818
 	imply IRQ
 	imply ACPIGEN if !QEMU
+	imply SYSINFO if GENERATE_SMBIOS_TABLE
+	imply SYSINFO_SMBIOS if GENERATE_SMBIOS_TABLE
 
 	# Thing to enable for when SPL/TPL are enabled: SPL
 	imply SPL_DM

arch/x86/dts/bayleybay.dts

@@ -16,6 +16,8 @@
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 
+#include "smbios.dtsi"
+
 / {
 	model = "Intel Bayley Bay";
 	compatible = "intel,bayleybay", "intel,baytrail";

arch/x86/dts/baytrail_som-db5800-som-6867.dts

@@ -16,6 +16,8 @@
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 
+#include "smbios.dtsi"
+
 / {
 	model = "Advantech SOM-DB5800-SOM-6867";
 	compatible = "advantech,som-db5800-som-6867", "intel,baytrail";

arch/x86/dts/cherryhill.dts

@@ -14,6 +14,8 @@
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 
+#include "smbios.dtsi"
+
 / {
 	model = "Intel Cherry Hill";
 	compatible = "intel,cherryhill", "intel,braswell";

arch/x86/dts/chromebook_link.dts

@@ -11,6 +11,8 @@
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 
+#include "smbios.dtsi"
+
 / {
 	model = "Google Link";
 	compatible = "google,link", "intel,celeron-ivybridge";

arch/x86/dts/chromebook_samus.dts

@@ -9,6 +9,8 @@
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 
+#include "smbios.dtsi"
+
 #ifdef CONFIG_CHROMEOS_VBOOT
 #include "chromeos-x86.dtsi"
 #include "flashmap-x86-ro.dtsi"

arch/x86/dts/chromebox_panther.dts

@@ -6,6 +6,8 @@
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 
+#include "smbios.dtsi"
+
 / {
 	model = "Google Panther";
 	compatible = "google,panther", "intel,haswell";

arch/x86/dts/conga-qeval20-qa3-e3845.dts

@@ -16,6 +16,8 @@
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 
+#include "smbios.dtsi"
+
 / {
 	model = "congatec-QEVAL20-QA3-E3845";
 	compatible = "congatec,qeval20-qa3-e3845", "intel,baytrail";

arch/x86/dts/cougarcanyon2.dts

@@ -14,6 +14,8 @@
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 
+#include "smbios.dtsi"
+
 / {
 	model = "Intel Cougar Canyon 2";
 	compatible = "intel,cougarcanyon2", "intel,chiefriver";

arch/x86/dts/crownbay.dts

@@ -15,6 +15,8 @@
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 
+#include "smbios.dtsi"
+
 / {
 	model = "Intel Crown Bay";
 	compatible = "intel,crownbay", "intel,queensbay";

arch/x86/dts/dfi-bt700.dtsi

@@ -13,6 +13,8 @@
 #include "rtc.dtsi"
 #include "tsc_timer.dtsi"
 
+#include "smbios.dtsi"
+
 / {
 	config {
 		silent_console = <0>;

arch/x86/dts/edison.dts

@@ -12,6 +12,8 @@
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 
+#include "smbios.dtsi"
+
 / {
 	model = "Intel Edison";
 	compatible = "intel,edison";

arch/x86/dts/minnowmax.dts

@@ -15,6 +15,8 @@
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 
+#include "smbios.dtsi"
+
 / {
 	model = "Intel Minnowboard Max";
 	compatible = "intel,minnowmax", "intel,baytrail";

arch/x86/dts/qemu-x86_i440fx.dts

@@ -14,6 +14,8 @@
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 
+#include "smbios.dtsi"
+
 / {
 	model = "QEMU x86 (I440FX)";
 	compatible = "qemu,x86";

arch/x86/dts/qemu-x86_q35.dts

@@ -24,6 +24,8 @@
 /include/ "rtc.dtsi"
 /include/ "tsc_timer.dtsi"
 
+#include "smbios.dtsi"
+
 / {
 	model = "QEMU x86 (Q35)";
 	compatible = "qemu,x86";

arch/x86/dts/smbios.dtsi

@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Default SMBIOS information. Include this in your board .dts file if you want
+ * these defaults.
+ *
+ * Copyright 2020 Google LLC
+ */
+
+#include <config.h>
+
+/ {
+	smbios: smbios {
+		compatible = "u-boot,sysinfo-smbios";
+
+		smbios {
+			system {
+				manufacturer = CONFIG_SYS_VENDOR;
+				product = CONFIG_SYS_BOARD;
+			};
+
+			baseboard {
+				manufacturer = CONFIG_SYS_VENDOR;
+				product = CONFIG_SYS_BOARD;
+			};
+
+			chassis {
+				manufacturer = CONFIG_SYS_VENDOR;
+				/* chassis product is not set by default */
+			};
+		};
+	};
+};

configs/chromebook_coral_defconfig

@@ -99,7 +99,7 @@ CONFIG_SOUND_MAX98357A=y
 CONFIG_SOUND_RT5677=y
 CONFIG_SPI=y
 CONFIG_ICH_SPI=y
-CONFIG_SYSINFO=y
+# CONFIG_SYSINFO_SMBIOS is not set
 CONFIG_TPL_SYSRESET=y
 # CONFIG_TPM_V1 is not set
 CONFIG_TPM2_CR50_I2C=y