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Driver model tidy-up for livetree

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Driver model big rename for consistency
 Python 3 clean-ups for patman
 Update sandbox serial driver to use membuff
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Merge tag 'dm-pull-14dec20' of git://git.denx.de/u-boot-dm into next

Driver model tidy-up for livetree
Driver model big rename for consistency
Python 3 clean-ups for patman
Update sandbox serial driver to use membuff
This commit is contained in:
Tom Rini 2020-12-14 18:57:57 -05:00
commit 8351a29d2d
1201 changed files with 5482 additions and 5374 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/Kconfig
View File

@ -112,6 +112,7 @@ config SANDBOX
imply BITREVERSE
select BLOBLIST
imply CMD_DM
imply CMD_EXCEPTION
imply CMD_GETTIME
imply CMD_HASH
imply CMD_IO

2
arch/arm/include/asm/arch-hi6220/gpio.h
View File

@ -18,7 +18,7 @@ struct gpio_bank {
};
/* Information about a GPIO bank */
struct hikey_gpio_platdata {
struct hikey_gpio_plat {
int bank_index;
ulong base; /* address of registers in physical memory */
};

2
arch/arm/include/asm/arch-imx8/power-domain.h
View File

@ -8,7 +8,7 @@
#include <asm/arch/sci/types.h>
struct imx8_power_domain_platdata {
struct imx8_power_domain_plat {
sc_rsrc_t resource_id;
};

2
arch/arm/include/asm/arch-imx8m/power-domain.h
View File

@ -6,7 +6,7 @@
#ifndef _ASM_ARCH_IMX8M_POWER_DOMAIN_H
#define _ASM_ARCH_IMX8M_POWER_DOMAIN_H
struct imx8m_power_domain_platdata {
struct imx8m_power_domain_plat {
int resource_id;
int has_pd;
struct power_domain pd;

2
arch/arm/include/asm/arch-vf610/gpio.h
View File

@ -20,7 +20,7 @@ struct vybrid_gpio_regs {
u32 gpio_pdir;
};
struct vybrid_gpio_platdata {
struct vybrid_gpio_plat {
unsigned int chip;
u32 base;
const char *port_name;

2
arch/arm/include/asm/omap_gpio.h
View File

@ -25,7 +25,7 @@
#if CONFIG_IS_ENABLED(DM_GPIO)
/* Information about a GPIO bank */
struct omap_gpio_platdata {
struct omap_gpio_plat {
int bank_index;
ulong base; /* address of registers in physical memory */
const char *port_name;

2
arch/arm/include/asm/omap_i2c.h
View File

@ -6,7 +6,7 @@
#ifdef CONFIG_DM_I2C
/* Information about a GPIO bank */
struct omap_i2c_platdata {
struct omap_i2c_plat {
ulong base; /* address of registers in physical memory */
int speed;
int ip_rev;

2
arch/arm/include/asm/omap_musb.h
View File

@ -23,7 +23,7 @@ struct omap_musb_board_data {
enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI};
struct ti_musb_platdata {
struct ti_musb_plat {
void *base;
void *ctrl_mod_base;
struct musb_hdrc_platform_data plat;

2
arch/arm/mach-at91/arm926ejs/at91sam9260_devices.c
View File

@ -213,7 +213,7 @@ void at91_sdram_hw_init(void)
}
/* Platform data for the GPIOs */
static const struct at91_port_platdata at91sam9260_plat[] = {
static const struct at91_port_plat at91sam9260_plat[] = {
{ ATMEL_BASE_PIOA, "PA" },
{ ATMEL_BASE_PIOB, "PB" },
{ ATMEL_BASE_PIOC, "PC" },

2
arch/arm/mach-at91/arm926ejs/at91sam9m10g45_devices.c
View File

@ -167,7 +167,7 @@ void at91_mci_hw_init(void)
#endif
/* Platform data for the GPIOs */
static const struct at91_port_platdata at91sam9260_plat[] = {
static const struct at91_port_plat at91sam9260_plat[] = {
{ ATMEL_BASE_PIOA, "PA" },
{ ATMEL_BASE_PIOB, "PB" },
{ ATMEL_BASE_PIOC, "PC" },

2
arch/arm/mach-at91/include/mach/atmel_serial.h
View File

@ -7,7 +7,7 @@
#define _ATMEL_SERIAL_H
/* Information about a serial port */
struct atmel_serial_platdata {
struct atmel_serial_plat {
uint32_t base_addr;
};

2
arch/arm/mach-at91/include/mach/gpio.h
View File

@ -253,7 +253,7 @@ static inline unsigned at91_gpio_to_pin(unsigned gpio)
}
/* Platform data for each GPIO port */
struct at91_port_platdata {
struct at91_port_plat {
uint32_t base_addr;
const char *bank_name;
};

4
arch/arm/mach-bcm283x/include/mach/gpio.h
View File

@ -52,11 +52,11 @@ struct bcm2835_gpio_regs {
};
/**
* struct bcm2835_gpio_platdata - GPIO platform description
* struct bcm2835_gpio_plat - GPIO platform description
*
* @base: Base address of GPIO controller
*/
struct bcm2835_gpio_platdata {
struct bcm2835_gpio_plat {
unsigned long base;
};

2
arch/arm/mach-imx/mx6/soc.c
View File

@ -46,7 +46,7 @@ static const struct imx_thermal_plat imx6_thermal_plat = {
U_BOOT_DEVICE(imx6_thermal) = {
.name = "imx_thermal",
.platdata = &imx6_thermal_plat,
.plat = &imx6_thermal_plat,
};
#endif

2
arch/arm/mach-imx/mx7/soc.c
View File

@ -62,7 +62,7 @@ static const struct imx_thermal_plat imx7_thermal_plat = {
U_BOOT_DEVICE(imx7_thermal) = {
.name = "imx_thermal",
.platdata = &imx7_thermal_plat,
.plat = &imx7_thermal_plat,
};
#endif

2
arch/arm/mach-ipq40xx/clock-ipq4019.c
View File

@ -83,6 +83,6 @@ U_BOOT_DRIVER(clk_msm) = {
.id = UCLASS_CLK,
.of_match = msm_clk_ids,
.ops = &msm_clk_ops,
.priv_auto_alloc_size = sizeof(struct msm_clk_priv),
.priv_auto = sizeof(struct msm_clk_priv),
.probe = msm_clk_probe,
};

2
arch/arm/mach-ipq40xx/pinctrl-snapdragon.c
View File

@ -131,7 +131,7 @@ U_BOOT_DRIVER(pinctrl_snapdraon) = {
.name = "pinctrl_msm",
.id = UCLASS_PINCTRL,
.of_match = msm_pinctrl_ids,
.priv_auto_alloc_size = sizeof(struct msm_pinctrl_priv),
.priv_auto = sizeof(struct msm_pinctrl_priv),
.ops = &msm_pinctrl_ops,
.probe = msm_pinctrl_probe,
};

4
arch/arm/mach-lpc32xx/devices.c
View File

@ -43,7 +43,7 @@ void lpc32xx_uart_init(unsigned int uart_id)
}
#if !CONFIG_IS_ENABLED(OF_CONTROL)
static const struct ns16550_platdata lpc32xx_uart[] = {
static const struct ns16550_plat lpc32xx_uart[] = {
{ .base = UART3_BASE, .reg_shift = 2,
.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
{ .base = UART4_BASE, .reg_shift = 2,
@ -55,7 +55,7 @@ static const struct ns16550_platdata lpc32xx_uart[] = {
};
#if defined(CONFIG_LPC32XX_HSUART)
static const struct lpc32xx_hsuart_platdata lpc32xx_hsuart[] = {
static const struct lpc32xx_hsuart_plat lpc32xx_hsuart[] = {
{ HS_UART1_BASE, },
{ HS_UART2_BASE, },
{ HS_UART7_BASE, },

4
arch/arm/mach-nexell/include/mach/display.h
View File

@ -212,7 +212,7 @@ struct dp_hdmi_dev {
};
/* platform data for the driver model */
struct nx_display_platdata {
struct nx_display_plat {
int module;
struct dp_sync_info sync;
struct dp_ctrl_info ctrl;
@ -267,7 +267,7 @@ int dp_plane_wait_vsync(int module, int layer, int fps);
#if defined CONFIG_SPL_BUILD || \
(!defined(CONFIG_DM) && !defined(CONFIG_OF_CONTROL))
int nx_display_probe(struct nx_display_platdata *plat);
int nx_display_probe(struct nx_display_plat *plat);
#endif
#endif

12
arch/arm/mach-omap2/am33xx/board.c
View File

@ -80,7 +80,7 @@ int dram_init_banksize(void)
}
#if !CONFIG_IS_ENABLED(OF_CONTROL)
static const struct ns16550_platdata am33xx_serial[] = {
static const struct ns16550_plat am33xx_serial[] = {
{ .base = CONFIG_SYS_NS16550_COM1, .reg_shift = 2,
.clock = CONFIG_SYS_NS16550_CLK, .fcr = UART_FCR_DEFVAL, },
# ifdef CONFIG_SYS_NS16550_COM2
@ -113,7 +113,7 @@ U_BOOT_DEVICES(am33xx_uarts) = {
};
#ifdef CONFIG_DM_I2C
static const struct omap_i2c_platdata am33xx_i2c[] = {
static const struct omap_i2c_plat am33xx_i2c[] = {
{ I2C_BASE1, 100000, OMAP_I2C_REV_V2},
{ I2C_BASE2, 100000, OMAP_I2C_REV_V2},
{ I2C_BASE3, 100000, OMAP_I2C_REV_V2},
@ -127,7 +127,7 @@ U_BOOT_DEVICES(am33xx_i2c) = {
#endif
#if CONFIG_IS_ENABLED(DM_GPIO)
static const struct omap_gpio_platdata am33xx_gpio[] = {
static const struct omap_gpio_plat am33xx_gpio[] = {
{ 0, AM33XX_GPIO0_BASE },
{ 1, AM33XX_GPIO1_BASE },
{ 2, AM33XX_GPIO2_BASE },
@ -157,7 +157,7 @@ static const struct omap3_spi_plat omap3_spi_pdata = {
U_BOOT_DEVICE(am33xx_spi) = {
.name = "omap3_spi",
.platdata = &omap3_spi_pdata,
.plat = &omap3_spi_pdata,
};
#endif
#endif
@ -214,7 +214,7 @@ static struct musb_hdrc_config musb_config = {
};
#if CONFIG_IS_ENABLED(DM_USB) && !CONFIG_IS_ENABLED(OF_CONTROL)
static struct ti_musb_platdata usb0 = {
static struct ti_musb_plat usb0 = {
.base = (void *)USB0_OTG_BASE,
.ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl0,
.plat = {
@ -224,7 +224,7 @@ static struct ti_musb_platdata usb0 = {
},
};
static struct ti_musb_platdata usb1 = {
static struct ti_musb_plat usb1 = {
.base = (void *)USB1_OTG_BASE,
.ctrl_mod_base = &((struct ctrl_dev *)CTRL_DEVICE_BASE)->usb_ctrl1,
.plat = {

2
arch/arm/mach-omap2/omap3/board.c
View File

@ -38,7 +38,7 @@ static void omap3_invalidate_l2_cache_secure(void);
#if CONFIG_IS_ENABLED(DM_GPIO)
#if !CONFIG_IS_ENABLED(OF_CONTROL)
/* Manually initialize GPIO banks when OF_CONTROL doesn't */
static const struct omap_gpio_platdata omap34xx_gpio[] = {
static const struct omap_gpio_plat omap34xx_gpio[] = {
{ 0, OMAP34XX_GPIO1_BASE },
{ 1, OMAP34XX_GPIO2_BASE },
{ 2, OMAP34XX_GPIO3_BASE },

8
arch/arm/mach-rockchip/px30/syscon_px30.c
View File

@ -23,7 +23,7 @@ U_BOOT_DRIVER(syscon_px30) = {
};
#if CONFIG_IS_ENABLED(OF_PLATDATA)
static int px30_syscon_bind_of_platdata(struct udevice *dev)
static int px30_syscon_bind_of_plat(struct udevice *dev)
{
dev->driver_data = dev->driver->of_match->data;
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
@ -35,20 +35,20 @@ U_BOOT_DRIVER(rockchip_px30_pmu) = {
.name = "rockchip_px30_pmu",
.id = UCLASS_SYSCON,
.of_match = px30_syscon_ids,
.bind = px30_syscon_bind_of_platdata,
.bind = px30_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_px30_pmugrf) = {
.name = "rockchip_px30_pmugrf",
.id = UCLASS_SYSCON,
.of_match = px30_syscon_ids + 1,
.bind = px30_syscon_bind_of_platdata,
.bind = px30_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_px30_grf) = {
.name = "rockchip_px30_grf",
.id = UCLASS_SYSCON,
.of_match = px30_syscon_ids + 2,
.bind = px30_syscon_bind_of_platdata,
.bind = px30_syscon_bind_of_plat,
};
#endif

8
arch/arm/mach-rockchip/rk3188/syscon_rk3188.c
View File

@ -24,7 +24,7 @@ U_BOOT_DRIVER(syscon_rk3188) = {
};
#if CONFIG_IS_ENABLED(OF_PLATDATA)
static int rk3188_syscon_bind_of_platdata(struct udevice *dev)
static int rk3188_syscon_bind_of_plat(struct udevice *dev)
{
dev->driver_data = dev->driver->of_match->data;
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
@ -36,20 +36,20 @@ U_BOOT_DRIVER(rockchip_rk3188_noc) = {
.name = "rockchip_rk3188_noc",
.id = UCLASS_SYSCON,
.of_match = rk3188_syscon_ids,
.bind = rk3188_syscon_bind_of_platdata,
.bind = rk3188_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3188_grf) = {
.name = "rockchip_rk3188_grf",
.id = UCLASS_SYSCON,
.of_match = rk3188_syscon_ids + 1,
.bind = rk3188_syscon_bind_of_platdata,
.bind = rk3188_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3188_pmu) = {
.name = "rockchip_rk3188_pmu",
.id = UCLASS_SYSCON,
.of_match = rk3188_syscon_ids + 2,
.bind = rk3188_syscon_bind_of_platdata,
.bind = rk3188_syscon_bind_of_plat,
};
#endif

10
arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
View File

@ -25,7 +25,7 @@ U_BOOT_DRIVER(syscon_rk3288) = {
};
#if CONFIG_IS_ENABLED(OF_PLATDATA)
static int rk3288_syscon_bind_of_platdata(struct udevice *dev)
static int rk3288_syscon_bind_of_plat(struct udevice *dev)
{
dev->driver_data = dev->driver->of_match->data;
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
@ -37,27 +37,27 @@ U_BOOT_DRIVER(rockchip_rk3288_noc) = {
.name = "rockchip_rk3288_noc",
.id = UCLASS_SYSCON,
.of_match = rk3288_syscon_ids,
.bind = rk3288_syscon_bind_of_platdata,
.bind = rk3288_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3288_grf) = {
.name = "rockchip_rk3288_grf",
.id = UCLASS_SYSCON,
.of_match = rk3288_syscon_ids + 1,
.bind = rk3288_syscon_bind_of_platdata,
.bind = rk3288_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3288_sgrf) = {
.name = "rockchip_rk3288_sgrf",
.id = UCLASS_SYSCON,
.of_match = rk3288_syscon_ids + 2,
.bind = rk3288_syscon_bind_of_platdata,
.bind = rk3288_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3288_pmu) = {
.name = "rockchip_rk3288_pmu",
.id = UCLASS_SYSCON,
.of_match = rk3288_syscon_ids + 3,
.bind = rk3288_syscon_bind_of_platdata,
.bind = rk3288_syscon_bind_of_plat,
};
#endif

10
arch/arm/mach-rockchip/rk3368/syscon_rk3368.c
View File

@ -30,7 +30,7 @@ U_BOOT_DRIVER(syscon_rk3368) = {
};
#if CONFIG_IS_ENABLED(OF_PLATDATA)
static int rk3368_syscon_bind_of_platdata(struct udevice *dev)
static int rk3368_syscon_bind_of_plat(struct udevice *dev)
{
dev->driver_data = dev->driver->of_match->data;
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
@ -42,27 +42,27 @@ U_BOOT_DRIVER(rockchip_rk3368_grf) = {
.name = "rockchip_rk3368_grf",
.id = UCLASS_SYSCON,
.of_match = rk3368_syscon_ids,
.bind = rk3368_syscon_bind_of_platdata,
.bind = rk3368_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3368_pmugrf) = {
.name = "rockchip_rk3368_pmugrf",
.id = UCLASS_SYSCON,
.of_match = rk3368_syscon_ids + 1,
.bind = rk3368_syscon_bind_of_platdata,
.bind = rk3368_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3368_msch) = {
.name = "rockchip_rk3368_msch",
.id = UCLASS_SYSCON,
.of_match = rk3368_syscon_ids + 2,
.bind = rk3368_syscon_bind_of_platdata,
.bind = rk3368_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3368_sgrf) = {
.name = "rockchip_rk3368_sgrf",
.id = UCLASS_SYSCON,
.of_match = rk3368_syscon_ids + 3,
.bind = rk3368_syscon_bind_of_platdata,
.bind = rk3368_syscon_bind_of_plat,
};
#endif

12
arch/arm/mach-rockchip/rk3399/syscon_rk3399.c
View File

@ -28,7 +28,7 @@ U_BOOT_DRIVER(syscon_rk3399) = {
};
#if CONFIG_IS_ENABLED(OF_PLATDATA)
static int rk3399_syscon_bind_of_platdata(struct udevice *dev)
static int rk3399_syscon_bind_of_plat(struct udevice *dev)
{
dev->driver_data = dev->driver->of_match->data;
debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
@ -40,34 +40,34 @@ U_BOOT_DRIVER(rockchip_rk3399_grf) = {
.name = "rockchip_rk3399_grf",
.id = UCLASS_SYSCON,
.of_match = rk3399_syscon_ids,
.bind = rk3399_syscon_bind_of_platdata,
.bind = rk3399_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3399_pmugrf) = {
.name = "rockchip_rk3399_pmugrf",
.id = UCLASS_SYSCON,
.of_match = rk3399_syscon_ids + 1,
.bind = rk3399_syscon_bind_of_platdata,
.bind = rk3399_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3399_pmusgrf) = {
.name = "rockchip_rk3399_pmusgrf",
.id = UCLASS_SYSCON,
.of_match = rk3399_syscon_ids + 2,
.bind = rk3399_syscon_bind_of_platdata,
.bind = rk3399_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3399_cic) = {
.name = "rockchip_rk3399_cic",
.id = UCLASS_SYSCON,
.of_match = rk3399_syscon_ids + 3,
.bind = rk3399_syscon_bind_of_platdata,
.bind = rk3399_syscon_bind_of_plat,
};
U_BOOT_DRIVER(rockchip_rk3399_pmu) = {
.name = "rockchip_rk3399_pmu",
.id = UCLASS_SYSCON,
.of_match = rk3399_syscon_ids + 4,
.bind = rk3399_syscon_bind_of_platdata,
.bind = rk3399_syscon_bind_of_plat,
};
#endif

4
arch/arm/mach-rockchip/spl-boot-order.c
View File

@ -46,7 +46,7 @@ static int spl_node_to_boot_device(int node)
dev;
device_find_next_child(&dev)) {
if (device_get_uclass_id(dev) == UCLASS_BLK) {
desc = dev_get_uclass_platdata(dev);
desc = dev_get_uclass_plat(dev);
break;
}
}
@ -99,7 +99,7 @@ __weak const char *board_spl_was_booted_from(void)
void board_boot_order(u32 *spl_boot_list)
{
/* In case of no fdt (or only platdata), use spl_boot_device() */
/* In case of no fdt (or only plat), use spl_boot_device() */
if (!CONFIG_IS_ENABLED(OF_CONTROL) || CONFIG_IS_ENABLED(OF_PLATDATA)) {
spl_boot_list[0] = spl_boot_device();
return;

2
arch/arm/mach-snapdragon/clock-snapdragon.c
View File

@ -143,6 +143,6 @@ U_BOOT_DRIVER(clk_msm) = {
.id = UCLASS_CLK,
.of_match = msm_clk_ids,
.ops = &msm_clk_ops,
.priv_auto_alloc_size = sizeof(struct msm_clk_priv),
.priv_auto = sizeof(struct msm_clk_priv),
.probe = msm_clk_probe,
};

2
arch/arm/mach-snapdragon/pinctrl-snapdragon.c
View File

@ -123,7 +123,7 @@ U_BOOT_DRIVER(pinctrl_snapdraon) = {
.name = "pinctrl_msm",
.id = UCLASS_PINCTRL,
.of_match = msm_pinctrl_ids,
.priv_auto_alloc_size = sizeof(struct msm_pinctrl_priv),
.priv_auto = sizeof(struct msm_pinctrl_priv),
.ops = &msm_pinctrl_ops,
.probe = msm_pinctrl_probe,
};

36
arch/arm/mach-stm32mp/bsec.c
View File

@ -280,13 +280,13 @@ static int bsec_program_otp(long base, u32 val, u32 otp)
}
/* BSEC MISC driver *******************************************************/
struct stm32mp_bsec_platdata {
struct stm32mp_bsec_plat {
u32 base;
};
static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp)
{
struct stm32mp_bsec_platdata *plat;
struct stm32mp_bsec_plat *plat;
u32 tmp_data = 0;
int ret;
@ -295,7 +295,7 @@ static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp)
STM32_SMC_READ_OTP,
otp, 0, val);
plat = dev_get_platdata(dev);
plat = dev_get_plat(dev);
/* read current shadow value */
ret = bsec_read_shadow(plat->base, &tmp_data, otp);
@ -319,21 +319,21 @@ static int stm32mp_bsec_read_otp(struct udevice *dev, u32 *val, u32 otp)
static int stm32mp_bsec_read_shadow(struct udevice *dev, u32 *val, u32 otp)
{
struct stm32mp_bsec_platdata *plat;
struct stm32mp_bsec_plat *plat;
if (IS_ENABLED(CONFIG_TFABOOT))
return stm32_smc(STM32_SMC_BSEC,
STM32_SMC_READ_SHADOW,
otp, 0, val);
plat = dev_get_platdata(dev);
plat = dev_get_plat(dev);
return bsec_read_shadow(plat->base, val, otp);
}
static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp)
{
struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev);
struct stm32mp_bsec_plat *plat = dev_get_plat(dev);
/* return OTP permanent write lock status */
*val = bsec_read_lock(plat->base + BSEC_WRLOCK_OFF, otp);
@ -343,14 +343,14 @@ static int stm32mp_bsec_read_lock(struct udevice *dev, u32 *val, u32 otp)
static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp)
{
struct stm32mp_bsec_platdata *plat;
struct stm32mp_bsec_plat *plat;
if (IS_ENABLED(CONFIG_TFABOOT))
return stm32_smc_exec(STM32_SMC_BSEC,
STM32_SMC_PROG_OTP,
otp, val);
plat = dev_get_platdata(dev);
plat = dev_get_plat(dev);
return bsec_program_otp(plat->base, val, otp);
@ -358,14 +358,14 @@ static int stm32mp_bsec_write_otp(struct udevice *dev, u32 val, u32 otp)
static int stm32mp_bsec_write_shadow(struct udevice *dev, u32 val, u32 otp)
{
struct stm32mp_bsec_platdata *plat;
struct stm32mp_bsec_plat *plat;
if (IS_ENABLED(CONFIG_TFABOOT))
return stm32_smc_exec(STM32_SMC_BSEC,
STM32_SMC_WRITE_SHADOW,
otp, val);
plat = dev_get_platdata(dev);
plat = dev_get_plat(dev);
return bsec_write_shadow(plat->base, val, otp);
}
@ -473,9 +473,9 @@ static const struct misc_ops stm32mp_bsec_ops = {
.write = stm32mp_bsec_write,
};
static int stm32mp_bsec_ofdata_to_platdata(struct udevice *dev)
static int stm32mp_bsec_of_to_plat(struct udevice *dev)
{
struct stm32mp_bsec_platdata *plat = dev_get_platdata(dev);
struct stm32mp_bsec_plat *plat = dev_get_plat(dev);
plat->base = (u32)dev_read_addr_ptr(dev);
@ -485,7 +485,7 @@ static int stm32mp_bsec_ofdata_to_platdata(struct udevice *dev)
static int stm32mp_bsec_probe(struct udevice *dev)
{
int otp;
struct stm32mp_bsec_platdata *plat;
struct stm32mp_bsec_plat *plat;
/*
* update unlocked shadow for OTP cleared by the rom code
@ -493,7 +493,7 @@ static int stm32mp_bsec_probe(struct udevice *dev)
*/
if (!IS_ENABLED(CONFIG_TFABOOT) && !IS_ENABLED(CONFIG_SPL_BUILD)) {
plat = dev_get_platdata(dev);
plat = dev_get_plat(dev);
for (otp = 57; otp <= BSEC_OTP_MAX_VALUE; otp++)
if (!bsec_read_SR_lock(plat->base, otp))
@ -512,8 +512,8 @@ U_BOOT_DRIVER(stm32mp_bsec) = {
.name = "stm32mp_bsec",
.id = UCLASS_MISC,
.of_match = stm32mp_bsec_ids,
.ofdata_to_platdata = stm32mp_bsec_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct stm32mp_bsec_platdata),
.of_to_plat = stm32mp_bsec_of_to_plat,
.plat_auto = sizeof(struct stm32mp_bsec_plat),
.ops = &stm32mp_bsec_ops,
.probe = stm32mp_bsec_probe,
};
@ -521,7 +521,7 @@ U_BOOT_DRIVER(stm32mp_bsec) = {
bool bsec_dbgswenable(void)
{
struct udevice *dev;
struct stm32mp_bsec_platdata *plat;
struct stm32mp_bsec_plat *plat;
int ret;
ret = uclass_get_device_by_driver(UCLASS_MISC,
@ -531,7 +531,7 @@ bool bsec_dbgswenable(void)
return false;
}
plat = dev_get_platdata(dev);
plat = dev_get_plat(dev);
if (readl(plat->base + BSEC_DENABLE_OFF) & BSEC_DENABLE_DBGSWENABLE)
return true;

18
arch/arm/mach-stm32mp/pwr_regulator.c
View File

@ -59,7 +59,7 @@ static int stm32mp_pwr_read(struct udevice *dev, uint reg, uint8_t *buff,
return 0;
}
static int stm32mp_pwr_ofdata_to_platdata(struct udevice *dev)
static int stm32mp_pwr_of_to_plat(struct udevice *dev)
{
struct stm32mp_pwr_priv *priv = dev_get_priv(dev);
@ -103,8 +103,8 @@ U_BOOT_DRIVER(stm32mp_pwr_pmic) = {
.of_match = stm32mp_pwr_ids,
.bind = stm32mp_pwr_bind,
.ops = &stm32mp_pwr_ops,
.ofdata_to_platdata = stm32mp_pwr_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct stm32mp_pwr_priv),
.of_to_plat = stm32mp_pwr_of_to_plat,
.priv_auto = sizeof(struct stm32mp_pwr_priv),
};
static const struct stm32mp_pwr_reg_info stm32mp_pwr_reg11 = {
@ -135,9 +135,9 @@ static const struct stm32mp_pwr_reg_info *stm32mp_pwr_reg_infos[] = {
static int stm32mp_pwr_regulator_probe(struct udevice *dev)
{
const struct stm32mp_pwr_reg_info **p = stm32mp_pwr_reg_infos;
struct dm_regulator_uclass_platdata *uc_pdata;
struct dm_regulator_uclass_plat *uc_pdata;
uc_pdata = dev_get_uclass_platdata(dev);
uc_pdata = dev_get_uclass_plat(dev);
while (*p) {
int rc;
@ -172,9 +172,9 @@ static int stm32mp_pwr_regulator_probe(struct udevice *dev)
static int stm32mp_pwr_regulator_set_value(struct udevice *dev, int uV)
{
struct dm_regulator_uclass_platdata *uc_pdata;
struct dm_regulator_uclass_plat *uc_pdata;
uc_pdata = dev_get_uclass_platdata(dev);
uc_pdata = dev_get_uclass_plat(dev);
if (!uc_pdata)
return -ENXIO;
@ -188,9 +188,9 @@ static int stm32mp_pwr_regulator_set_value(struct udevice *dev, int uV)
static int stm32mp_pwr_regulator_get_value(struct udevice *dev)
{
struct dm_regulator_uclass_platdata *uc_pdata;
struct dm_regulator_uclass_plat *uc_pdata;
uc_pdata = dev_get_uclass_platdata(dev);
uc_pdata = dev_get_uclass_plat(dev);
if (!uc_pdata)
return -ENXIO;

2
arch/arm/mach-tegra/board.c
View File

@ -257,7 +257,7 @@ void board_init_uart_f(void)
}
#if !CONFIG_IS_ENABLED(OF_CONTROL)
static struct ns16550_platdata ns16550_com1_pdata = {
static struct ns16550_plat ns16550_com1_pdata = {
.base = CONFIG_SYS_NS16550_COM1,
.reg_shift = 2,
.clock = CONFIG_SYS_NS16550_CLK,

2
arch/riscv/include/asm/arch-fu540/gpio.h
View File

@ -28,7 +28,7 @@ enum gpio_state {
};
/* Details about a GPIO bank */
struct sifive_gpio_platdata {
struct sifive_gpio_plat {
void *base; /* address of registers in physical memory */
};

2
arch/riscv/include/asm/arch-generic/gpio.h
View File

@ -28,7 +28,7 @@ enum gpio_state {
};
/* Details about a GPIO bank */
struct sifive_gpio_platdata {
struct sifive_gpio_plat {
void *base; /* address of registers in physical memory */
};

9
arch/sandbox/Kconfig
View File

@ -51,6 +51,15 @@ config HOST_64BIT
endchoice
config SANDBOX_CRASH_RESET
bool "Reset on crash"
help
If an illegal instruction or an illegal memory access occurs, the
sandbox by default writes a crash dump and exits. If you set this
flag, the sandbox is reset instead. This may be useful when running
test suites like the UEFI self certification test which continue
with the next test after a crash.
config SANDBOX_BITS_PER_LONG
int
default 32 if HOST_32BIT

40
arch/sandbox/cpu/os.c
View File

@ -3,6 +3,8 @@
* Copyright (c) 2011 The Chromium OS Authors.
*/
#define _GNU_SOURCE
#include <dirent.h>
#include <errno.h>
#include <fcntl.h>
@ -15,11 +17,13 @@
#include <string.h>
#include <termios.h>
#include <time.h>
#include <ucontext.h>
#include <unistd.h>
#include <sys/mman.h>
#include <sys/stat.h>
#include <sys/time.h>
#include <sys/types.h>
#include <linux/compiler_attributes.h>
#include <linux/types.h>
#include <asm/getopt.h>
@ -191,6 +195,42 @@ static void os_sigint_handler(int sig)
raise(SIGINT);
}
static void os_signal_handler(int sig, siginfo_t *info, void *con)
{
ucontext_t __maybe_unused *context = con;
unsigned long pc;
#if defined(__x86_64__)
pc = context->uc_mcontext.gregs[REG_RIP];
#elif defined(__aarch64__)
pc = context->uc_mcontext.pc;
#elif defined(__riscv)
pc = context->uc_mcontext.__gregs[REG_PC];
#else
const char msg[] =
"\nUnsupported architecture, cannot read program counter\n";
os_write(1, msg, sizeof(msg));
pc = 0;
#endif
os_signal_action(sig, pc);
}
int os_setup_signal_handlers(void)
{
struct sigaction act;
act.sa_sigaction = os_signal_handler;
sigemptyset(&act.sa_mask);
act.sa_flags = SA_SIGINFO | SA_NODEFER;
if (sigaction(SIGILL, &act, NULL) ||
sigaction(SIGBUS, &act, NULL) ||
sigaction(SIGSEGV, &act, NULL))
return -1;
return 0;
}
/* Put tty into raw mode so <tab> and <ctrl+c> work */
void os_tty_raw(int fd, bool allow_sigs)
{

4
arch/sandbox/cpu/start.c
View File

@ -451,6 +451,10 @@ int main(int argc, char *argv[])
if (ret)
goto err;
ret = os_setup_signal_handlers();
if (ret)
goto err;
#if CONFIG_VAL(SYS_MALLOC_F_LEN)
gd->malloc_base = CONFIG_MALLOC_F_ADDR;
#endif

35
arch/sandbox/lib/interrupts.c
View File

@ -6,7 +6,13 @@
*/
#include <common.h>
#include <efi_loader.h>
#include <irq_func.h>
#include <os.h>
#include <asm-generic/signal.h>
#include <asm/u-boot-sandbox.h>
DECLARE_GLOBAL_DATA_PTR;
int interrupt_init(void)
{
@ -21,3 +27,32 @@ int disable_interrupts(void)
{
return 0;
}
void os_signal_action(int sig, unsigned long pc)
{
efi_restore_gd();
switch (sig) {
case SIGILL:
printf("\nIllegal instruction\n");
break;
case SIGBUS:
printf("\nBus error\n");
break;
case SIGSEGV:
printf("\nSegmentation violation\n");
break;
default:
break;
}
printf("pc = 0x%lx, ", pc);
printf("pc_reloc = 0x%lx\n\n", pc - gd->reloc_off);
efi_print_image_infos((void *)pc);
if (IS_ENABLED(CONFIG_SANDBOX_CRASH_RESET)) {
printf("resetting ...\n\n");
sandbox_reset();
} else {
sandbox_exit();
}
}

6
arch/x86/cpu/acpi_gpe.c
View File

@ -51,7 +51,7 @@ static int acpi_gpe_read_and_clear(struct irq *irq)
return ret;
}
static int acpi_gpe_ofdata_to_platdata(struct udevice *dev)
static int acpi_gpe_of_to_plat(struct udevice *dev)
{
struct acpi_gpe_priv *priv = dev_get_priv(dev);
@ -107,6 +107,6 @@ U_BOOT_DRIVER(acpi_gpe_drv) = {
.id = UCLASS_IRQ,
.of_match = acpi_gpe_ids,
.ops = &acpi_gpe_ops,
.ofdata_to_platdata = acpi_gpe_ofdata_to_platdata,
.priv_auto_alloc_size = sizeof(struct acpi_gpe_priv),
.of_to_plat = acpi_gpe_of_to_plat,
.priv_auto = sizeof(struct acpi_gpe_priv),
};

16
arch/x86/cpu/apollolake/hostbridge.c
View File

@ -42,7 +42,7 @@ enum {
};
/**
* struct apl_hostbridge_platdata - platform data for hostbridge
* struct apl_hostbridge_plat - platform data for hostbridge
*
* @dtplat: Platform data for of-platdata
* @early_pads: Early pad data to set up, each (pad, cfg0, cfg1)
@ -50,7 +50,7 @@ enum {
* @pciex_region_size: BAR length in bytes
* @bdf: Bus/device/function of hostbridge
*/
struct apl_hostbridge_platdata {
struct apl_hostbridge_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_intel_apl_hostbridge dtplat;
#endif
@ -158,7 +158,7 @@ static const struct nhlt_endp_descriptor dmic_4ch_descriptors[] = {
static int apl_hostbridge_early_init_pinctrl(struct udevice *dev)
{
struct apl_hostbridge_platdata *plat = dev_get_platdata(dev);
struct apl_hostbridge_plat *plat = dev_get_plat(dev);
struct udevice *pinctrl;
int ret;
@ -172,7 +172,7 @@ static int apl_hostbridge_early_init_pinctrl(struct udevice *dev)
static int apl_hostbridge_early_init(struct udevice *dev)
{
struct apl_hostbridge_platdata *plat = dev_get_platdata(dev);
struct apl_hostbridge_plat *plat = dev_get_plat(dev);
u32 region_size;
ulong base;
u32 reg;
@ -221,9 +221,9 @@ static int apl_hostbridge_early_init(struct udevice *dev)
return 0;
}
static int apl_hostbridge_ofdata_to_platdata(struct udevice *dev)
static int apl_hostbridge_of_to_plat(struct udevice *dev)
{
struct apl_hostbridge_platdata *plat = dev_get_platdata(dev);
struct apl_hostbridge_plat *plat = dev_get_plat(dev);
struct udevice *pinctrl;
int ret;
@ -400,10 +400,10 @@ U_BOOT_DRIVER(intel_apl_hostbridge) = {
.name = "intel_apl_hostbridge",
.id = UCLASS_NORTHBRIDGE,
.of_match = apl_hostbridge_ids,
.ofdata_to_platdata = apl_hostbridge_ofdata_to_platdata,
.of_to_plat = apl_hostbridge_of_to_plat,
.probe = apl_hostbridge_probe,
.remove = apl_hostbridge_remove,
.platdata_auto_alloc_size = sizeof(struct apl_hostbridge_platdata),
.plat_auto = sizeof(struct apl_hostbridge_plat),
ACPI_OPS_PTR(&apl_hostbridge_acpi_ops)
.flags = DM_FLAG_OS_PREPARE,
};

14
arch/x86/cpu/apollolake/pmc.c
View File

@ -53,7 +53,7 @@ enum {
CF9_GLB_RST = 1 << 20,
};
struct apl_pmc_platdata {
struct apl_pmc_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_intel_apl_pmc dtplat;
#endif
@ -108,10 +108,10 @@ static int apl_global_reset_set_enable(struct udevice *dev, bool enable)
return 0;
}
int apl_pmc_ofdata_to_uc_platdata(struct udevice *dev)
int apl_pmc_ofdata_to_uc_plat(struct udevice *dev)
{
struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
struct apl_pmc_platdata *plat = dev_get_platdata(dev);
struct apl_pmc_plat *plat = dev_get_plat(dev);
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
u32 base[6];
@ -144,7 +144,7 @@ int apl_pmc_ofdata_to_uc_platdata(struct udevice *dev)
if (ret)
return log_msg_ret("Bad gpe0-dw", ret);
return pmc_ofdata_to_uc_platdata(dev);
return pmc_ofdata_to_uc_plat(dev);
#else
struct dtd_intel_apl_pmc *dtplat = &plat->dtplat;
@ -169,7 +169,7 @@ int apl_pmc_ofdata_to_uc_platdata(struct udevice *dev)
static int enable_pmcbar(struct udevice *dev)
{
struct acpi_pmc_upriv *upriv = dev_get_uclass_priv(dev);
struct apl_pmc_platdata *priv = dev_get_platdata(dev);
struct apl_pmc_plat *priv = dev_get_plat(dev);
pci_dev_t pmc = priv->bdf;
/*
@ -221,8 +221,8 @@ U_BOOT_DRIVER(intel_apl_pmc) = {
.name = "intel_apl_pmc",
.id = UCLASS_ACPI_PMC,
.of_match = apl_pmc_ids,
.ofdata_to_platdata = apl_pmc_ofdata_to_uc_platdata,
.of_to_plat = apl_pmc_ofdata_to_uc_plat,
.probe = apl_pmc_probe,
.ops = &apl_pmc_ops,
.platdata_auto_alloc_size = sizeof(struct apl_pmc_platdata),
.plat_auto = sizeof(struct apl_pmc_plat),
};

8
arch/x86/cpu/apollolake/spl.c
View File

@ -85,14 +85,14 @@ static int apl_flash_probe(struct udevice *dev)
/*
* Manually set the parent of the SPI flash to SPI, since dtoc doesn't. We also
* need to allocate the parent_platdata since by the time this function is
* need to allocate the parent_plat since by the time this function is
* called device_bind() has already gone past that step.
*/
static int apl_flash_bind(struct udevice *dev)
{
if (CONFIG_IS_ENABLED(OF_PLATDATA) &&
!CONFIG_IS_ENABLED(OF_PLATDATA_PARENT)) {
struct dm_spi_slave_platdata *plat;
struct dm_spi_slave_plat *plat;
struct udevice *spi;
int ret;
@ -104,7 +104,7 @@ static int apl_flash_bind(struct udevice *dev)
plat = calloc(sizeof(*plat), 1);
if (!plat)
return -ENOMEM;
dev->parent_platdata = plat;
dev->parent_plat = plat;
}
return 0;
@ -125,7 +125,7 @@ U_BOOT_DRIVER(winbond_w25q128fw) = {
.of_match = apl_flash_ids,
.bind = apl_flash_bind,
.probe = apl_flash_probe,
.priv_auto_alloc_size = sizeof(struct spi_flash),
.priv_auto = sizeof(struct spi_flash),
.ops = &apl_flash_ops,
};

24
arch/x86/cpu/apollolake/uart.c
View File

@ -68,16 +68,16 @@ void apl_uart_init(pci_dev_t bdf, ulong base)
* This driver uses its own compatible string but almost everything else from
* the standard ns16550 driver. This allows us to provide an of-platdata
* implementation, since the platdata produced by of-platdata does not match
* struct ns16550_platdata.
* struct ns16550_plat.
*
* When running with of-platdata (generally TPL), the platdata is converted to
* something that ns16550 expects. When running withoutof-platdata (SPL, U-Boot
* proper), we use ns16550's ofdata_to_platdata routine.
* proper), we use ns16550's of_to_plat routine.
*/
static int apl_ns16550_probe(struct udevice *dev)
{
struct ns16550_platdata *plat = dev_get_platdata(dev);
struct ns16550_plat *plat = dev_get_plat(dev);
if (!CONFIG_IS_ENABLED(PCI))
apl_uart_init(plat->bdf, plat->base);
@ -85,14 +85,14 @@ static int apl_ns16550_probe(struct udevice *dev)
return ns16550_serial_probe(dev);
}
static int apl_ns16550_ofdata_to_platdata(struct udevice *dev)
static int apl_ns16550_of_to_plat(struct udevice *dev)
{
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_intel_apl_ns16550 *dtplat = dev_get_platdata(dev);
struct ns16550_platdata *plat;
struct dtd_intel_apl_ns16550 *dtplat = dev_get_plat(dev);
struct ns16550_plat *plat;
/*
* Convert our platdata to the ns16550's platdata, so we can just use
* Convert our plat to the ns16550's plat, so we can just use
* that driver
*/
plat = malloc(sizeof(*plat));
@ -105,11 +105,11 @@ static int apl_ns16550_ofdata_to_platdata(struct udevice *dev)
plat->clock = dtplat->clock_frequency;
plat->fcr = UART_FCR_DEFVAL;
plat->bdf = pci_ofplat_get_devfn(dtplat->reg[0]);
dev->platdata = plat;
dev->plat = plat;
#else
int ret;
ret = ns16550_serial_ofdata_to_platdata(dev);
ret = ns16550_serial_of_to_plat(dev);
if (ret)
return ret;
#endif /* OF_PLATDATA */
@ -126,9 +126,9 @@ U_BOOT_DRIVER(intel_apl_ns16550) = {
.name = "intel_apl_ns16550",
.id = UCLASS_SERIAL,
.of_match = apl_ns16550_serial_ids,
.platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
.priv_auto_alloc_size = sizeof(struct NS16550),
.plat_auto = sizeof(struct ns16550_plat),
.priv_auto = sizeof(struct NS16550),
.ops = &ns16550_serial_ops,
.ofdata_to_platdata = apl_ns16550_ofdata_to_platdata,
.of_to_plat = apl_ns16550_of_to_plat,
.probe = apl_ns16550_probe,
};

4
arch/x86/cpu/broadwell/adsp.c
View File

@ -122,7 +122,7 @@ static int broadwell_adsp_probe(struct udevice *dev)
return 0;
}
static int broadwell_adsp_ofdata_to_platdata(struct udevice *dev)
static int broadwell_adsp_of_to_plat(struct udevice *dev)
{
struct broadwell_adsp_priv *priv = dev_get_priv(dev);
@ -142,7 +142,7 @@ static const struct udevice_id broadwell_adsp_ids[] = {
U_BOOT_DRIVER(broadwell_adsp_drv) = {
.name = "adsp",
.id = UCLASS_SYSCON,
.ofdata_to_platdata = broadwell_adsp_ofdata_to_platdata,
.of_to_plat = broadwell_adsp_of_to_plat,
.of_match = broadwell_adsp_ids,
.bind = dm_scan_fdt_dev,
.probe = broadwell_adsp_probe,

2
arch/x86/cpu/broadwell/cpu_full.c
View File

@ -665,6 +665,6 @@ U_BOOT_DRIVER(cpu_x86_broadwell_drv) = {
.bind = cpu_x86_bind,
.probe = cpu_x86_broadwell_probe,
.ops = &cpu_x86_broadwell_ops,
.priv_auto_alloc_size = sizeof(struct cpu_broadwell_priv),
.priv_auto = sizeof(struct cpu_broadwell_priv),
.flags = DM_FLAG_PRE_RELOC,
};

14
arch/x86/cpu/broadwell/sata.c
View File

@ -17,7 +17,7 @@
#include <asm/arch/pch.h>
#include <linux/delay.h>
struct sata_platdata {
struct sata_plat {
int port_map;
uint port0_gen3_tx;
uint port1_gen3_tx;
@ -41,7 +41,7 @@ struct sata_platdata {
static void broadwell_sata_init(struct udevice *dev)
{
struct sata_platdata *plat = dev_get_platdata(dev);
struct sata_plat *plat = dev_get_plat(dev);
u32 reg32;
u8 *abar;
u16 reg16;
@ -211,7 +211,7 @@ static void broadwell_sata_init(struct udevice *dev)
static int broadwell_sata_enable(struct udevice *dev)
{
struct sata_platdata *plat = dev_get_platdata(dev);
struct sata_plat *plat = dev_get_plat(dev);
struct gpio_desc desc;
u16 map;
int ret;
@ -232,9 +232,9 @@ static int broadwell_sata_enable(struct udevice *dev)
return 0;
}
static int broadwell_sata_ofdata_to_platdata(struct udevice *dev)
static int broadwell_sata_of_to_plat(struct udevice *dev)
{
struct sata_platdata *plat = dev_get_platdata(dev);
struct sata_plat *plat = dev_get_plat(dev);
const void *blob = gd->fdt_blob;
int node = dev_of_offset(dev);
@ -264,7 +264,7 @@ U_BOOT_DRIVER(ahci_broadwell_drv) = {
.name = "ahci_broadwell",
.id = UCLASS_AHCI,
.of_match = broadwell_ahci_ids,
.ofdata_to_platdata = broadwell_sata_ofdata_to_platdata,
.of_to_plat = broadwell_sata_of_to_plat,
.probe = broadwell_sata_probe,
.platdata_auto_alloc_size = sizeof(struct sata_platdata),
.plat_auto = sizeof(struct sata_plat),
};

2
arch/x86/cpu/cpu_x86.c
View File

@ -13,7 +13,7 @@ DECLARE_GLOBAL_DATA_PTR;
int cpu_x86_bind(struct udevice *dev)
{
struct cpu_platdata *plat = dev_get_parent_platdata(dev);
struct cpu_plat *plat = dev_get_parent_plat(dev);
struct cpuid_result res;
plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev),

12
arch/x86/cpu/intel_common/itss.c
View File

@ -19,7 +19,7 @@
#include <spl.h>
#include <asm/itss.h>
struct itss_platdata {
struct itss_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
/* Put this first since driver model will copy the data here */
struct dtd_intel_itss dtplat;
@ -178,13 +178,13 @@ static int itss_bind(struct udevice *dev)
return 0;
}
static int itss_ofdata_to_platdata(struct udevice *dev)
static int itss_of_to_plat(struct udevice *dev)
{
struct itss_priv *priv = dev_get_priv(dev);
int ret;
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct itss_platdata *plat = dev_get_platdata(dev);
struct itss_plat *plat = dev_get_plat(dev);
struct dtd_intel_itss *dtplat = &plat->dtplat;
/*
@ -241,7 +241,7 @@ U_BOOT_DRIVER(intel_itss) = {
.of_match = itss_ids,
.ops = &itss_ops,
.bind = itss_bind,
.ofdata_to_platdata = itss_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct itss_platdata),
.priv_auto_alloc_size = sizeof(struct itss_priv),
.of_to_plat = itss_of_to_plat,
.plat_auto = sizeof(struct itss_plat),
.priv_auto = sizeof(struct itss_priv),
};

17
arch/x86/cpu/intel_common/p2sb.c
View File

@ -19,7 +19,7 @@
#define PCH_P2SB_E0 0xe0
#define HIDE_BIT BIT(0)
struct p2sb_platdata {
struct p2sb_plat {
#if CONFIG_IS_ENABLED(OF_PLATDATA)
struct dtd_intel_p2sb dtplat;
#endif
@ -57,7 +57,7 @@ struct p2sb_platdata {
*/
static int p2sb_early_init(struct udevice *dev)
{
struct p2sb_platdata *plat = dev_get_platdata(dev);
struct p2sb_plat *plat = dev_get_plat(dev);
pci_dev_t pdev = plat->bdf;
/*
@ -90,10 +90,10 @@ static int p2sb_spl_init(struct udevice *dev)
return 0;
}
int p2sb_ofdata_to_platdata(struct udevice *dev)
int p2sb_of_to_plat(struct udevice *dev)
{
struct p2sb_uc_priv *upriv = dev_get_uclass_priv(dev);
struct p2sb_platdata *plat = dev_get_platdata(dev);
struct p2sb_plat *plat = dev_get_plat(dev);
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
int ret;
@ -167,7 +167,7 @@ static int p2sb_remove(struct udevice *dev)
static int p2sb_child_post_bind(struct udevice *dev)
{
#if !CONFIG_IS_ENABLED(OF_PLATDATA)
struct p2sb_child_platdata *pplat = dev_get_parent_platdata(dev);
struct p2sb_child_plat *pplat = dev_get_parent_plat(dev);
int ret;
u32 pid;
@ -196,10 +196,9 @@ U_BOOT_DRIVER(intel_p2sb) = {
.probe = p2sb_probe,
.remove = p2sb_remove,
.ops = &p2sb_ops,
.ofdata_to_platdata = p2sb_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct p2sb_platdata),
.per_child_platdata_auto_alloc_size =
sizeof(struct p2sb_child_platdata),
.of_to_plat = p2sb_of_to_plat,
.plat_auto = sizeof(struct p2sb_plat),
.per_child_plat_auto = sizeof(struct p2sb_child_plat),
.child_post_bind = p2sb_child_post_bind,
.flags = DM_FLAG_OS_PREPARE,
};

2
arch/x86/cpu/irq.c
View File

@ -362,5 +362,5 @@ U_BOOT_DRIVER(irq_router_drv) = {
.id = UCLASS_IRQ,
.of_match = irq_router_ids,
.probe = irq_router_probe,
.priv_auto_alloc_size = sizeof(struct irq_router),
.priv_auto = sizeof(struct irq_router),
};

4
arch/x86/cpu/mp_init.c
View File

@ -221,7 +221,7 @@ static int find_cpu_by_apic_id(int apic_id, struct udevice **devp)
for (uclass_find_first_device(UCLASS_CPU, &dev);
dev;
uclass_find_next_device(&dev)) {
struct cpu_platdata *plat = dev_get_parent_platdata(dev);
struct cpu_plat *plat = dev_get_parent_plat(dev);
if (plat->cpu_id == apic_id) {
*devp = dev;
@ -706,7 +706,7 @@ static int ap_wait_for_instruction(struct udevice *cpu, void *unused)
static int mp_init_cpu(struct udevice *cpu, void *unused)
{
struct cpu_platdata *plat = dev_get_parent_platdata(cpu);
struct cpu_plat *plat = dev_get_parent_plat(cpu);
plat->ucode_version = microcode_read_rev();
plat->device_id = gd->arch.x86_device;

4
arch/x86/cpu/qfw_cpu.c
View File

@ -18,7 +18,7 @@ int qemu_cpu_fixup(void)
int cpu_num;
int cpu_online;
struct udevice *dev, *pdev;
struct cpu_platdata *plat;
struct cpu_plat *plat;
char *cpu;
/* first we need to find '/cpus' */
@ -67,7 +67,7 @@ int qemu_cpu_fixup(void)
printf("binding cpu@%d failed: %d\n", cpu_num, ret);
return ret;
}
plat = dev_get_parent_platdata(dev);
plat = dev_get_parent_plat(dev);
plat->cpu_id = cpu_num;
}
return 0;

10
arch/x86/cpu/slimbootloader/serial.c
View File

@ -14,11 +14,11 @@
* The serial port info hob is generated by Slim Bootloader, so eligible for
* Slim Bootloader based boards only.
*/
static int slimbootloader_serial_ofdata_to_platdata(struct udevice *dev)
static int slimbootloader_serial_of_to_plat(struct udevice *dev)
{
const efi_guid_t guid = SBL_SERIAL_PORT_INFO_GUID;
struct sbl_serial_port_info *data;
struct ns16550_platdata *plat = dev->platdata;
struct ns16550_plat *plat = dev->plat;
if (!gd->arch.hob_list)
panic("hob list not found!");
@ -57,9 +57,9 @@ U_BOOT_DRIVER(serial_slimbootloader) = {
.name = "serial_slimbootloader",
.id = UCLASS_SERIAL,
.of_match = slimbootloader_serial_ids,
.ofdata_to_platdata = slimbootloader_serial_ofdata_to_platdata,
.platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
.priv_auto_alloc_size = sizeof(struct NS16550),
.of_to_plat = slimbootloader_serial_of_to_plat,
.plat_auto = sizeof(struct ns16550_plat),
.priv_auto = sizeof(struct NS16550),
.probe = ns16550_serial_probe,
.ops = &ns16550_serial_ops,
};

2
arch/x86/cpu/tangier/pinmux.c
View File

@ -191,5 +191,5 @@ U_BOOT_DRIVER(tangier_pinctrl) = {
.id = UCLASS_SYSCON,
.of_match = tangier_pinctrl_match,
.probe = tangier_pinctrl_probe,
.priv_auto_alloc_size = sizeof(struct mrfld_pinctrl),
.priv_auto = sizeof(struct mrfld_pinctrl),
};

2
arch/x86/include/asm/arch-broadwell/gpio.h
View File

@ -11,7 +11,7 @@
#define GPIO_PER_BANK 32
#define GPIO_BANKS 3
struct broadwell_bank_platdata {
struct broadwell_bank_plat {
uint16_t base_addr;
const char *bank_name;
int bank;

2
arch/x86/include/asm/gpio.h
View File

@ -8,7 +8,7 @@
#include <asm-generic/gpio.h>
struct ich6_bank_platdata {
struct ich6_bank_plat {
uint16_t base_addr;
const char *bank_name;
int offset;

7
arch/x86/include/asm/intel_pinctrl.h
View File

@ -162,16 +162,15 @@ extern const struct pinctrl_ops intel_pinctrl_ops;
int intel_pinctrl_probe(struct udevice *dev);
/**
* intel_pinctrl_ofdata_to_platdata() - Handle common platdata setup
* intel_pinctrl_of_to_plat() - Handle common plat setup
*
* @dev: Pinctrl device
* @comm: Pad community for this device
* @num_cfgs: Number of configuration words for each pad
* @return 0 if OK, -EDOM if @comm is NULL, other -ve value on other error
*/
int intel_pinctrl_ofdata_to_platdata(struct udevice *dev,
const struct pad_community *comm,
int num_cfgs);
int intel_pinctrl_of_to_plat(struct udevice *dev,
const struct pad_community *comm, int num_cfgs);
/**
* pinctrl_route_gpe() - set GPIO groups for the general-purpose-event blocks

2
arch/x86/lib/acpi_table.c
View File

@ -74,7 +74,7 @@ int acpi_create_madt_lapics(u32 current)
for (uclass_find_first_device(UCLASS_CPU, &dev);
dev;
uclass_find_next_device(&dev)) {
struct cpu_platdata *plat = dev_get_parent_platdata(dev);
struct cpu_plat *plat = dev_get_parent_plat(dev);
int length;
length = acpi_create_madt_lapic(

4
arch/x86/lib/fsp/fsp_graphics.c
View File

@ -80,7 +80,7 @@ static int save_vesa_mode(struct vesa_mode_info *vesa)
static int fsp_video_probe(struct udevice *dev)
{
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
struct video_uc_plat *plat = dev_get_uclass_plat(dev);
struct video_priv *uc_priv = dev_get_uclass_priv(dev);
struct vesa_mode_info *vesa = &mode_info.vesa;
int ret;
@ -124,7 +124,7 @@ err:
static int fsp_video_bind(struct udevice *dev)
{
struct video_uc_platdata *plat = dev_get_uclass_platdata(dev);
struct video_uc_plat *plat = dev_get_uclass_plat(dev);
/* Set the maximum supported resolution */
plat->size = 2560 * 1600 * 4;

2
arch/x86/lib/mpspec.c
View File

@ -81,7 +81,7 @@ void mp_write_processor(struct mp_config_table *mc)
for (uclass_find_first_device(UCLASS_CPU, &dev);
dev;
uclass_find_next_device(&dev)) {
struct cpu_platdata *plat = dev_get_parent_platdata(dev);
struct cpu_plat *plat = dev_get_parent_plat(dev);
u8 cpuflag = MPC_CPU_EN;
if (!device_active(dev))

2
arch/x86/lib/pmu.c
View File

@ -113,5 +113,5 @@ U_BOOT_DRIVER(intel_mid_pmu) = {
.id = UCLASS_SYSCON,
.of_match = pmu_mid_match,
.probe = pmu_mid_probe,
.priv_auto_alloc_size = sizeof(struct pmu_mid),
.priv_auto = sizeof(struct pmu_mid),
};

2
arch/x86/lib/scu.c
View File

@ -227,5 +227,5 @@ U_BOOT_DRIVER(scu_ipc) = {
.id = UCLASS_SYSCON,
.of_match = scu_ipc_match,
.probe = scu_ipc_probe,
.priv_auto_alloc_size = sizeof(struct scu),
.priv_auto = sizeof(struct scu),
};

2
arch/x86/lib/sfi.c
View File

@ -84,7 +84,7 @@ static int sfi_write_cpus(struct table_info *tab)
for (uclass_find_first_device(UCLASS_CPU, &dev);
dev;
uclass_find_next_device(&dev)) {
struct cpu_platdata *plat = dev_get_parent_platdata(dev);
struct cpu_plat *plat = dev_get_parent_plat(dev);
if (!device_active(dev))
continue;

4
board/armltd/integrator/integrator.c
View File

@ -32,7 +32,7 @@
DECLARE_GLOBAL_DATA_PTR;
static const struct pl01x_serial_platdata serial_platdata = {
static const struct pl01x_serial_plat serial_plat = {
.base = 0x16000000,
#ifdef CONFIG_ARCH_CINTEGRATOR
.type = TYPE_PL011,
@ -45,7 +45,7 @@ static const struct pl01x_serial_platdata serial_platdata = {
U_BOOT_DEVICE(integrator_serials) = {
.name = "serial_pl01x",
.platdata = &serial_platdata,
.plat = &serial_plat,
};
void peripheral_power_enable (void);

4
board/armltd/total_compute/total_compute.c
View File

@ -9,7 +9,7 @@
#include <dm/platform_data/serial_pl01x.h>
#include <asm/armv8/mmu.h>
static const struct pl01x_serial_platdata serial_platdata = {
static const struct pl01x_serial_plat serial_plat = {
.base = UART0_BASE,
.type = TYPE_PL011,
.clock = CONFIG_PL011_CLOCK,
@ -17,7 +17,7 @@ static const struct pl01x_serial_platdata serial_platdata = {
U_BOOT_DEVICE(total_compute_serials) = {
.name = "serial_pl01x",
.platdata = &serial_platdata,
.plat = &serial_plat,
};
static struct mm_region total_compute_mem_map[] = {

4
board/armltd/vexpress64/vexpress64.c
View File

@ -20,7 +20,7 @@
DECLARE_GLOBAL_DATA_PTR;
static const struct pl01x_serial_platdata serial_platdata = {
static const struct pl01x_serial_plat serial_plat = {
.base = V2M_UART0,
.type = TYPE_PL011,
.clock = CONFIG_PL011_CLOCK,
@ -28,7 +28,7 @@ static const struct pl01x_serial_platdata serial_platdata = {
U_BOOT_DEVICE(vexpress_serials) = {
.name = "serial_pl01x",
.platdata = &serial_platdata,
.plat = &serial_plat,
};
static struct mm_region vexpress64_mem_map[] = {

6
board/bluewater/gurnard/gurnard.c
View File

@ -348,7 +348,7 @@ int board_init(void)
uclass_find_first_device(UCLASS_VIDEO, &dev);
if (dev) {
struct atmel_lcd_platdata *plat = dev_get_platdata(dev);
struct atmel_lcd_plat *plat = dev_get_plat(dev);
plat->timing_index = 1;
}
@ -416,11 +416,11 @@ void reset_phy(void)
{
}
static struct atmel_serial_platdata at91sam9260_serial_plat = {
static struct atmel_serial_plat at91sam9260_serial_plat = {
.base_addr = ATMEL_BASE_DBGU,
};
U_BOOT_DEVICE(at91sam9260_serial) = {
.name = "serial_atmel",
.platdata = &at91sam9260_serial_plat,
.plat = &at91sam9260_serial_plat,
};

4
board/bluewater/snapper9260/snapper9260.c
View File

@ -143,11 +143,11 @@ void reset_phy(void)
{
}
static struct atmel_serial_platdata at91sam9260_serial_plat = {
static struct atmel_serial_plat at91sam9260_serial_plat = {
.base_addr = ATMEL_BASE_DBGU,
};
U_BOOT_DEVICE(at91sam9260_serial) = {
.name = "serial_atmel",
.platdata = &at91sam9260_serial_plat,
.plat = &at91sam9260_serial_plat,
};

2
board/cadence/xtfpga/xtfpga.c
View File

@ -106,5 +106,5 @@ static struct ethoc_eth_pdata ethoc_pdata = {
U_BOOT_DEVICE(ethoc) = {
.name = "ethoc",
.platdata = &ethoc_pdata,
.plat = &ethoc_pdata,
};

8
board/cavium/thunderx/thunderx.c
View File

@ -18,7 +18,7 @@
#if !CONFIG_IS_ENABLED(OF_CONTROL)
#include <dm/platform_data/serial_pl01x.h>
static const struct pl01x_serial_platdata serial0 = {
static const struct pl01x_serial_plat serial0 = {
.base = CONFIG_SYS_SERIAL0,
.type = TYPE_PL011,
.clock = 0,
@ -27,10 +27,10 @@ static const struct pl01x_serial_platdata serial0 = {
U_BOOT_DEVICE(thunderx_serial0) = {
.name = "serial_pl01x",
.platdata = &serial0,
.plat = &serial0,
};
static const struct pl01x_serial_platdata serial1 = {
static const struct pl01x_serial_plat serial1 = {
.base = CONFIG_SYS_SERIAL1,
.type = TYPE_PL011,
.clock = 0,
@ -39,7 +39,7 @@ static const struct pl01x_serial_platdata serial1 = {
U_BOOT_DEVICE(thunderx_serial1) = {
.name = "serial_pl01x",
.platdata = &serial1,
.plat = &serial1,
};
#endif

4
board/compulab/cm_fx6/cm_fx6.c
View File

@ -724,13 +724,13 @@ u32 get_board_rev(void)
return cl_eeprom_get_board_rev(CONFIG_SYS_I2C_EEPROM_BUS);
}
static struct mxc_serial_platdata cm_fx6_mxc_serial_plat = {
static struct mxc_serial_plat cm_fx6_mxc_serial_plat = {
.reg = (struct mxc_uart *)UART4_BASE,
};
U_BOOT_DEVICE(cm_fx6_serial) = {
.name = "serial_mxc",
.platdata = &cm_fx6_mxc_serial_plat,
.plat = &cm_fx6_mxc_serial_plat,
};
#if CONFIG_IS_ENABLED(AHCI)

8
board/davinci/da8xxevm/omapl138_lcdk.c
View File

@ -356,7 +356,7 @@ int board_mmc_init(struct bd_info *bis)
#endif
#ifdef CONFIG_SPL_BUILD
static const struct ns16550_platdata serial_pdata = {
static const struct ns16550_plat serial_pdata = {
.base = DAVINCI_UART2_BASE,
.reg_shift = 2,
.clock = 228000000,
@ -365,10 +365,10 @@ static const struct ns16550_platdata serial_pdata = {
U_BOOT_DEVICE(omapl138_uart) = {
.name = "ns16550_serial",
.platdata = &serial_pdata,
.plat = &serial_pdata,
};
static const struct davinci_mmc_plat mmc_platdata = {
static const struct davinci_mmc_plat mmc_plat = {
.reg_base = (struct davinci_mmc_regs *)DAVINCI_MMC_SD0_BASE,
.cfg = {
.f_min = 200000,
@ -381,7 +381,7 @@ static const struct davinci_mmc_plat mmc_platdata = {
};
U_BOOT_DEVICE(omapl138_mmc) = {
.name = "ti_da830_mmc",
.platdata = &mmc_platdata,
.plat = &mmc_plat,
};
void spl_board_init(void)

4
board/freescale/ls1012afrdm/eth.c
View File

@ -116,10 +116,10 @@ static struct pfe_eth_pdata pfe_pdata1 = {
U_BOOT_DEVICE(ls1012a_pfe0) = {
.name = "pfe_eth",
.platdata = &pfe_pdata0,
.plat = &pfe_pdata0,
};
U_BOOT_DEVICE(ls1012a_pfe1) = {
.name = "pfe_eth",
.platdata = &pfe_pdata1,
.plat = &pfe_pdata1,
};

4
board/freescale/ls1012aqds/eth.c
View File

@ -300,10 +300,10 @@ static struct pfe_eth_pdata pfe_pdata1 = {
U_BOOT_DEVICE(ls1012a_pfe0) = {
.name = "pfe_eth",
.platdata = &pfe_pdata0,
.plat = &pfe_pdata0,
};
U_BOOT_DEVICE(ls1012a_pfe1) = {
.name = "pfe_eth",
.platdata = &pfe_pdata1,
.plat = &pfe_pdata1,
};

4
board/freescale/ls1012ardb/eth.c
View File

@ -162,10 +162,10 @@ static struct pfe_eth_pdata pfe_pdata1 = {
U_BOOT_DEVICE(ls1012a_pfe0) = {
.name = "pfe_eth",
.platdata = &pfe_pdata0,
.plat = &pfe_pdata0,
};
U_BOOT_DEVICE(ls1012a_pfe1) = {
.name = "pfe_eth",
.platdata = &pfe_pdata1,
.plat = &pfe_pdata1,
};

8
board/freescale/lx2160a/lx2160a.c
View File

@ -51,7 +51,7 @@
DECLARE_GLOBAL_DATA_PTR;
static struct pl01x_serial_platdata serial0 = {
static struct pl01x_serial_plat serial0 = {
#if CONFIG_CONS_INDEX == 0
.base = CONFIG_SYS_SERIAL0,
#elif CONFIG_CONS_INDEX == 1
@ -64,17 +64,17 @@ static struct pl01x_serial_platdata serial0 = {
U_BOOT_DEVICE(nxp_serial0) = {
.name = "serial_pl01x",
.platdata = &serial0,
.plat = &serial0,
};
static struct pl01x_serial_platdata serial1 = {
static struct pl01x_serial_plat serial1 = {
.base = CONFIG_SYS_SERIAL1,
.type = TYPE_PL011,
};
U_BOOT_DEVICE(nxp_serial1) = {
.name = "serial_pl01x",
.platdata = &serial1,
.plat = &serial1,
};
int select_i2c_ch_pca9547(u8 ch)

4
board/gateworks/gw_ventana/gw_ventana.c
View File

@ -1371,11 +1371,11 @@ int ft_board_setup(void *blob, struct bd_info *bd)
}
#endif /* CONFIG_OF_BOARD_SETUP */
static struct mxc_serial_platdata ventana_mxc_serial_plat = {
static struct mxc_serial_plat ventana_mxc_serial_plat = {
.reg = (struct mxc_uart *)UART2_BASE,
};
U_BOOT_DEVICE(ventana_serial) = {
.name = "serial_mxc",
.platdata = &ventana_mxc_serial_plat,
.plat = &ventana_mxc_serial_plat,
};

6
board/hisilicon/hikey/hikey.c
View File

@ -26,7 +26,7 @@
#include <asm/armv8/mmu.h>
/*TODO drop this table in favour of device tree */
static const struct hikey_gpio_platdata hi6220_gpio[] = {
static const struct hikey_gpio_plat hi6220_gpio[] = {
{ 0, HI6220_GPIO_BASE(0)},
{ 1, HI6220_GPIO_BASE(1)},
{ 2, HI6220_GPIO_BASE(2)},
@ -77,7 +77,7 @@ DECLARE_GLOBAL_DATA_PTR;
#if !CONFIG_IS_ENABLED(OF_CONTROL)
static const struct pl01x_serial_platdata serial_platdata = {
static const struct pl01x_serial_plat serial_plat = {
#if CONFIG_CONS_INDEX == 1
.base = HI6220_UART0_BASE,
#elif CONFIG_CONS_INDEX == 4
@ -91,7 +91,7 @@ static const struct pl01x_serial_platdata serial_platdata = {
U_BOOT_DEVICE(hikey_seriala) = {
.name = "serial_pl01x",
.platdata = &serial_platdata,
.plat = &serial_plat,
};
#endif

4
board/hisilicon/hikey960/hikey960.c
View File

@ -26,7 +26,7 @@ DECLARE_GLOBAL_DATA_PTR;
#if !CONFIG_IS_ENABLED(OF_CONTROL)
#include <dm/platform_data/serial_pl01x.h>
static const struct pl01x_serial_platdata serial_platdata = {
static const struct pl01x_serial_plat serial_plat = {
.base = HI3660_UART6_BASE,
.type = TYPE_PL011,
.clock = 19200000
@ -34,7 +34,7 @@ static const struct pl01x_serial_platdata serial_platdata = {
U_BOOT_DEVICE(hikey960_serial0) = {
.name = "serial_pl01x",
.platdata = &serial_platdata,
.plat = &serial_plat,
};
#endif

4
board/hisilicon/poplar/poplar.c
View File

@ -40,7 +40,7 @@ static struct mm_region poplar_mem_map[] = {
struct mm_region *mem_map = poplar_mem_map;
#if !CONFIG_IS_ENABLED(OF_CONTROL)
static const struct pl01x_serial_platdata serial_platdata = {
static const struct pl01x_serial_plat serial_plat = {
.base = REG_BASE_UART0,
.type = TYPE_PL010,
.clock = 75000000,
@ -48,7 +48,7 @@ static const struct pl01x_serial_platdata serial_platdata = {
U_BOOT_DEVICE(poplar_serial) = {
.name = "serial_pl01x",
.platdata = &serial_platdata,
.plat = &serial_plat,
};
#endif

2
board/intel/galileo/galileo.c
View File

@ -12,7 +12,7 @@
* Intel Galileo gen2 board uses GPIO Resume Well bank pin0 as the PERST# pin.
*
* We cannot use any public GPIO APIs in <asm-generic/gpio.h> to control this
* pin, as these APIs will eventually call into gpio_ich6_ofdata_to_platdata()
* pin, as these APIs will eventually call into gpio_ich6_of_to_plat()
* in the Intel ICH6 GPIO driver where it calls PCI configuration space access
* APIs which will trigger PCI enumeration process.
*

2
board/isee/igep00x0/igep00x0.c
View File

@ -29,7 +29,7 @@
#include <fdt_support.h>
#include "igep00x0.h"
static const struct ns16550_platdata igep_serial = {
static const struct ns16550_plat igep_serial = {
.base = OMAP34XX_UART3,
.reg_shift = 2,
.clock = V_NS16550_CLK,

4
board/lg/sniper/sniper.c
View File

@ -30,7 +30,7 @@ const omap3_sysinfo sysinfo = {
.nand_string = "MMC"
};
static const struct ns16550_platdata serial_omap_platdata = {
static const struct ns16550_plat serial_omap_plat = {
.base = OMAP34XX_UART3,
.reg_shift = 2,
.clock = V_NS16550_CLK,
@ -39,7 +39,7 @@ static const struct ns16550_platdata serial_omap_platdata = {
U_BOOT_DEVICE(sniper_serial) = {
.name = "ns16550_serial",
.platdata = &serial_omap_platdata
.plat = &serial_omap_plat
};
static struct musb_hdrc_config musb_config = {

2
board/nokia/rx51/rx51.c
View File

@ -703,7 +703,7 @@ void board_mmc_power_init(void)
twl4030_power_mmc_init(1);
}
static const struct omap_i2c_platdata rx51_i2c[] = {
static const struct omap_i2c_plat rx51_i2c[] = {
{ I2C_BASE1, 2200000, OMAP_I2C_REV_V1 },
{ I2C_BASE2, 100000, OMAP_I2C_REV_V1 },
{ I2C_BASE3, 400000, OMAP_I2C_REV_V1 },

2
board/renesas/ulcb/cpld.c
View File

@ -188,5 +188,5 @@ U_BOOT_DRIVER(sysreset_renesas_ulcb) = {
.ops = &renesas_ulcb_sysreset,
.probe = renesas_ulcb_sysreset_probe,
.of_match = renesas_ulcb_sysreset_ids,
.priv_auto_alloc_size = sizeof(struct renesas_ulcb_sysreset_priv),
.priv_auto = sizeof(struct renesas_ulcb_sysreset_priv),
};

4
board/siemens/corvus/board.c
View File

@ -314,11 +314,11 @@ void spi_cs_deactivate(struct spi_slave *slave)
}
}
static struct atmel_serial_platdata at91sam9260_serial_plat = {
static struct atmel_serial_plat at91sam9260_serial_plat = {
.base_addr = ATMEL_BASE_DBGU,
};
U_BOOT_DEVICE(at91sam9260_serial) = {
.name = "serial_atmel",
.platdata = &at91sam9260_serial_plat,
.plat = &at91sam9260_serial_plat,
};

4
board/st/stv0991/stv0991.c
View File

@ -24,7 +24,7 @@ struct gpio_regs *const gpioa_regs =
(struct gpio_regs *) GPIOA_BASE_ADDR;
#ifndef CONFIG_OF_CONTROL
static const struct pl01x_serial_platdata serial_platdata = {
static const struct pl01x_serial_plat serial_plat = {
.base = 0x80406000,
.type = TYPE_PL011,
.clock = 2700 * 1000,
@ -32,7 +32,7 @@ static const struct pl01x_serial_platdata serial_platdata = {
U_BOOT_DEVICE(stv09911_serials) = {
.name = "serial_pl01x",
.platdata = &serial_platdata,
.plat = &serial_plat,
};
#endif

4
board/sysam/amcore/amcore.c
View File

@ -107,7 +107,7 @@ int dram_init(void)
return 0;
}
static struct coldfire_serial_platdata mcf5307_serial_plat = {
static struct coldfire_serial_plat mcf5307_serial_plat = {
.base = CONFIG_SYS_UART_BASE,
.port = 0,
.baudrate = CONFIG_BAUDRATE,
@ -115,5 +115,5 @@ static struct coldfire_serial_platdata mcf5307_serial_plat = {
U_BOOT_DEVICE(coldfire_serial) = {
.name = "serial_coldfire",
.platdata = &mcf5307_serial_plat,
.plat = &mcf5307_serial_plat,
};

12
board/ti/am335x/board.c
View File

@ -885,7 +885,7 @@ int board_late_init(void)
}
#endif
/* CPSW platdata */
/* CPSW plat */
#if !CONFIG_IS_ENABLED(OF_CONTROL)
struct cpsw_slave_data slave_data[] = {
{
@ -929,7 +929,7 @@ struct eth_pdata cpsw_pdata = {
U_BOOT_DEVICE(am335x_eth) = {
.name = "eth_cpsw",
.platdata = &cpsw_pdata,
.plat = &cpsw_pdata,
};
#endif
@ -963,7 +963,7 @@ void board_fit_image_post_process(void **p_image, size_t *p_size)
#endif
#if !CONFIG_IS_ENABLED(OF_CONTROL)
static const struct omap_hsmmc_plat am335x_mmc0_platdata = {
static const struct omap_hsmmc_plat am335x_mmc0_plat = {
.base_addr = (struct hsmmc *)OMAP_HSMMC1_BASE,
.cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_4BIT,
.cfg.f_min = 400000,
@ -974,10 +974,10 @@ static const struct omap_hsmmc_plat am335x_mmc0_platdata = {
U_BOOT_DEVICE(am335x_mmc0) = {
.name = "omap_hsmmc",
.platdata = &am335x_mmc0_platdata,
.plat = &am335x_mmc0_plat,
};
static const struct omap_hsmmc_plat am335x_mmc1_platdata = {
static const struct omap_hsmmc_plat am335x_mmc1_plat = {
.base_addr = (struct hsmmc *)OMAP_HSMMC2_BASE,
.cfg.host_caps = MMC_MODE_HS_52MHz | MMC_MODE_HS | MMC_MODE_8BIT,
.cfg.f_min = 400000,
@ -988,6 +988,6 @@ static const struct omap_hsmmc_plat am335x_mmc1_platdata = {
U_BOOT_DEVICE(am335x_mmc1) = {
.name = "omap_hsmmc",
.platdata = &am335x_mmc1_platdata,
.plat = &am335x_mmc1_plat,
};
#endif

2
board/timll/devkit8000/devkit8000.c
View File

@ -47,7 +47,7 @@ static u32 gpmc_net_config[GPMC_MAX_REG] = {
0
};
static const struct ns16550_platdata devkit8000_serial = {
static const struct ns16550_plat devkit8000_serial = {
.base = OMAP34XX_UART3,
.reg_shift = 2,
.clock = V_NS16550_CLK,

4
board/toradex/apalis_imx6/apalis_imx6.c
View File

@ -1144,12 +1144,12 @@ void reset_cpu(ulong addr)
#endif /* CONFIG_SPL_BUILD */
static struct mxc_serial_platdata mxc_serial_plat = {
static struct mxc_serial_plat mxc_serial_plat = {
.reg = (struct mxc_uart *)UART1_BASE,
.use_dte = true,
};
U_BOOT_DEVICE(mxc_serial) = {
.name = "serial_mxc",
.platdata = &mxc_serial_plat,
.plat = &mxc_serial_plat,
};

4
board/toradex/colibri-imx6ull/colibri-imx6ull.c
View File

@ -203,12 +203,12 @@ int ft_board_setup(void *blob, struct bd_info *bd)
}
#endif
static struct mxc_serial_platdata mxc_serial_plat = {
static struct mxc_serial_plat mxc_serial_plat = {
.reg = (struct mxc_uart *)UART1_BASE,
.use_dte = 1,
};
U_BOOT_DEVICE(mxc_serial) = {
.name = "serial_mxc",
.platdata = &mxc_serial_plat,
.plat = &mxc_serial_plat,
};

4
board/toradex/colibri_imx6/colibri_imx6.c
View File

@ -1086,12 +1086,12 @@ void reset_cpu(ulong addr)
#endif /* CONFIG_SPL_BUILD */
static struct mxc_serial_platdata mxc_serial_plat = {
static struct mxc_serial_plat mxc_serial_plat = {
.reg = (struct mxc_uart *)UART1_BASE,
.use_dte = true,
};
U_BOOT_DEVICE(mxc_serial) = {
.name = "serial_mxc",
.platdata = &mxc_serial_plat,
.plat = &mxc_serial_plat,
};

8
board/toradex/colibri_pxa270/colibri_pxa270.c
View File

@ -129,18 +129,18 @@ int board_mmc_init(struct bd_info *bis)
return 0;
}
#else /* !CONFIG_IS_ENABLED(DM_MMC) */
static const struct pxa_mmc_plat mmc_platdata = {
static const struct pxa_mmc_plat mmc_plat = {
.base = (struct pxa_mmc_regs *)MMC0_BASE,
};
U_BOOT_DEVICE(pxa_mmcs) = {
.name = "pxa_mmc",
.platdata = &mmc_platdata,
.plat = &mmc_plat,
};
#endif /* !CONFIG_IS_ENABLED(DM_MMC) */
#endif
static const struct pxa_serial_platdata serial_platdata = {
static const struct pxa_serial_plat serial_plat = {
.base = (struct pxa_uart_regs *)FFUART_BASE,
.port = FFUART_INDEX,
.baudrate = CONFIG_BAUDRATE,
@ -148,5 +148,5 @@ static const struct pxa_serial_platdata serial_platdata = {
U_BOOT_DEVICE(pxa_serials) = {
.name = "serial_pxa",
.platdata = &serial_platdata,
.plat = &serial_plat,
};

4
cmd/Kconfig
View File

@ -1691,7 +1691,7 @@ config CMD_EFIDEBUG
config CMD_EXCEPTION
bool "exception - raise exception"
depends on ARM || RISCV || X86
depends on ARM || RISCV || SANDBOX || X86
help
Enable the 'exception' command which allows to raise an exception.
@ -1917,7 +1917,7 @@ config CMD_REGULATOR
The '-f' (force) option can be used for set the value which exceeds
the limits, which are found in device-tree and are kept in regulator's
uclass platdata structure.
uclass plat structure.
endmenu

1
cmd/Makefile
View File

@ -193,6 +193,7 @@ obj-$(CONFIG_CMD_AVB) += avb.o
obj-$(CONFIG_ARM) += arm/
obj-$(CONFIG_RISCV) += riscv/
obj-$(CONFIG_SANDBOX) += sandbox/
obj-$(CONFIG_X86) += x86/
obj-$(CONFIG_ARCH_MVEBU) += mvebu/

2
cmd/button.c
View File

@ -37,7 +37,7 @@ static int list_buttons(void)
for (uclass_find_first_device(UCLASS_BUTTON, &dev);
dev;
uclass_find_next_device(&dev)) {
struct button_uc_plat *plat = dev_get_uclass_platdata(dev);
struct button_uc_plat *plat = dev_get_uclass_plat(dev);
if (!plat->label)
continue;

2
cmd/cpu.c
View File

@ -26,7 +26,7 @@ static int print_cpu_list(bool detail)
for (uclass_first_device(UCLASS_CPU, &dev);
dev;
uclass_next_device(&dev)) {
struct cpu_platdata *plat = dev_get_parent_platdata(dev);
struct cpu_plat *plat = dev_get_parent_plat(dev);
struct cpu_info info;
bool first = true;
int ret, i;

4
cmd/demo.c
View File

@ -71,10 +71,10 @@ int do_demo_list(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
for (i = 0, ret = uclass_first_device(UCLASS_DEMO, &dev);
dev;
ret = uclass_next_device(&dev)) {
printf("entry %d - instance %08x, ops %08x, platdata %08x\n",
printf("entry %d - instance %08x, ops %08x, plat %08x\n",
i++, (uint)map_to_sysmem(dev),
(uint)map_to_sysmem(dev->driver->ops),
(uint)map_to_sysmem(dev_get_platdata(dev)));
(uint)map_to_sysmem(dev_get_plat(dev)));
}
return cmd_process_error(cmdtp, ret);

2
cmd/host.c
View File

@ -91,7 +91,7 @@ static int do_host_info(struct cmd_tbl *cmdtp, int flag, int argc,
struct host_block_dev *host_dev;
#ifdef CONFIG_BLK
host_dev = dev_get_platdata(blk_dev->bdev);
host_dev = dev_get_plat(blk_dev->bdev);
#else
host_dev = blk_dev->priv;
#endif

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