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https://github.com/brain-hackers/u-boot-brain
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net: mvpp2: add 1000BaseX and 2500BaseX ppv2 support
Signed-off-by: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
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8d3aa376a9
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@ -2880,6 +2880,10 @@ static void mvpp2_port_mii_set(struct mvpp2_port *port)
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case PHY_INTERFACE_MODE_SGMII:
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val |= MVPP2_GMAC_INBAND_AN_MASK;
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break;
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case PHY_INTERFACE_MODE_1000BASEX:
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case PHY_INTERFACE_MODE_2500BASEX:
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val &= ~MVPP2_GMAC_INBAND_AN_MASK;
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break;
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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val |= MVPP2_GMAC_PORT_RGMII_MASK;
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@ -2940,7 +2944,9 @@ static void mvpp2_port_loopback_set(struct mvpp2_port *port)
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else
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val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
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if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
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if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
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port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
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port->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
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val |= MVPP2_GMAC_PCS_LB_EN_MASK;
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else
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val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
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@ -3051,10 +3057,10 @@ static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port *port)
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val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
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/*
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* Configure GIG MAC to 1000Base-X mode connected to a fiber
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* Configure GIG MAC to SGMII mode connected to a fiber
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* transceiver
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*/
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val |= MVPP2_GMAC_PORT_TYPE_MASK;
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val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
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writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
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/* configure AN 0x9268 */
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@ -3106,6 +3112,89 @@ static void gop_gmac_sgmii_cfg(struct mvpp2_port *port)
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writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
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}
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static void gop_gmac_2500basex_cfg(struct mvpp2_port *port)
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{
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u32 val, thresh;
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/*
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* Configure minimal level of the Tx FIFO before the lower part
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* starts to read a packet
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*/
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thresh = MVPP2_SGMII2_5_TX_FIFO_MIN_TH;
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val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
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val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
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val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
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writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
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/* Disable bypass of sync module */
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val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
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val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
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/* configure DP clock select according to mode */
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val |= MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
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/* configure QSGMII bypass according to mode */
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val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
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writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
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val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
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/*
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* Configure GIG MAC to 2500Base-X mode connected to a fiber
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* transceiver
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*/
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val |= MVPP2_GMAC_PORT_TYPE_MASK;
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writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
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/* In 2500BaseX mode, we can't negotiate speed
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* and we do not want InBand autoneg
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* bypass enabled (link interrupt storm risk
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* otherwise).
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*/
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val = MVPP2_GMAC_EN_PCS_AN |
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MVPP2_GMAC_CONFIG_GMII_SPEED |
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MVPP2_GMAC_CONFIG_FULL_DUPLEX |
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MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
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writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
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}
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static void gop_gmac_1000basex_cfg(struct mvpp2_port *port)
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{
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u32 val, thresh;
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/*
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* Configure minimal level of the Tx FIFO before the lower part
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* starts to read a packet
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*/
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thresh = MVPP2_SGMII_TX_FIFO_MIN_TH;
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val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
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val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
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val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
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writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
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/* Disable bypass of sync module */
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val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
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val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
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/* configure DP clock select according to mode */
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val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
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/* configure QSGMII bypass according to mode */
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val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
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writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
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val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
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/* configure GIG MAC to 1000BASEX mode */
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val |= MVPP2_GMAC_PORT_TYPE_MASK;
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writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
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/* In 1000BaseX mode, we can't negotiate speed (it's
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* only 1000), and we do not want InBand autoneg
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* bypass enabled (link interrupt storm risk
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* otherwise).
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*/
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val = MVPP2_GMAC_EN_PCS_AN |
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MVPP2_GMAC_CONFIG_GMII_SPEED |
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MVPP2_GMAC_CONFIG_FULL_DUPLEX |
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MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
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writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
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}
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static void gop_gmac_rgmii_cfg(struct mvpp2_port *port)
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{
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u32 val, thresh;
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@ -3157,6 +3246,12 @@ static int gop_gmac_mode_cfg(struct mvpp2_port *port)
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gop_gmac_sgmii_cfg(port);
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break;
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case PHY_INTERFACE_MODE_1000BASEX:
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gop_gmac_1000basex_cfg(port);
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case PHY_INTERFACE_MODE_2500BASEX:
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gop_gmac_2500basex_cfg(port);
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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gop_gmac_rgmii_cfg(port);
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@ -3329,6 +3424,8 @@ static int gop_port_init(struct mvpp2_port *port)
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break;
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_1000BASEX:
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case PHY_INTERFACE_MODE_2500BASEX:
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/* configure PCS */
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gop_gpcs_mode_cfg(port, 1);
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@ -3386,6 +3483,8 @@ static void gop_port_enable(struct mvpp2_port *port, int enable)
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_1000BASEX:
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case PHY_INTERFACE_MODE_2500BASEX:
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if (enable)
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mvpp2_port_enable(port);
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else
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@ -3419,7 +3518,9 @@ static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type)
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u32 val = 0;
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if (gop_id == 2) {
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if (phy_type == PHY_INTERFACE_MODE_SGMII)
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if (phy_type == PHY_INTERFACE_MODE_SGMII ||
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phy_type == PHY_INTERFACE_MODE_1000BASEX ||
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phy_type == PHY_INTERFACE_MODE_2500BASEX)
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val |= MV_NETC_GE_MAC2_SGMII;
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else if (phy_type == PHY_INTERFACE_MODE_RGMII ||
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phy_type == PHY_INTERFACE_MODE_RGMII_ID)
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@ -3427,7 +3528,9 @@ static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type)
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}
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if (gop_id == 3) {
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if (phy_type == PHY_INTERFACE_MODE_SGMII)
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if (phy_type == PHY_INTERFACE_MODE_SGMII ||
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phy_type == PHY_INTERFACE_MODE_1000BASEX ||
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phy_type == PHY_INTERFACE_MODE_2500BASEX)
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val |= MV_NETC_GE_MAC3_SGMII;
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else if (phy_type == PHY_INTERFACE_MODE_RGMII ||
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phy_type == PHY_INTERFACE_MODE_RGMII_ID)
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@ -4423,6 +4526,8 @@ static void mvpp2_start_dev(struct mvpp2_port *port)
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_1000BASEX:
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case PHY_INTERFACE_MODE_2500BASEX:
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mvpp2_gmac_max_rx_size_set(port);
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default:
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break;
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@ -5159,6 +5264,8 @@ static int mvpp2_start(struct udevice *dev)
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_SGMII:
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case PHY_INTERFACE_MODE_1000BASEX:
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case PHY_INTERFACE_MODE_2500BASEX:
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mvpp2_port_power_up(port);
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default:
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break;
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