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x86: Add basic Intel Quark processor support
Add minimum codes to support Intel Quark SoC. DRAM initialization is not ready yet so a hardcoded gd->ram_size is assigned. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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121
arch/x86/cpu/quark/Kconfig
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121
arch/x86/cpu/quark/Kconfig
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#
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# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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config INTEL_QUARK
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bool
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select HAVE_RMU
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if INTEL_QUARK
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config HAVE_RMU
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bool "Add a Remote Management Unit (RMU) binary"
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help
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Select this option to add a Remote Management Unit (RMU) binary
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to the resulting U-Boot image. It is a data block (up to 64K) of
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machine-specific code which must be put in the flash for the RMU
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within the Quark SoC processor to access when powered up before
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system BIOS is executed.
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config RMU_FILE
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string "Remote Management Unit (RMU) binary filename"
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depends on HAVE_RMU
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default "rmu.bin"
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help
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The filename of the file to use as Remote Management Unit (RMU)
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binary in the board directory.
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config RMU_ADDR
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hex "Remote Management Unit (RMU) binary location"
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depends on HAVE_RMU
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default 0xfff00000
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help
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The location of the RMU binary is determined by a strap. It must be
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put in flash at a location matching the strap-determined base address.
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The default base address of 0xfff00000 indicates that the binary must
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be located at offset 0 from the beginning of a 1MB flash device.
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config HAVE_CMC
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bool
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default HAVE_RMU
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config CMC_FILE
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string
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depends on HAVE_CMC
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default RMU_FILE
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config CMC_ADDR
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hex
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depends on HAVE_CMC
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default RMU_ADDR
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config ESRAM_BASE
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hex
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default 0x80000000
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help
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Embedded SRAM (eSRAM) memory-mapped base address.
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config PCIE_ECAM_BASE
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hex
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default 0xe0000000
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config RCBA_BASE
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hex
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default 0xfed1c000
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help
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Root Complex register block memory-mapped base address.
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config ACPI_PM1_BASE
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hex
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default 0x1000
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help
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ACPI Power Managment 1 (PM1) i/o-mapped base address.
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This device is defined in ACPI specification, with 16 bytes in size.
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config ACPI_PBLK_BASE
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hex
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default 0x1010
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help
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ACPI Processor Block (PBLK) i/o-mapped base address.
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This device is defined in ACPI specification, with 16 bytes in size.
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config SPI_DMA_BASE
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hex
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default 0x1020
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help
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SPI DMA i/o-mapped base address.
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config GPIO_BASE
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hex
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default 0x1080
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help
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GPIO i/o-mapped base address.
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config ACPI_GPE0_BASE
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hex
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default 0x1100
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help
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ACPI General Purpose Event 0 (GPE0) i/o-mapped base address.
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This device is defined in ACPI specification, with 64 bytes in size.
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config WDT_BASE
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hex
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default 0x1140
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help
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Watchdog timer i/o-mapped base address.
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config SYS_CAR_ADDR
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hex
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default ESRAM_BASE
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config SYS_CAR_SIZE
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hex
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default 0x8000
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help
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Space in bytes in eSRAM used as Cache-As-ARM (CAR).
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Note this size must not exceed eSRAM's total size.
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endif
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8
arch/x86/cpu/quark/Makefile
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8
arch/x86/cpu/quark/Makefile
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#
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# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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#
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# SPDX-License-Identifier: GPL-2.0+
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#
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obj-y += car.o dram.o msg_port.o quark.o
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obj-$(CONFIG_PCI) += pci.o
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39
arch/x86/cpu/quark/dram.c
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39
arch/x86/cpu/quark/dram.c
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/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/post.h>
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#include <asm/arch/quark.h>
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DECLARE_GLOBAL_DATA_PTR;
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int dram_init(void)
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{
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/* hardcode the DRAM size for now */
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gd->ram_size = DRAM_MAX_SIZE;
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post_code(POST_DRAM);
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return 0;
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}
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void dram_init_banksize(void)
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{
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gd->bd->bi_dram[0].start = 0;
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gd->bd->bi_dram[0].size = gd->ram_size;
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}
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/*
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* This function looks for the highest region of memory lower than 4GB which
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* has enough space for U-Boot where U-Boot is aligned on a page boundary.
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* It overrides the default implementation found elsewhere which simply
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* picks the end of ram, wherever that may be. The location of the stack,
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* the relocation address, and how far U-Boot is moved by relocation are
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* set in the global data structure.
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*/
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ulong board_get_usable_ram_top(ulong total_size)
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{
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return gd->ram_size;
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}
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70
arch/x86/cpu/quark/pci.c
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70
arch/x86/cpu/quark/pci.c
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/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <pci.h>
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#include <asm/pci.h>
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#include <asm/arch/device.h>
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DECLARE_GLOBAL_DATA_PTR;
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void board_pci_setup_hose(struct pci_controller *hose)
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{
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hose->first_busno = 0;
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hose->last_busno = 0;
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/* PCI memory space */
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pci_set_region(hose->regions + 0,
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CONFIG_PCI_MEM_BUS,
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CONFIG_PCI_MEM_PHYS,
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CONFIG_PCI_MEM_SIZE,
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PCI_REGION_MEM);
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/* PCI IO space */
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pci_set_region(hose->regions + 1,
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CONFIG_PCI_IO_BUS,
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CONFIG_PCI_IO_PHYS,
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CONFIG_PCI_IO_SIZE,
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PCI_REGION_IO);
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pci_set_region(hose->regions + 2,
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CONFIG_PCI_PREF_BUS,
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CONFIG_PCI_PREF_PHYS,
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CONFIG_PCI_PREF_SIZE,
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PCI_REGION_PREFETCH);
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pci_set_region(hose->regions + 3,
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0,
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0,
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gd->ram_size,
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PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
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hose->region_count = 4;
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}
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int board_pci_post_scan(struct pci_controller *hose)
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{
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return 0;
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}
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int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
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{
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/*
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* TODO:
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*
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* For some unknown reason, the PCI enumeration process hangs
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* when it scans to the PCIe root port 0 (D23:F0) & 1 (D23:F1).
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*
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* For now we just skip these two devices, and this needs to
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* be revisited later.
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*/
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if (dev == QUARK_HOST_BRIDGE ||
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dev == QUARK_PCIE0 || dev == QUARK_PCIE1) {
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return 1;
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}
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return 0;
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}
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44
arch/x86/cpu/quark/quark.c
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arch/x86/cpu/quark/quark.c
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/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/pci.h>
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#include <asm/post.h>
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#include <asm/processor.h>
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int arch_cpu_init(void)
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{
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struct pci_controller *hose;
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int ret;
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post_code(POST_CPU_INIT);
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#ifdef CONFIG_SYS_X86_TSC_TIMER
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timer_set_base(rdtsc());
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#endif
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ret = x86_cpu_init_f();
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if (ret)
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return ret;
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ret = pci_early_init_hose(&hose);
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if (ret)
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return ret;
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return 0;
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}
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int print_cpuinfo(void)
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{
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post_code(POST_CPU_INFO);
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return default_print_cpuinfo();
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}
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void reset_cpu(ulong addr)
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{
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/* cold reset */
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outb(0x08, PORT_RESET);
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}
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13
arch/x86/include/asm/arch-quark/gpio.h
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13
arch/x86/include/asm/arch-quark/gpio.h
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/*
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* Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _X86_ARCH_GPIO_H_
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#define _X86_ARCH_GPIO_H_
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/* Where in config space is the register that points to the GPIO registers? */
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#define PCI_CFG_GPIOBASE 0x44
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#endif /* _X86_ARCH_GPIO_H_ */
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