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https://github.com/brain-hackers/u-boot-brain
synced 2024-09-27 23:20:26 +09:00
mips: dts: Fix PIC32MZDA GPIO register definitions
GPIO state cannot be changed via the device tree (e.g. with gpio-hog) or using the 'gpio' command from the console. The root cause is a discrepancy between the driver and the device tree: the driver code expects an absolute I/O address in the <reg> property, while the device tree defines the address relative to a declaration in the parent pinctrl node. Changing the device tree to fix a driver issue would normally be wrong, however: - I have run the first version of U-Boot in which this driver appears (v2016.03) and the same problem exists, so this is not a regression; - There is no code that references a parent device tree node that might suggest the intent of the author was to parse the DT as it exists now; - The equivalent Linux PIC32 GPIO driver also uses absolute addresses for the GPIO <reg> property. This change brings the U-Boot DT more into line with Linux. Additionally, the data sheet (Microchip ref. 60001361H) shows that the register set to control a GPIO bank spans 0xE0 bytes, but the device tree specified size is only 0x48 bytes. Signed-off-by: John Robertson <john.robertson@simiatec.com>
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@ -77,6 +77,8 @@
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};
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pinctrl: pinctrl@1f801400 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "microchip,pic32mzda-pinctrl";
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reg = <0x1f801400 0x100>, /* in */
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<0x1f801500 0x200>, /* out */
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@ -84,75 +86,72 @@
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reg-names = "ppsin","ppsout","port";
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status = "disabled";
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ranges = <0 0x1f860000 0xa00>;
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#address-cells = <1>;
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#size-cells = <1>;
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gpioA: gpio0@0 {
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gpioA: gpio0@1f860000 {
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compatible = "microchip,pic32mzda-gpio";
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reg = <0x000 0x48>;
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reg = <0x1f860000 0xe0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpioB: gpio1@100 {
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gpioB: gpio1@1f860100 {
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compatible = "microchip,pic32mzda-gpio";
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reg = <0x100 0x48>;
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reg = <0x1f860100 0xe0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpioC: gpio2@200 {
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gpioC: gpio2@1f860200 {
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compatible = "microchip,pic32mzda-gpio";
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reg = <0x200 0x48>;
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reg = <0x1f860200 0xe0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpioD: gpio3@300 {
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gpioD: gpio3@1f860300 {
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compatible = "microchip,pic32mzda-gpio";
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reg = <0x300 0x48>;
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reg = <0x1f860300 0xe0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpioE: gpio4@400 {
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gpioE: gpio4@1f860400 {
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compatible = "microchip,pic32mzda-gpio";
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reg = <0x400 0x48>;
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reg = <0x1f860400 0xe0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpioF: gpio5@500 {
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gpioF: gpio5@1f860500 {
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compatible = "microchip,pic32mzda-gpio";
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reg = <0x500 0x48>;
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reg = <0x1f860500 0xe0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpioG: gpio6@600 {
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gpioG: gpio6@1f860600 {
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compatible = "microchip,pic32mzda-gpio";
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reg = <0x600 0x48>;
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reg = <0x1f860600 0xe0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpioH: gpio7@700 {
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gpioH: gpio7@1f860700 {
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compatible = "microchip,pic32mzda-gpio";
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reg = <0x700 0x48>;
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reg = <0x1f860700 0xe0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpioJ: gpio8@800 {
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gpioJ: gpio8@1f860800 {
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compatible = "microchip,pic32mzda-gpio";
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reg = <0x800 0x48>;
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reg = <0x1f860800 0xe0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpioK: gpio9@900 {
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gpioK: gpio9@1f860900 {
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compatible = "microchip,pic32mzda-gpio";
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reg = <0x900 0x48>;
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reg = <0x1f860900 0xe0>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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