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https://github.com/brain-hackers/u-boot-brain
synced 2024-09-24 05:30:37 +09:00
sharp: fix indent
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079c491063
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816ea16594
@ -20,15 +20,15 @@ static int mxsfb_write_byte(uint32_t payload, const unsigned int data)
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const unsigned int timeout = 0x10000;
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if (mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
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timeout))
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timeout))
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return -ETIMEDOUT;
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writel((1 << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
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(1 << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET),
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®s->hw_lcdif_transfer_count);
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(1 << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET),
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®s->hw_lcdif_transfer_count);
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writel(LCDIF_CTRL_DATA_SELECT | LCDIF_CTRL_RUN,
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®s->hw_lcdif_ctrl_clr);
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®s->hw_lcdif_ctrl_clr);
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if (data)
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writel(LCDIF_CTRL_DATA_SELECT, ®s->hw_lcdif_ctrl_set);
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@ -40,7 +40,7 @@ static int mxsfb_write_byte(uint32_t payload, const unsigned int data)
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writel(payload, ®s->hw_lcdif_data);
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return mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
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timeout);
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timeout);
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}
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void mxsfb_system_setup(void)
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@ -61,22 +61,22 @@ void mxsfb_system_setup(void)
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lcd_config_t config = get_lcd_config();
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valid_data = readl(&lcdif->hw_lcdif_ctrl1) &
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LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK;
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LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK;
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writel(0x3 << LCDIF_CTRL1_BYTE_PACKING_FORMAT_OFFSET,
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&lcdif->hw_lcdif_ctrl1);
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&lcdif->hw_lcdif_ctrl1);
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/* Switch the LCDIF into System-Mode */
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writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DOTCLK_MODE |
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LCDIF_CTRL_BYPASS_COUNT,
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&lcdif->hw_lcdif_ctrl_clr);
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LCDIF_CTRL_BYPASS_COUNT,
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&lcdif->hw_lcdif_ctrl_clr);
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writel(LCDIF_CTRL_VSYNC_MODE, &lcdif->hw_lcdif_ctrl_set);
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writel(LCDIF_VDCTRL3_VSYNC_ONLY, &lcdif->hw_lcdif_vdctrl3_set);
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writel((0x01 << LCDIF_TIMING_CMD_HOLD_OFFSET) |
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(0x01 << LCDIF_TIMING_CMD_SETUP_OFFSET) |
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(0x01 << LCDIF_TIMING_DATA_HOLD_OFFSET) |
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(0x01 << LCDIF_TIMING_DATA_SETUP_OFFSET),
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&lcdif->hw_lcdif_timing);
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(0x01 << LCDIF_TIMING_CMD_SETUP_OFFSET) |
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(0x01 << LCDIF_TIMING_DATA_HOLD_OFFSET) |
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(0x01 << LCDIF_TIMING_DATA_SETUP_OFFSET),
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&lcdif->hw_lcdif_timing);
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/* Enable LCD Controller */
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gpio_direction_output(MX28_PAD_GPMI_ALE__GPIO_0_26, 1);
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@ -129,44 +129,44 @@ void mxsfb_system_setup(void)
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}
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#endif
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mxsfb_write_byte(0x11, 0); /* Sleep Out */
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mdelay(120);
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mxsfb_write_byte(0x11, 0); /* Sleep Out */
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mdelay(120);
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#ifdef CONFIG_BRAIN_2G
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mxsfb_write_byte(0x34, 0);
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mdelay(30);
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#endif
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mxsfb_write_byte(0x29, 0); /* Display On */
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mdelay(20);
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mxsfb_write_byte(0x29, 0); /* Display On */
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mdelay(20);
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mxsfb_write_byte(0x2a, 0); /* Column Address Set */
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mxsfb_write_byte(0x2a, 0); /* Column Address Set */
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mxsfb_write_byte(0x00, 1); /* Start Column in 2 Bytes */
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mxsfb_write_byte(0x00, 1);
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mxsfb_write_byte(0x00, 1); /* Start Column in 2 Bytes */
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mxsfb_write_byte(0x00, 1);
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#ifdef CONFIG_BRAIN_3G_4G
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mxsfb_write_byte((config.width & 0xff00) >> 8, 1); /* End Column in 2 Bytes */
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mxsfb_write_byte((config.width & 0x00ff) >> 0, 1);
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mxsfb_write_byte((config.width & 0xff00) >> 8, 1); /* End Column in 2 Bytes */
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mxsfb_write_byte((config.width & 0x00ff) >> 0, 1);
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#else
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mxsfb_write_byte((config.height & 0xff00) >> 8, 1); /* End Column in 2 Bytes */
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mxsfb_write_byte((config.height & 0x00ff) >> 0, 1);
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#endif
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mxsfb_write_byte(0x2b, 0); /* Page Address Set */
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mxsfb_write_byte(0x2b, 0); /* Page Address Set */
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mxsfb_write_byte(0x00, 1); /* Start Page in 2 Bytes */
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mxsfb_write_byte(0x00, 1);
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mxsfb_write_byte(0x00, 1); /* Start Page in 2 Bytes */
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mxsfb_write_byte(0x00, 1);
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#ifdef CONFIG_BRAIN_3G_4G
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mxsfb_write_byte((config.height & 0xff00) >> 8, 1); /* End Page in 2 Bytes */
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mxsfb_write_byte((config.height & 0x00ff) >> 0, 1);
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mxsfb_write_byte((config.height & 0xff00) >> 8, 1); /* End Page in 2 Bytes */
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mxsfb_write_byte((config.height & 0x00ff) >> 0, 1);
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#else
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mxsfb_write_byte((config.width & 0xff00) >> 8, 1); /* End Page in 2 Bytes */
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mxsfb_write_byte((config.width & 0x00ff) >> 0, 1);
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mxsfb_write_byte((config.width & 0x00ff) >> 0, 1);
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#endif
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mxsfb_write_byte(0x2c, 0); /* Memory Write */
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mxsfb_write_byte(0x2c, 0); /* Memory Write */
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#ifdef CONFIG_BRAIN_3G_4G
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/* Fill black */
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@ -184,7 +184,7 @@ void mxsfb_system_setup(void)
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#endif
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writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DATA_SELECT,
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&lcdif->hw_lcdif_ctrl_set);
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&lcdif->hw_lcdif_ctrl_set);
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/* Turn on backlight */
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writel(CLKCTRL_XTAL_PWM_CLK24M_GATE, &xtal->hw_clkctrl_xtal_clr);
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@ -193,29 +193,29 @@ void mxsfb_system_setup(void)
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writel(PWM_CTRL_CLKGATE, &pwm->hw_pwm_ctrl_clr);
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writel(PWM_CTRL_PWM0_ENABLE | PWM_CTRL_PWM1_ENABLE,
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&pwm->hw_pwm_ctrl_clr);
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&pwm->hw_pwm_ctrl_clr);
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writel((0x005a << PWM_ACTIVE0_INACTIVE_OFFSET) |
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(0x0000 << PWM_ACTIVE0_ACTIVE_OFFSET),
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&pwm->hw_pwm_active0_set);
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(0x0000 << PWM_ACTIVE0_ACTIVE_OFFSET),
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&pwm->hw_pwm_active0_set);
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writel((0x00f0 << PWM_ACTIVE1_INACTIVE_OFFSET) |
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(0x0000 << PWM_ACTIVE1_ACTIVE_OFFSET),
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&pwm->hw_pwm_active1_set);
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(0x0000 << PWM_ACTIVE1_ACTIVE_OFFSET),
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&pwm->hw_pwm_active1_set);
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writel((0x1 << PWM_PERIOD0_CDIV_OFFSET) |
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(0x2 << PWM_PERIOD0_INACTIVE_STATE_OFFSET) |
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(0x3 << PWM_PERIOD0_ACTIVE_STATE_OFFSET) |
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(0x01f3 << PWM_PERIOD0_PERIOD_OFFSET),
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&pwm->hw_pwm_period0_set);
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(0x2 << PWM_PERIOD0_INACTIVE_STATE_OFFSET) |
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(0x3 << PWM_PERIOD0_ACTIVE_STATE_OFFSET) |
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(0x01f3 << PWM_PERIOD0_PERIOD_OFFSET),
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&pwm->hw_pwm_period0_set);
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writel((0x0 << PWM_PERIOD1_CDIV_OFFSET) |
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(0x3 << PWM_PERIOD1_INACTIVE_STATE_OFFSET) |
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(0x3 << PWM_PERIOD1_ACTIVE_STATE_OFFSET) |
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(0x07cf << PWM_PERIOD1_PERIOD_OFFSET),
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&pwm->hw_pwm_period1_set);
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(0x3 << PWM_PERIOD1_INACTIVE_STATE_OFFSET) |
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(0x3 << PWM_PERIOD1_ACTIVE_STATE_OFFSET) |
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(0x07cf << PWM_PERIOD1_PERIOD_OFFSET),
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&pwm->hw_pwm_period1_set);
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writel(PWM_CTRL_PWM0_ENABLE | PWM_CTRL_PWM1_ENABLE,
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&pwm->hw_pwm_ctrl_set);
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&pwm->hw_pwm_ctrl_set);
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}
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#endif
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