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clk: renesas: Synchronize R-Car Gen2 tables with Linux 5.12

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Synchronize R-Car Gen2 clock tables with Linux 5.12,
commit 9f4ad9e425a1 ("Linux 5.12") .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
This commit is contained in:
Marek Vasut 2021-04-25 21:09:10 +02:00
parent f07c9ecb36
commit 8152c189bd
5 changed files with 6 additions and 9 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
drivers/clk/renesas/r8a7790-cpg-mssr.c
View File

@ -108,8 +108,8 @@ static const struct mssr_mod_clk r8a7790_mod_clks[] = {
DEF_MOD("tmu0", 125, R8A7790_CLK_CP),
DEF_MOD("vsp1du1", 127, R8A7790_CLK_ZS),
DEF_MOD("vsp1du0", 128, R8A7790_CLK_ZS),
DEF_MOD("vsp1-rt", 130, R8A7790_CLK_ZS),
DEF_MOD("vsp1-sy", 131, R8A7790_CLK_ZS),
DEF_MOD("vspr", 130, R8A7790_CLK_ZS),
DEF_MOD("vsps", 131, R8A7790_CLK_ZS),
DEF_MOD("scifa2", 202, R8A7790_CLK_MP),
DEF_MOD("scifa1", 203, R8A7790_CLK_MP),
DEF_MOD("scifa0", 204, R8A7790_CLK_MP),

2
drivers/clk/renesas/r8a7791-cpg-mssr.c
View File

@ -106,7 +106,7 @@ static const struct mssr_mod_clk r8a7791_mod_clks[] = {
DEF_MOD("tmu0", 125, R8A7791_CLK_CP),
DEF_MOD("vsp1du1", 127, R8A7791_CLK_ZS),
DEF_MOD("vsp1du0", 128, R8A7791_CLK_ZS),
DEF_MOD("vsp1-sy", 131, R8A7791_CLK_ZS),
DEF_MOD("vsps", 131, R8A7791_CLK_ZS),
DEF_MOD("scifa2", 202, R8A7791_CLK_MP),
DEF_MOD("scifa1", 203, R8A7791_CLK_MP),
DEF_MOD("scifa0", 204, R8A7791_CLK_MP),

2
drivers/clk/renesas/r8a7792-cpg-mssr.c
View File

@ -88,7 +88,7 @@ static const struct mssr_mod_clk r8a7792_mod_clks[] = {
DEF_MOD("tmu0", 125, R8A7792_CLK_CP),
DEF_MOD("vsp1du1", 127, R8A7792_CLK_ZS),
DEF_MOD("vsp1du0", 128, R8A7792_CLK_ZS),
DEF_MOD("vsp1-sy", 131, R8A7792_CLK_ZS),
DEF_MOD("vsps", 131, R8A7792_CLK_ZS),
DEF_MOD("msiof1", 208, R8A7792_CLK_MP),
DEF_MOD("sys-dmac1", 218, R8A7792_CLK_ZS),
DEF_MOD("sys-dmac0", 219, R8A7792_CLK_ZS),

2
drivers/clk/renesas/r8a7794-cpg-mssr.c
View File

@ -97,7 +97,7 @@ static const struct mssr_mod_clk r8a7794_mod_clks[] = {
DEF_MOD("cmt0", 124, R8A7794_CLK_R),
DEF_MOD("tmu0", 125, R8A7794_CLK_CP),
DEF_MOD("vsp1du0", 128, R8A7794_CLK_ZS),
DEF_MOD("vsp1-sy", 131, R8A7794_CLK_ZS),
DEF_MOD("vsps", 131, R8A7794_CLK_ZS),
DEF_MOD("scifa2", 202, R8A7794_CLK_MP),
DEF_MOD("scifa1", 203, R8A7794_CLK_MP),
DEF_MOD("scifa0", 204, R8A7794_CLK_MP),

5
drivers/clk/renesas/rcar-gen2-cpg.h
View File

@ -1,11 +1,8 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* R-Car Gen2 Clock Pulse Generator
*
* Copyright (C) 2016 Cogent Embedded Inc.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License version 2 as published
* by the Free Software Foundation; version 2 of the License.
*/
#ifndef __CLK_RENESAS_RCAR_GEN2_CPG_H__