brain-hackers_pepepper-mirror/u-boot-brain
1
0
Fork 0
mirror of https://github.com/brain-hackers/u-boot-brain synced 2024-06-09 23:36:03 +09:00
Code Issues Projects Releases Wiki Activity

mpc83xx: cosmetic: mpc8308_p1m.h checkpatch compliance

Browse Source 
Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
Cc: Joe Hershberger <joe.hershberger@gmail.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
This commit is contained in:
Joe Hershberger 2011-10-11 23:57:24 -05:00 committed by Kim Phillips
parent b43b12e6b1
commit 80ae4df929
1 changed files with 14 additions and 15 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

29
include/configs/mpc8308_p1m.h
View File

@ -220,7 +220,7 @@
*/
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
#define CONFIG_SYS_GBL_DATA_OFFSET \
(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
@ -246,10 +246,9 @@
#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
#define CONFIG_SYS_BR0_PRELIM (\
CONFIG_SYS_FLASH_BASE /* Flash Base address */ |\
(2 << BR_PS_SHIFT) /* 16 bit port size */ |\
BR_V) /* valid */
#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE /* Flash Base addr */ \
| (2 << BR_PS_SHIFT) /* 16 bit port */ \
| BR_V) /* valid */
#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \
| OR_UPM_XAM \
| OR_GPCM_CSNT \
@ -271,11 +270,11 @@
/*
* SJA1000 CAN controller on Local Bus
*/
#define CONFIG_SYS_SJA1000_BASE 0xFBFF0000
#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_SJA1000_BASE \
| (1 << BR_PS_SHIFT) /* 8 bit port size */ \
| BR_V ) /* valid */
#define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \
#define CONFIG_SYS_SJA1000_BASE 0xFBFF0000
#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_SJA1000_BASE \
| (1 << BR_PS_SHIFT) /* 8 bit port */ \
| BR_V) /* valid */
#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 /* length 32K */ \
| OR_GPCM_SCY_5 \
| OR_GPCM_EHTR)
/* 0xFFFF8052 */
@ -286,11 +285,11 @@
/*
* CPLD on Local Bus
*/
#define CONFIG_SYS_CPLD_BASE 0xFBFF8000
#define CONFIG_SYS_BR2_PRELIM ( CONFIG_SYS_CPLD_BASE \
| (1 << BR_PS_SHIFT) /* 8 bit port size */ \
| BR_V ) /* valid */
#define CONFIG_SYS_OR2_PRELIM ( 0xFFFF8000 /* length 32K */ \
#define CONFIG_SYS_CPLD_BASE 0xFBFF8000
#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_CPLD_BASE \
| (1 << BR_PS_SHIFT) /* 8 bit port */ \
| BR_V) /* valid */
#define CONFIG_SYS_OR2_PRELIM (0xFFFF8000 /* length 32K */ \
| OR_GPCM_SCY_4 \
| OR_GPCM_EHTR)
/* 0xFFFF8042 */