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tegra: clock: Add checking for invalid clock IDs
The get_pll() function can do the wrong thing if passed values that are out of range. Add checks for this and add a function which can return a 'simple' PLL. This can be defined by SoCs with their own clocks. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
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@ -265,6 +265,9 @@ void clock_early_init(void);
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/* Returns a pointer to the clock source register for a peripheral */
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/* Returns a pointer to the clock source register for a peripheral */
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u32 *get_periph_source_reg(enum periph_id periph_id);
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u32 *get_periph_source_reg(enum periph_id periph_id);
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/* Returns a pointer to the given 'simple' PLL */
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struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid);
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/**
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/**
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* Given a peripheral ID and the required source clock, this returns which
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* Given a peripheral ID and the required source clock, this returns which
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* value should be programmed into the source mux for that peripheral.
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* value should be programmed into the source mux for that peripheral.
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@ -81,9 +81,18 @@ static struct clk_pll *get_pll(enum clock_id clkid)
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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(struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
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assert(clock_id_is_pll(clkid));
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assert(clock_id_is_pll(clkid));
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if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) {
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debug("%s: Invalid PLL\n", __func__);
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return NULL;
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}
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return &clkrst->crc_pll[clkid];
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return &clkrst->crc_pll[clkid];
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}
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}
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__weak struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
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{
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return NULL;
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}
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int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
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int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
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u32 *divp, u32 *cpcon, u32 *lfcon)
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u32 *divp, u32 *cpcon, u32 *lfcon)
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{
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{
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@ -110,7 +119,7 @@ unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
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u32 divp, u32 cpcon, u32 lfcon)
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u32 divp, u32 cpcon, u32 lfcon)
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{
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{
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struct clk_pll *pll = get_pll(clkid);
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struct clk_pll *pll = get_pll(clkid);
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u32 data;
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u32 misc_data, data;
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/*
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/*
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* We cheat by treating all PLL (except PLLU) in the same fashion.
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* We cheat by treating all PLL (except PLLU) in the same fashion.
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@ -119,8 +128,7 @@ unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
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* - DCCON is always 0, doesn't conflict
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* - DCCON is always 0, doesn't conflict
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* - M,N, P of PLLP values are ignored for PLLP
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* - M,N, P of PLLP values are ignored for PLLP
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*/
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*/
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data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
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misc_data = (cpcon << PLL_CPCON_SHIFT) | (lfcon << PLL_LFCON_SHIFT);
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writel(data, &pll->pll_misc);
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data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
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data = (divm << PLL_DIVM_SHIFT) | (divn << PLL_DIVN_SHIFT) |
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(0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
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(0 << PLL_BYPASS_SHIFT) | (1 << PLL_ENABLE_SHIFT);
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@ -129,7 +137,19 @@ unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
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data |= divp << PLLU_VCO_FREQ_SHIFT;
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data |= divp << PLLU_VCO_FREQ_SHIFT;
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else
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else
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data |= divp << PLL_DIVP_SHIFT;
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data |= divp << PLL_DIVP_SHIFT;
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writel(data, &pll->pll_base);
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if (pll) {
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writel(misc_data, &pll->pll_misc);
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writel(data, &pll->pll_base);
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} else {
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struct clk_pll_simple *pll = clock_get_simple_pll(clkid);
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if (!pll) {
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debug("%s: Uknown simple PLL %d\n", __func__, clkid);
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return 0;
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}
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writel(misc_data, &pll->pll_misc);
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writel(data, &pll->pll_base);
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}
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/* calculate the stable time */
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/* calculate the stable time */
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return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
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return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
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@ -431,6 +451,8 @@ unsigned clock_get_rate(enum clock_id clkid)
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return parent_rate;
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return parent_rate;
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pll = get_pll(clkid);
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pll = get_pll(clkid);
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if (!pll)
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return 0;
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base = readl(&pll->pll_base);
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base = readl(&pll->pll_base);
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/* Oh for bf_unpack()... */
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/* Oh for bf_unpack()... */
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