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rockchip: px30: enable spl-fifo-mode for both emmc and sdmmc on evb

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As part of loading trustedfirmware, the SPL is required to place portions
of code into the socs sram but the mmc controllers can only do dma
transfers into the regular memory, not sram.

The results of this are not directly visible in u-boot itself, but
manifest as security-relate cpu aborts during boot of for example Linux.

There were a number of attempts to solve this elegantly but so far
discussion is still ongoing, so to make the board at least boot correctly
put both mmc controllers into fifo-mode, which also circumvents the
issue for now.

Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
This commit is contained in:
Heiko Stuebner 2019-11-19 12:04:02 +01:00 committed by Kever Yang
parent c8dd0e42d7
commit 8019d32c47
1 changed files with 5 additions and 2 deletions
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7
arch/arm/dts/px30-evb-u-boot.dtsi
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@ -31,12 +31,15 @@
&sdmmc {
u-boot,dm-pre-reloc;
/* temporary till I find out why dma mode doesn't work */
fifo-mode;
/* mmc to sram can't do dma, prevent aborts transfering TF-A parts */
u-boot,spl-fifo-mode;
};
&emmc {
u-boot,dm-pre-reloc;
/* mmc to sram can't do dma, prevent aborts transfering TF-A parts */
u-boot,spl-fifo-mode;
};
&grf {