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PXA: fix MDREFR[APD] bit setting

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pxa_mem_setup macro use r6 to store CONFIG_SYS_MDREFR_VAL during memory
initialization. This reg is modified during execution of pxa_wait_ticks.
Later we use r6 to setup MDREFR[APD] bit. As result MDREFR[APD] is always
zero.

Signed-off-by: Mikhail Kshevetskiy <mikhail.kshevetskiy@gmail.com>
This commit is contained in:
Mikhail Kshevetskiy 2010-08-26 23:24:22 +04:00 committed by Wolfgang Denk
parent 11934fbf52
commit 80124df14f
1 changed files with 12 additions and 8 deletions
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20
arch/arm/include/asm/arch-pxa/macro.h
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@ -102,7 +102,11 @@
/*
* This macro sets up the Memory controller of the PXA2xx CPU
*
* Clobbered regs: r3, r4, r5
* WARNING: This macro uses internally r3 and r7 regs for MEMC_BASE
* and CONFIG_SYS_MDREFR_VAL correspondingly. Please do not
* use this regs for other purpose inside this macro.
*
* Clobbered regs: r3, r4, r5, r6, r7
*/
.macro pxa_mem_setup
/* This comes handy when setting MDREFR */
@ -157,7 +161,7 @@
bic r5, r5, #0xf00 /* MDREFR user config with zeroed DRI */
ldr r4, =CONFIG_SYS_MDREFR_VAL
mov r6, r4
mov r7, r4
lsl r4, #20
lsr r4, #20 /* Get a valid DRI field */
@ -187,12 +191,12 @@
* 6) Initialize SDRAM
*/
bic r6, #MDREFR_SLFRSH
str r6, [r3, #MDREFR_OFFSET]
bic r7, #MDREFR_SLFRSH
str r7, [r3, #MDREFR_OFFSET]
ldr r4, [r3, #MDREFR_OFFSET]
orr r6, #MDREFR_E1PIN
str r6, [r3, #MDREFR_OFFSET]
orr r7, #MDREFR_E1PIN
str r7, [r3, #MDREFR_OFFSET]
ldr r4, [r3, #MDREFR_OFFSET]
/*
@ -250,8 +254,8 @@
*/
ldr r4, [r3, #MDREFR_OFFSET]
and r6, r6, #MDREFR_APD
orr r4, r4, r6
and r7, r7, #MDREFR_APD
orr r4, r4, r7
str r4, [r3, #MDREFR_OFFSET]
ldr r4, [r3, #MDREFR_OFFSET]
.endm