mirror of
https://github.com/brain-hackers/u-boot-brain
synced 2024-09-29 08:00:26 +09:00
[PPC440SPe] Improve PCIe configuration space access
- correct configuration space mapping - correct bus numbering - better access to config space Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the first device on the first bus. We now allow to configure up to 16 buses; also, scanning for devices behind the PCIe-PCIe bridge is supported, so peripheral devices farther in hierarchy can be identified. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
This commit is contained in:
parent
15ee4734e4
commit
7f19139389
@ -67,9 +67,9 @@ tlbtabA:
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tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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@ -109,9 +109,9 @@ tlbtabB:
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tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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@ -392,7 +392,7 @@ int katmai_pcie_card_present(int port)
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static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
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static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
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void pcie_setup_hoses(void)
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void pcie_setup_hoses(int busno)
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{
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{
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struct pci_controller *hose;
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struct pci_controller *hose;
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int i, bus;
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int i, bus;
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@ -401,7 +401,7 @@ void pcie_setup_hoses(void)
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* assume we're called after the PCIX hose is initialized, which takes
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* assume we're called after the PCIX hose is initialized, which takes
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* bus ID 0 and therefore start numbering PCIe's from 1.
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* bus ID 0 and therefore start numbering PCIe's from 1.
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*/
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*/
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bus = 1;
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bus = busno;
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for (i = 0; i <= 2; i++) {
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for (i = 0; i <= 2; i++) {
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/* Check for katmai card presence */
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/* Check for katmai card presence */
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if (!katmai_pcie_card_present(i))
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if (!katmai_pcie_card_present(i))
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@ -418,8 +418,8 @@ void pcie_setup_hoses(void)
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hose = &pcie_hose[i];
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hose = &pcie_hose[i];
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hose->first_busno = bus;
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hose->first_busno = bus;
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hose->last_busno = bus;
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hose->last_busno = bus;
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bus++;
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hose->current_busno = bus;
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/* setup mem resource */
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/* setup mem resource */
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pci_set_region(hose->regions + 0,
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pci_set_region(hose->regions + 0,
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@ -443,6 +443,7 @@ void pcie_setup_hoses(void)
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* Config access can only go down stream
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* Config access can only go down stream
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*/
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*/
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hose->last_busno = pci_hose_scan(hose);
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hose->last_busno = pci_hose_scan(hose);
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bus = hose->last_busno + 1;
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#endif
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#endif
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}
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}
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}
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}
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@ -70,9 +70,9 @@ tlbtabA:
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tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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@ -112,9 +112,9 @@ tlbtabB:
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tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE0_CFGBASE, SZ_1K, 0x00100000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE1_CFGBASE, SZ_1K, 0x20100000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE2_CFGBASE, SZ_1K, 0x40100000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)
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@ -846,7 +846,7 @@ void yucca_setup_pcie_fpga_endpoint(int port)
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static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
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static struct pci_controller pcie_hose[3] = {{0},{0},{0}};
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void pcie_setup_hoses(void)
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void pcie_setup_hoses(int busno)
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{
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{
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struct pci_controller *hose;
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struct pci_controller *hose;
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int i, bus;
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int i, bus;
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@ -855,7 +855,7 @@ void pcie_setup_hoses(void)
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* assume we're called after the PCIX hose is initialized, which takes
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* assume we're called after the PCIX hose is initialized, which takes
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* bus ID 0 and therefore start numbering PCIe's from 1.
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* bus ID 0 and therefore start numbering PCIe's from 1.
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*/
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*/
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bus = 1;
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bus = busno;
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for (i = 0; i <= 2; i++) {
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for (i = 0; i <= 2; i++) {
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/* Check for yucca card presence */
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/* Check for yucca card presence */
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if (!yucca_pcie_card_present(i))
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if (!yucca_pcie_card_present(i))
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@ -874,8 +874,8 @@ void pcie_setup_hoses(void)
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hose = &pcie_hose[i];
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hose = &pcie_hose[i];
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hose->first_busno = bus;
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hose->first_busno = bus;
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hose->last_busno = bus;
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hose->last_busno = bus;
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bus++;
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hose->current_busno = bus;
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/* setup mem resource */
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/* setup mem resource */
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pci_set_region(hose->regions + 0,
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pci_set_region(hose->regions + 0,
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@ -899,6 +899,7 @@ void pcie_setup_hoses(void)
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* Config access can only go down stream
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* Config access can only go down stream
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*/
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*/
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hose->last_busno = pci_hose_scan(hose);
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hose->last_busno = pci_hose_scan(hose);
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bus = hose->last_busno + 1;
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#endif
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#endif
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}
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}
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}
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}
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@ -443,7 +443,7 @@ void pci_init_board(void)
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static struct pci_controller ppc440_hose = {0};
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static struct pci_controller ppc440_hose = {0};
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void pci_440_init (struct pci_controller *hose)
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int pci_440_init (struct pci_controller *hose)
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{
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{
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int reg_num = 0;
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int reg_num = 0;
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@ -459,7 +459,7 @@ void pci_440_init (struct pci_controller *hose)
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if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
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if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
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printf("PCI: SDR0_STRP1[PISE] not set.\n");
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printf("PCI: SDR0_STRP1[PISE] not set.\n");
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printf("PCI: Configuration aborted.\n");
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printf("PCI: Configuration aborted.\n");
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return;
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return -1;
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}
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}
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#elif defined(CONFIG_440GP)
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#elif defined(CONFIG_440GP)
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unsigned long strap;
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unsigned long strap;
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@ -468,7 +468,7 @@ void pci_440_init (struct pci_controller *hose)
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if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
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if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
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printf("PCI: CPC0_STRP1[PISE] not set.\n");
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printf("PCI: CPC0_STRP1[PISE] not set.\n");
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printf("PCI: Configuration aborted.\n");
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printf("PCI: Configuration aborted.\n");
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return;
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return -1;
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}
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}
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#endif
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#endif
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#endif /* CONFIG_DISABLE_PISE_TEST */
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#endif /* CONFIG_DISABLE_PISE_TEST */
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@ -477,7 +477,7 @@ void pci_440_init (struct pci_controller *hose)
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* PCI controller init
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* PCI controller init
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*--------------------------------------------------------------------------*/
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*--------------------------------------------------------------------------*/
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hose->first_busno = 0;
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hose->first_busno = 0;
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hose->last_busno = 0xff;
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hose->last_busno = 0;
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/* PCI I/O space */
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/* PCI I/O space */
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pci_set_region(hose->regions + reg_num++,
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pci_set_region(hose->regions + reg_num++,
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@ -515,7 +515,7 @@ void pci_440_init (struct pci_controller *hose)
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if (pci_pre_init (hose) == 0) {
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if (pci_pre_init (hose) == 0) {
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printf("PCI: Board-specific initialization failed.\n");
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printf("PCI: Board-specific initialization failed.\n");
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printf("PCI: Configuration aborted.\n");
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printf("PCI: Configuration aborted.\n");
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return;
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return -1;
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}
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}
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pci_register_hose( hose );
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pci_register_hose( hose );
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@ -578,13 +578,16 @@ void pci_440_init (struct pci_controller *hose)
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#endif
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#endif
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hose->last_busno = pci_hose_scan(hose);
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hose->last_busno = pci_hose_scan(hose);
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}
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}
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return hose->last_busno;
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}
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}
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void pci_init_board(void)
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void pci_init_board(void)
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{
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{
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pci_440_init (&ppc440_hose);
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int busno;
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busno = pci_440_init (&ppc440_hose);
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#if defined(CONFIG_440SPE)
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#if defined(CONFIG_440SPE)
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pcie_setup_hoses();
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pcie_setup_hoses(busno + 1);
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#endif
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#endif
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}
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}
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@ -40,6 +40,23 @@ enum {
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LNKW_X8 = 0x8
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LNKW_X8 = 0x8
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};
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};
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static u8* pcie_get_base(struct pci_controller *hose, unsigned int devfn)
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{
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u8 *base = (u8*)hose->cfg_data;
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/* use local configuration space for the first bus */
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if (PCI_BUS(devfn) == 0) {
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if (hose->cfg_data == (u8*)CFG_PCIE0_CFGBASE)
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base = (u8*)CFG_PCIE0_XCFGBASE;
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if (hose->cfg_data == (u8*)CFG_PCIE1_CFGBASE)
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base = (u8*)CFG_PCIE1_XCFGBASE;
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if (hose->cfg_data == (u8*)CFG_PCIE2_CFGBASE)
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base = (u8*)CFG_PCIE2_XCFGBASE;
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}
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return base;
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}
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static void pcie_dmer_disable(void)
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static void pcie_dmer_disable(void)
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{
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{
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mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE),
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mtdcr (DCRN_PEGPL_CFG(DCRN_PCIE0_BASE),
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@ -60,18 +77,35 @@ static void pcie_dmer_enable(void)
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mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA);
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mfdcr (DCRN_PEGPL_CFG(DCRN_PCIE2_BASE)) & ~GPL_DMER_MASK_DISA);
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}
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}
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static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
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static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
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int offset, int len, u32 *val) {
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int offset, int len, u32 *val) {
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u8 *address;
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*val = 0;
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*val = 0;
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/*
|
/*
|
||||||
* 440SPE implements only one function per port
|
* Bus numbers are relative to hose->first_busno
|
||||||
*/
|
*/
|
||||||
if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1)))
|
devfn -= PCI_BDF(hose->first_busno, 0, 0);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* NOTICE: configuration space ranges are currenlty mapped only for
|
||||||
|
* the first 16 buses, so such limit must be imposed. In case more
|
||||||
|
* buses are required the TLB settings in board/amcc/<board>/init.S
|
||||||
|
* need to be altered accordingly (one bus takes 1 MB of memory space).
|
||||||
|
*/
|
||||||
|
if (PCI_BUS(devfn) >= 16)
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
devfn = PCI_BDF(0,0,0);
|
/*
|
||||||
|
* Only single device/single function is supported for the primary and
|
||||||
|
* secondary buses of the 440SPe host bridge.
|
||||||
|
*/
|
||||||
|
if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
|
||||||
|
((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
address = pcie_get_base(hose, devfn);
|
||||||
offset += devfn << 4;
|
offset += devfn << 4;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -101,13 +135,24 @@ static int pcie_read_config(struct pci_controller *hose, unsigned int devfn,
|
|||||||
static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
|
static int pcie_write_config(struct pci_controller *hose, unsigned int devfn,
|
||||||
int offset, int len, u32 val) {
|
int offset, int len, u32 val) {
|
||||||
|
|
||||||
|
u8 *address;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* 440SPE implements only one function per port
|
* Bus numbers are relative to hose->first_busno
|
||||||
*/
|
*/
|
||||||
if (!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 1)))
|
devfn -= PCI_BDF(hose->first_busno, 0, 0);
|
||||||
|
|
||||||
|
/*
|
||||||
|
* Same constraints as in pcie_read_config().
|
||||||
|
*/
|
||||||
|
if (PCI_BUS(devfn) >= 16)
|
||||||
return 0;
|
return 0;
|
||||||
|
|
||||||
devfn = PCI_BDF(0,0,0);
|
if ((!((PCI_FUNC(devfn) == 0) && (PCI_DEV(devfn) == 0))) &&
|
||||||
|
((PCI_BUS(devfn) == 0) || (PCI_BUS(devfn) == 1)))
|
||||||
|
return 0;
|
||||||
|
|
||||||
|
address = pcie_get_base(hose, devfn);
|
||||||
offset += devfn << 4;
|
offset += devfn << 4;
|
||||||
|
|
||||||
/*
|
/*
|
||||||
@ -137,7 +182,7 @@ int pcie_read_config_byte(struct pci_controller *hose,pci_dev_t dev,int offset,u
|
|||||||
u32 v;
|
u32 v;
|
||||||
int rv;
|
int rv;
|
||||||
|
|
||||||
rv = pcie_read_config(hose, dev, offset, 1, &v);
|
rv = pcie_read_config(hose, dev, offset, 1, &v);
|
||||||
*val = (u8)v;
|
*val = (u8)v;
|
||||||
return rv;
|
return rv;
|
||||||
}
|
}
|
||||||
@ -794,12 +839,12 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
|
|||||||
volatile void *rmbase = NULL;
|
volatile void *rmbase = NULL;
|
||||||
|
|
||||||
pci_set_ops(hose,
|
pci_set_ops(hose,
|
||||||
pcie_read_config_byte,
|
pcie_read_config_byte,
|
||||||
pcie_read_config_word,
|
pcie_read_config_word,
|
||||||
pcie_read_config_dword,
|
pcie_read_config_dword,
|
||||||
pcie_write_config_byte,
|
pcie_write_config_byte,
|
||||||
pcie_write_config_word,
|
pcie_write_config_word,
|
||||||
pcie_write_config_dword);
|
pcie_write_config_dword);
|
||||||
|
|
||||||
switch (port) {
|
switch (port) {
|
||||||
case 0:
|
case 0:
|
||||||
@ -822,14 +867,9 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
|
|||||||
/*
|
/*
|
||||||
* Set bus numbers on our root port
|
* Set bus numbers on our root port
|
||||||
*/
|
*/
|
||||||
if (ppc440spe_revB()) {
|
out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
|
||||||
out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
|
out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
|
||||||
out_8((u8 *)mbase + PCI_SECONDARY_BUS, 1);
|
out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
|
||||||
out_8((u8 *)mbase + PCI_SUBORDINATE_BUS, 1);
|
|
||||||
} else {
|
|
||||||
out_8((u8 *)mbase + PCI_PRIMARY_BUS, 0);
|
|
||||||
out_8((u8 *)mbase + PCI_SECONDARY_BUS, 0);
|
|
||||||
}
|
|
||||||
|
|
||||||
/*
|
/*
|
||||||
* Set up outbound translation to hose->mem_space from PLB
|
* Set up outbound translation to hose->mem_space from PLB
|
||||||
@ -886,6 +926,29 @@ void ppc440spe_setup_pcie_rootpoint(struct pci_controller *hose, int port)
|
|||||||
in_le16((u16 *)(mbase + PCI_COMMAND)) |
|
in_le16((u16 *)(mbase + PCI_COMMAND)) |
|
||||||
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
|
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
|
||||||
printf("PCIE:%d successfully set as rootpoint\n",port);
|
printf("PCIE:%d successfully set as rootpoint\n",port);
|
||||||
|
|
||||||
|
/* Set Device and Vendor Id */
|
||||||
|
switch (port) {
|
||||||
|
case 0:
|
||||||
|
out_le16(mbase + 0x200, 0xaaa0);
|
||||||
|
out_le16(mbase + 0x202, 0xbed0);
|
||||||
|
break;
|
||||||
|
case 1:
|
||||||
|
out_le16(mbase + 0x200, 0xaaa1);
|
||||||
|
out_le16(mbase + 0x202, 0xbed1);
|
||||||
|
break;
|
||||||
|
case 2:
|
||||||
|
out_le16(mbase + 0x200, 0xaaa2);
|
||||||
|
out_le16(mbase + 0x202, 0xbed2);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
out_le16(mbase + 0x200, 0xaaa3);
|
||||||
|
out_le16(mbase + 0x202, 0xbed3);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Set Class Code to PCI-PCI bridge and Revision Id to 1 */
|
||||||
|
out_le32(mbase + 0x208, 0x06040001);
|
||||||
|
|
||||||
}
|
}
|
||||||
|
|
||||||
int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port)
|
int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port)
|
||||||
@ -963,8 +1026,8 @@ int ppc440spe_setup_pcie_endpoint(struct pci_controller *hose, int port)
|
|||||||
|
|
||||||
/* Enable I/O, Mem, and Busmaster cycles */
|
/* Enable I/O, Mem, and Busmaster cycles */
|
||||||
out_le16((u16 *)(mbase + PCI_COMMAND),
|
out_le16((u16 *)(mbase + PCI_COMMAND),
|
||||||
in_le16((u16 *)(mbase + PCI_COMMAND)) |
|
in_le16((u16 *)(mbase + PCI_COMMAND)) |
|
||||||
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
|
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
|
||||||
out_le16(mbase + 0x200,0xcaad); /* Setting vendor ID */
|
out_le16(mbase + 0x200,0xcaad); /* Setting vendor ID */
|
||||||
out_le16(mbase + 0x202,0xfeed); /* Setting device ID */
|
out_le16(mbase + 0x202,0xfeed); /* Setting device ID */
|
||||||
attempts = 10;
|
attempts = 10;
|
||||||
|
@ -275,7 +275,7 @@ void pciinfo (int, int);
|
|||||||
# endif
|
# endif
|
||||||
int is_pci_host (struct pci_controller *);
|
int is_pci_host (struct pci_controller *);
|
||||||
#if defined(CONFIG_440SPE)
|
#if defined(CONFIG_440SPE)
|
||||||
void pcie_setup_hoses(void);
|
void pcie_setup_hoses(int busno);
|
||||||
#endif
|
#endif
|
||||||
#endif
|
#endif
|
||||||
|
|
||||||
|
@ -66,11 +66,11 @@
|
|||||||
#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
|
#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
|
||||||
|
|
||||||
#define CFG_PCIE0_CFGBASE 0xc0000000
|
#define CFG_PCIE0_CFGBASE 0xc0000000
|
||||||
#define CFG_PCIE0_XCFGBASE 0xc0000400
|
#define CFG_PCIE1_CFGBASE 0xc1000000
|
||||||
#define CFG_PCIE1_CFGBASE 0xc0001000
|
#define CFG_PCIE2_CFGBASE 0xc2000000
|
||||||
#define CFG_PCIE1_XCFGBASE 0xc0001400
|
#define CFG_PCIE0_XCFGBASE 0xc3000000
|
||||||
#define CFG_PCIE2_CFGBASE 0xc0002000
|
#define CFG_PCIE1_XCFGBASE 0xc3001000
|
||||||
#define CFG_PCIE2_XCFGBASE 0xc0002400
|
#define CFG_PCIE2_XCFGBASE 0xc3002000
|
||||||
|
|
||||||
/* System RAM mapped to PCI space */
|
/* System RAM mapped to PCI space */
|
||||||
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
|
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
|
||||||
|
@ -68,11 +68,11 @@
|
|||||||
#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
|
#define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
|
||||||
|
|
||||||
#define CFG_PCIE0_CFGBASE 0xc0000000
|
#define CFG_PCIE0_CFGBASE 0xc0000000
|
||||||
#define CFG_PCIE0_XCFGBASE 0xc0000400
|
#define CFG_PCIE1_CFGBASE 0xc1000000
|
||||||
#define CFG_PCIE1_CFGBASE 0xc0001000
|
#define CFG_PCIE2_CFGBASE 0xc2000000
|
||||||
#define CFG_PCIE1_XCFGBASE 0xc0001400
|
#define CFG_PCIE0_XCFGBASE 0xc3000000
|
||||||
#define CFG_PCIE2_CFGBASE 0xc0002000
|
#define CFG_PCIE1_XCFGBASE 0xc3001000
|
||||||
#define CFG_PCIE2_XCFGBASE 0xc0002400
|
#define CFG_PCIE2_XCFGBASE 0xc3002000
|
||||||
|
|
||||||
/* System RAM mapped to PCI space */
|
/* System RAM mapped to PCI space */
|
||||||
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
|
#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
|
||||||
|
Loading…
Reference in New Issue
Block a user