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spi: cadence_qspi: Add quad write support
Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
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02f173ca15
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@ -256,7 +256,7 @@ static int cadence_spi_xfer(struct udevice *dev, unsigned int bitlen,
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break;
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break;
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case CQSPI_INDIRECT_WRITE:
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case CQSPI_INDIRECT_WRITE:
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err = cadence_qspi_apb_indirect_write_setup
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err = cadence_qspi_apb_indirect_write_setup
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(plat, priv->cmd_len, cmd_buf);
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(plat, priv->cmd_len, dm_plat->mode, cmd_buf);
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if (!err) {
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if (!err) {
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err = cadence_qspi_apb_indirect_write_execute
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err = cadence_qspi_apb_indirect_write_execute
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(plat, data_bytes, dout);
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(plat, data_bytes, dout);
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@ -60,7 +60,7 @@ int cadence_qspi_apb_indirect_read_setup(struct cadence_spi_platdata *plat,
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int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
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int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat,
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unsigned int rxlen, u8 *rxbuf);
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unsigned int rxlen, u8 *rxbuf);
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int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
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int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
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unsigned int cmdlen, const u8 *cmdbuf);
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unsigned int cmdlen, unsigned int tx_width, const u8 *cmdbuf);
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int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
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int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat,
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unsigned int txlen, const u8 *txbuf);
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unsigned int txlen, const u8 *txbuf);
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@ -77,6 +77,7 @@
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#define CQSPI_REG_WR_INSTR 0x08
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#define CQSPI_REG_WR_INSTR 0x08
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#define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
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#define CQSPI_REG_WR_INSTR_OPCODE_LSB 0
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#define CQSPI_REG_WR_INSTR_TYPE_DATA_LSB 16
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#define CQSPI_REG_DELAY 0x0C
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#define CQSPI_REG_DELAY 0x0C
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#define CQSPI_REG_DELAY_TSLCH_LSB 0
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#define CQSPI_REG_DELAY_TSLCH_LSB 0
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@ -686,7 +687,7 @@ failrd:
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/* Opcode + Address (3/4 bytes) */
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/* Opcode + Address (3/4 bytes) */
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int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
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int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
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unsigned int cmdlen, const u8 *cmdbuf)
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unsigned int cmdlen, unsigned int tx_width, const u8 *cmdbuf)
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{
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{
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unsigned int reg;
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unsigned int reg;
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unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
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unsigned int addr_bytes = cmdlen > 4 ? 4 : 3;
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@ -702,6 +703,10 @@ int cadence_qspi_apb_indirect_write_setup(struct cadence_spi_platdata *plat,
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/* Configure the opcode */
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/* Configure the opcode */
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reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
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reg = cmdbuf[0] << CQSPI_REG_WR_INSTR_OPCODE_LSB;
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if (tx_width & SPI_TX_QUAD)
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reg |= CQSPI_INST_TYPE_QUAD << CQSPI_REG_WR_INSTR_TYPE_DATA_LSB;
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writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
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writel(reg, plat->regbase + CQSPI_REG_WR_INSTR);
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/* Setup write address. */
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/* Setup write address. */
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