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Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86 

- Fix CMD_ACPI dependency in Kconfig
- Correct overflow in __udelay() in TSC timer driver
- Add a devicetree node for eMMC for Coral
- Minor improvements on image loading
- Reduce size of Samus image
This commit is contained in:
Tom Rini 2021-02-01 08:15:46 -05:00
parent d039975f07 77f898d040
commit 7ee6205a5f
16 changed files with 124 additions and 32 deletions
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6
arch/x86/cpu/acpi_gpe.c
View File

@ -4,6 +4,8 @@
* Written by Simon Glass <sjg@chromium.org>
*/
#define LOG_CATEGORY UCLASS_IRQ
#include <common.h>
#include <dm.h>
#include <irq.h>
@ -102,8 +104,8 @@ static const struct udevice_id acpi_gpe_ids[] = {
{ }
};
U_BOOT_DRIVER(acpi_gpe_drv) = {
.name = "acpi_gpe",
U_BOOT_DRIVER(intel_acpi_gpe) = {
.name = "intel_acpi_gpe",
.id = UCLASS_IRQ,
.of_match = acpi_gpe_ids,
.ops = &acpi_gpe_ops,

12
arch/x86/cpu/apollolake/spl.c
View File

@ -3,6 +3,8 @@
* Copyright 2019 Google LLC
*/
#define LOG_CATEGORY LOGC_BOOT
#include <common.h>
#include <binman_sym.h>
#include <bootstage.h>
@ -33,12 +35,11 @@ static int rom_load_image(struct spl_image_info *spl_image,
int ret;
spl_image->size = CONFIG_SYS_MONITOR_LEN; /* We don't know SPL size */
spl_image->entry_point = spl_phase() == PHASE_TPL ?
CONFIG_SPL_TEXT_BASE : CONFIG_SYS_TEXT_BASE;
spl_image->entry_point = spl_get_image_text_base();
spl_image->load_addr = spl_image->entry_point;
spl_image->os = IH_OS_U_BOOT;
spl_image->name = "U-Boot";
debug("Reading from mapped SPI %lx, size %lx", spl_pos, spl_size);
log_debug("Reading from mapped SPI %lx, size %lx\n", spl_pos, spl_size);
if (CONFIG_IS_ENABLED(SPI_FLASH_SUPPORT)) {
ret = uclass_find_first_device(UCLASS_SPI_FLASH, &dev);
@ -56,7 +57,8 @@ static int rom_load_image(struct spl_image_info *spl_image,
return ret;
}
spl_pos += map_base & ~0xff000000;
debug(", base %lx, pos %lx\n", map_base, spl_pos);
log_debug(", base %lx, pos %lx, load %lx\n", map_base, spl_pos,
spl_image->load_addr);
bootstage_start(BOOTSTAGE_ID_ACCUM_MMAP_SPI, "mmap_spi");
memcpy((void *)spl_image->load_addr, (void *)spl_pos, spl_size);
cpu_flush_l1d_to_l2();
@ -121,7 +123,7 @@ static int spl_fast_spi_load_image(struct spl_image_info *spl_image,
spl_image->os = IH_OS_U_BOOT;
spl_image->name = "U-Boot";
spl_pos &= ~0xff000000;
debug("Reading from flash %lx, size %lx\n", spl_pos, spl_size);
log_debug("Reading from flash %lx, size %lx\n", spl_pos, spl_size);
ret = spi_flash_read_dm(dev, spl_pos, spl_size,
(void *)spl_image->load_addr);
cpu_flush_l1d_to_l2();

12
arch/x86/cpu/u-boot-spl.lds
View File

@ -43,11 +43,23 @@ SECTIONS
__binman_sym_start = .;
KEEP(*(SORT(.binman_sym*)));
__binman_sym_end = .;
/*
* Force 32-byte alignment so that it lines up with the start of
* bss, which may have up to 32-byte alignment. This ensures
* that the end of the .bin file matches up with
* _image_binary_end or __bss_end - see board_fdt_blob_setup().
* The alignment of BSS depends on what is in it, so can range
* from 4 to 32 bytes.
*/
. = ALIGN(32);
}
_image_binary_end = .;
#if CONFIG_IS_ENABLED(SEPARATE_BSS)
. = 0x120000;
#endif
.bss (OVERLAY) : {
__bss_start = .;
*(.bss*)

6
arch/x86/dts/chromebook_coral.dts
View File

@ -575,6 +575,12 @@
acpi,name = "SDCD";
};
emmc: emmc@1c,0 {
reg = <0x0000e000 0 0 0 0>;
compatible = "intel,apl-emmc";
non-removable;
};
pch: pch@1f,0 {
reg = <0x0000f800 0 0 0 0>;
compatible = "intel,apl-pch";

34
arch/x86/include/asm/intel_gnvs.h
View File

@ -9,6 +9,7 @@
#ifndef _INTEL_GNVS_H_
#define _INTEL_GNVS_H_
#include <linux/bitops.h>
/*
* The chromeos_acpi portion of ACPI GNVS is assumed to live from offset
* 0x100 - 0x1000. When defining acpi_global_nvs, use check_member
@ -18,6 +19,11 @@
*/
#define GNVS_CHROMEOS_ACPI_OFFSET 0x100
enum {
BOOT_REASON_OTHER = 0,
BOOT_REASON_S3DIAG = 9
};
enum {
CHSW_RECOVERY_X86 = BIT(1),
CHSW_RECOVERY_EC = BIT(2),
@ -25,6 +31,22 @@ enum {
CHSW_FIRMWARE_WP = BIT(9),
};
enum {
RECOVERY_REASON_NONE = 0,
RECOVERY_REASON_ME = 1
};
enum {
ACTIVE_ECFW_RO = 0,
ACTIVE_ECFW_RW = 1
};
enum {
BINF_RECOVERY = 0,
BINF_RW_A = 1,
BINF_RW_B = 2
};
enum {
FIRMWARE_TYPE_AUTO_DETECT = -1,
FIRMWARE_TYPE_RECOVERY = 0,
@ -40,14 +62,14 @@ struct __packed chromeos_acpi_gnvs {
u32 active_main_fw; /* 04 (0=recovery, 1=A, 2=B) */
u32 activeec_fw; /* 08 (0=RO, 1=RW) */
u16 switches; /* 0c CHSW */
u8 vbt4[256]; /* 0e HWID */
u8 vbt5[64]; /* 10e FWID */
u8 vbt6[64]; /* 14e FRID - 275 */
u8 hwid[256]; /* 0e HWID */
u8 fwid[64]; /* 10e FWID */
u8 frid[64]; /* 14e FRID - 275 */
u32 main_fw_type; /* 18e (2 = developer mode) */
u32 vbt8; /* 192 recovery reason */
u32 vbt9; /* 196 fmap base address */
u32 recovery_reason; /* 192 recovery reason */
u32 fmap_base; /* 196 fmap base address */
u8 vdat[3072]; /* 19a VDAT space filled by verified boot */
u32 vbt10; /* d9a smbios bios version */
u32 fwid_ptr; /* d9a smbios bios version */
u32 mehh[8]; /* d9e management engine hash */
u32 ramoops_base; /* dbe ramoops base address */
u32 ramoops_len; /* dc2 ramoops length */

10
arch/x86/include/asm/zimage.h
View File

@ -62,6 +62,16 @@ struct boot_params *load_zimage(char *image, unsigned long kernel_size,
int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
ulong initrd_addr, ulong initrd_size, ulong cmdline_force);
/**
* zimage_dump() - Dump the metadata of a zimage
*
* This shows all available information in a zimage that has been loaded.
*
* @base_ptr: Pointer to the boot parameters, typically at address
* DEFAULT_SETUP_BASE
*/
void zimage_dump(struct boot_params *base_ptr);
void setup_video(struct screen_info *screen_info);
void setup_efi_info(struct efi_info *efi_info);

2
arch/x86/lib/spl.c
View File

@ -115,8 +115,8 @@ static int x86_spl_init(void)
}
#ifndef CONFIG_SYS_COREBOOT
# ifndef CONFIG_TPL
memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start);
# ifndef CONFIG_TPL
/* TODO(sjg@chromium.org): Consider calling cpu_init_r() here */
ret = interrupt_init();

7
arch/x86/lib/tpl.c
View File

@ -111,7 +111,12 @@ int spl_spi_load_image(void)
void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
{
debug("Jumping to U-Boot SPL at %lx\n", (ulong)spl_image->entry_point);
debug("Jumping to %s at %lx\n", spl_phase_name(spl_next_phase()),
(ulong)spl_image->entry_point);
#ifdef DEBUG
print_buffer(spl_image->entry_point, (void *)spl_image->entry_point, 1,
0x20, 0);
#endif
jump_to_spl(spl_image->entry_point);
hang();
}

33
arch/x86/lib/zimage.c
View File

@ -109,8 +109,11 @@ static void build_command_line(char *command_line, int auto_boot)
if (env_command_line)
strcat(command_line, env_command_line);
printf("Kernel command line: \"%s\"\n", command_line);
#ifdef DEBUG
printf("Kernel command line:");
puts(command_line);
printf("\n");
#endif
}
static int kernel_magic_ok(struct setup_header *hdr)
@ -354,7 +357,8 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot,
build_command_line(cmd_line, auto_boot);
ret = bootm_process_cmdline(cmd_line, max_size, BOOTM_CL_ALL);
if (ret) {
printf("Cmdline setup failed (err=%d)\n", ret);
printf("Cmdline setup failed (max_size=%x, bootproto=%x, err=%d)\n",
max_size, bootproto, ret);
return ret;
}
printf("Kernel command line: \"");
@ -600,19 +604,12 @@ static void show_loader(struct setup_header *hdr)
printf("\n");
}
int do_zboot_dump(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
void zimage_dump(struct boot_params *base_ptr)
{
struct boot_params *base_ptr = state.base_ptr;
struct setup_header *hdr;
const char *version;
int i;
if (argc > 1)
base_ptr = (void *)simple_strtoul(argv[1], NULL, 16);
if (!base_ptr) {
printf("No zboot setup_base\n");
return CMD_RET_FAILURE;
}
printf("Setup located at %p:\n\n", base_ptr);
print_num64("ACPI RSDP addr", base_ptr->acpi_rsdp_addr);
@ -688,6 +685,20 @@ int do_zboot_dump(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
print_num("Handover offset", hdr->handover_offset);
if (get_boot_protocol(hdr, false) >= 0x215)
print_num("Kernel info offset", hdr->kernel_info_offset);
}
static int do_zboot_dump(struct cmd_tbl *cmdtp, int flag, int argc,
char *const argv[])
{
struct boot_params *base_ptr = state.base_ptr;
if (argc > 1)
base_ptr = (void *)simple_strtoul(argv[1], NULL, 16);
if (!base_ptr) {
printf("No zboot setup_base\n");
return CMD_RET_FAILURE;
}
zimage_dump(base_ptr);
return 0;
}

3
cmd/Kconfig
View File

@ -84,7 +84,8 @@ menu "Info commands"
config CMD_ACPI
bool "acpi"
default y if ACPIGEN
depends on ACPIGEN
default y
help
List and dump ACPI tables. ACPI (Advanced Configuration and Power
Interface) is used mostly on x86 for providing information to the

6
common/spl/spl.c
View File

@ -144,6 +144,12 @@ ulong spl_get_image_size(void)
binman_sym(ulong, u_boot_any, size);
}
ulong spl_get_image_text_base(void)
{
return spl_phase() == PHASE_TPL ? CONFIG_SPL_TEXT_BASE :
CONFIG_SYS_TEXT_BASE;
}
/*
* Weak default function for board specific cleanup/preparation before
* Linux boot. Some boards/platforms might not need it, so just provide

1
configs/chromebook_samus_defconfig
View File

@ -54,6 +54,7 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_REGMAP=y
CONFIG_SYSCON=y
# CONFIG_ACPIGEN is not set
CONFIG_CPU=y
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_DW=y

2
drivers/timer/tsc_timer.c
View File

@ -372,7 +372,7 @@ void __udelay(unsigned long usec)
u64 now = get_ticks();
u64 stop;
stop = now + usec * get_tbclk_mhz();
stop = now + (u64)usec * get_tbclk_mhz();
while ((int64_t)(stop - get_ticks()) > 0)
#if defined(CONFIG_QEMU) && defined(CONFIG_SMP)

9
include/acpi/acpi_device.h
View File

@ -171,10 +171,11 @@ enum acpi_gpio_polarity {
* @io_restrict: I/O restriction setting
* @polarity: GPIO polarity
*
* Note that GpioIo doesn't have any means of Active Low / High setting, so a
* _DSD must be provided to mitigate this.
* Note that GpioIo() doesn't have any means of Active Low / High setting, so a
* _DSD must be provided to mitigate this. This parameter does not make sense
* for GpioInt() since it has its own means to define it.
*
* GpioIo doesn't properly communicate the initial state of the output pin,
* GpioIo() doesn't properly communicate the initial state of the output pin,
* thus Linux assumes the simple rule:
*
* Pull Bias Polarity Requested...
@ -184,7 +185,7 @@ enum acpi_gpio_polarity {
* assuming non-active (Polarity = !Pull Bias)
*
* Down Low as low, assuming active
* Down High as high, assuming non-active
* Down High as low, assuming non-active
* Up Low as high, assuming non-active
* Up High as high, assuming active
*

3
include/configs/chromebook_samus.h
View File

@ -15,6 +15,9 @@
#include <configs/x86-common.h>
#include <configs/x86-chromebook.h>
/* We can rely on running natively, and this saves code size */
#undef CONFIG_BIOSEMU
#undef CONFIG_STD_DEVICES_SETTINGS
#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,i8042-kbd,serial\0" \
"stdout=vidconsole,serial\0" \

10
include/spl.h
View File

@ -254,6 +254,16 @@ ulong spl_get_image_pos(void);
*/
ulong spl_get_image_size(void);
/**
* spl_get_image_text_base() - get the text base of the next phase
*
* This returns the address that the next stage is linked to run at, i.e.
* CONFIG_SPL_TEXT_BASE or CONFIG_SYS_TEXT_BASE
*
* @return text-base address
*/
ulong spl_get_image_text_base(void);
/**
* spl_load_simple_fit_skip_processing() - Hook to allow skipping the FIT
* image processing during spl_load_simple_fit().